Electronic device

Abstract

The utility model provides an electronic device comprising a substrate and at least one first input / output pad, each first pad is coupled to the substrate through an assembly, each assembly comprises a first well and a second well, the first well is located in the second well, the second well is located in the substrate, the substrate and the first well are doped with a first conductive type, and the first conductive type is doped with a second conductive type. The first well is doped with a first conductivity type, the second well is doped with a second conductivity type opposite to the first conductivity type, and each component is configured such that a threshold voltage of a diode formed by the first well and the second well is lower than a threshold voltage of a diode formed by the second well and the substrate when the first conductivity type is type P, or lower than a threshold voltage of a diode formed by the second well and the substrate when the first conductivity type is type N; the threshold voltage is higher than the threshold voltage of a diode formed by the second well and the substrate.

Description

[0001] Cross-references to related applications

[0002] This application is a translation of and claims priority to French patent application No. 2400632 entitled “Dispositifélectronique”, filed on January 23, 2024, which is hereby incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices, and more specifically to input and output connections of electronic devices. Background Technology

[0004] In a semiconductor electronic device that receives an external voltage, the reference voltage is, for example, the voltage that biases a substrate thereto.

[0005] In some electronic devices, applying a voltage below a reference voltage causes leakage, while applying a voltage above the reference voltage does not. In other electronic devices, applying a voltage above the reference voltage causes leakage, while applying a voltage below the reference voltage does not. Utility Model Content

[0006] The embodiments overcome all or some of the disadvantages of known electronic devices.

[0007] An embodiment provides an electronic device including a substrate and at least one first input / output pad, each first input / output pad being coupled to the substrate via a component, each component including first and second wells, the first well being located in a second well, the second well being located in the substrate, the substrate and the first well of each component being doped with a first conductivity type, the second well of each component being doped with a second conductivity type opposite to the first conductivity type, each component being configured such that the threshold voltage of a diode formed by the first and second wells of the component is: (i) lower than the threshold voltage of a diode formed by the second well and the substrate when the first conductivity type is type P, or (ii) higher than the threshold voltage of a diode formed by the second well and the substrate when the first conductivity type is type N.

[0008] According to an embodiment, the first well of each component is coupled to the substrate through an element outside the substrate.

[0009] According to an embodiment, the first well of each component is coupled to the substrate via a wire element.

[0010] According to an embodiment, the device includes at least two first input / output pads.

[0011] According to an embodiment, the first well of each component is separated from the substrate by a second well of the same component.

[0012] According to an embodiment, the device includes a second input / output pad coupled to a substrate via a component, the second pad being configured to receive a reference voltage.

[0013] According to the embodiment, the reference voltage is zero potential.

[0014] According to an embodiment, the first input / output pad is coupled to the electronic circuit.

[0015] According to an embodiment, the electronic circuit includes a bipolar transistor. Attached Figure Description

[0016] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of this disclosure with reference to the accompanying drawings, in which specific embodiments are given in an illustrative rather than restrictive manner, wherein:

[0017] Figure 1 An electronic device according to an embodiment is shown; and

[0018] Figure 2 schematically shown Figure 1 The device. Detailed Implementation

[0019] Similar features in the various figures are indicated by similar reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0020] For clarity, only detailed illustrations and descriptions are provided for the steps and elements useful for understanding the described embodiments.

[0021] Unless otherwise specified, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0022] In the following description, when referring to terms that define absolute position (such as the terms "front", "back", "top", "low", "left", "right", etc.), or terms that define relative position (such as the terms "upper", "lower", "upper part", "lower part", etc.), or terms that define direction (such as the terms "horizontal", "vertical", etc.), they refer to the orientation of the accompanying drawings unless otherwise specified.

[0023] Unless otherwise specified, the expressions “about,” “approximately,” “substantially,” and “about” indicate addition or subtraction of 10%, preferably 5%.

[0024] Figure 1 An electronic device 10 according to an embodiment is shown.

[0025] The device 10 corresponds for example to an electronic chip. The device 10 comprises a semiconductor substrate 12. The substrate 12 is for example made of silicon. The substrate 12 is doped with a first conductivity type, for example P-type.

[0026] The device 10 comprises at least one electronic circuit 14. The circuit 14 is for example configured to perform at least one function. The circuit 14 is for example a power management circuit. More precisely, the device 10 comprises electronic components forming the circuit 14. The electronic components of the circuit 14 are for example formed on the inside and on the top of the substrate 12. The device 10 is for example an electronic control device intended to be integrated into an electrical, electromechanical or optoelectronic equipment. The device 10 is for example intended to be integrated into an industrial equipment, a household appliance or an automotive equipment, for controlling such equipment. The device 10 is for example suitable for controlling a device via a wired bus of LIN or CAN type. The device 10 is for example suitable for controlling an equipment according to the IEC61131-2 standard.

[0027] The circuit 14 is coupled to at least one input / output pad 16, preferably an input pad. In Figure 1 In the example, the circuit 14 is connected to two input / output pads 16a and 16b. Each of the two input / output pads 16 is for example configured to receive an input voltage. Similarly, the circuit 14 is configured to receive an input voltage. For example, at least one pad 16 is coupled, preferably connected, to a terminal of a transistor of the circuit 14, for example a bipolar transistor, a MOSFET transistor or another type of transistor.

[0028] The device 10 also comprises an input / output pad 16c. The pad 16c is configured to receive a reference voltage, for example ground. The pad 16c is for example configured to receive a zero potential.

[0029] Each input pad 16 is also coupled to the substrate 12 via a component 18. More specifically, the pad 16a is coupled to the substrate 12 through a component 18a. The pad 16b is coupled to the substrate 12 through a component 18b. The pad 16c is coupled to the substrate 12 through a component 18c. Preferably, the device 10 does not comprise an input / output pad directly connected to the substrate 12.

[0030] Each component 18 comprises a first well 20. The well is located in the substrate 12. The well 20 is preferably flush with the upper surface of the substrate 12. The well 20 is made of a semiconductor material, for example the same material as the substrate 12. The well 20 is doped with a conductivity type opposite to that of the substrate 12. The well 20 is for example N-doped.

[0031] Each component 18 also includes a well 22 within the well 20. The well 22 is preferably flush with the upper surface of the well 20. The upper surface of the substrate 12 and the upper surfaces of the wells 20 and 22 are, for example, coplanar. The well 22 is, for example, completely surrounded by the well 20, except for its upper surface. The well 22 is completely separated from the substrate 12 by the well 20. The well 22 is made of a semiconductor material (e.g., the same material as the substrate 12 and the well 20). The well 22 is doped with a conductivity type opposite to the conductivity type of the well 20 (i.e., the same conductivity type as the substrate 12). The well 22 is, for example, P-type doped.

[0032] Thus, the component 18a includes wells 20 and 22 (denoted with reference numerals 20a and 22a), such as described previously. The component 18b includes wells 20 and 22 (denoted with reference numerals 20b and 22b), such as described previously. The component 18c includes wells 20 and 22 (denoted with reference numerals 20c and 22c), such as described previously.

[0033] Each component 18 also includes a contact 24. The contact 24 is located in the well 20 of the same component 18. The contact 24, for example, corresponds to a region of the well 20 of the same component that is more heavily doped than the rest of the well 20. The contact 24 is coupled (preferably connected) to the pad 16 associated with the component 18 of the contact 24. The contact 24 of at least some of the components 18 (e.g., all components except the component 18c) is, for example, coupled (preferably connected) to the circuit 14. Thus, the well 20 of each component 18 is biased to the voltage delivered on the pad 16 associated with the component 18.

[0034] Each component 18 also includes a contact 26. The contact 26 is located in the well 22 of the same component 18. The contact 26, for example, corresponds to a region of the well 22 of the same component that is more heavily doped than the rest of the well 22.

[0035] Each component 18 also includes a contact 28. The contact 28 is located in the substrate 12, for example, around the well 20. The contact 28, for example, corresponds to a region of the substrate 12 (e.g., a region of the substrate around the well 20) that is more heavily doped than the rest of the substrate 12.

[0036] The regions forming the contacts 26 and 28 of the same component 18 are coupled (preferably connected) by a connection element external to the substrate 12. For example, the regions forming the contacts 26 and 28 of the same component 18 are coupled (preferably connected) by a wire connection element 30 (e.g., a metal wire).

[0037] In Figure 1In the case of device 10, component 18a includes contact portions 24, 26, and 28 indicated by reference numerals 24a, 26a, and 28a, and a connecting element 30 indicated by reference numeral 30a, as described above. Component 18b includes contact portions 24, 26, and 28 indicated by reference numerals 24b, 26b, and 28b, and a connecting element 30 indicated by reference numeral 30b, as described above. Component 18c includes contact portions 24, 26, and 28 indicated by reference numerals 24c, 26c, and 28c, and a connecting element 30 indicated by reference numeral 30c, as described above.

[0038] A PN junction located between wells 20 and 22 of the same component 18 (i.e., a PN junction formed at the interface between wells 20 and 22 of the same component 18) forms a diode 32. Similarly, a PN junction located between well 20 of the component and the substrate 12 surrounding the component 18 (i.e., a PN junction formed at the interface between well 20 of the component and the substrate 12 surrounding the component 18) forms a so-called parasitic diode 34. For illustration, diodes 32 and 34 in... Figure 1 They are represented schematically by their symbols.

[0039] exist Figure 1 In the example shown, the doping levels of substrate 12 and wells 20 and 22 are selected such that the saturation current of diode 32 of component 18 is at least ten times greater than the saturation current of diode 34 of the same component. For example, the PN junction between wells 20 and 22 of the same component 18 is configured to be abrupt, while the junction between well 20 and substrate 12 of this component is configured to be more gradually varied.

[0040] Figure 2 schematically shown Figure 1 Device 10.

[0041] and Figure 1 similar, Figure 2 The substrate 12 and the circuit 14 located in the substrate 12 are shown. Figure 2 The input / output pads 16 are also shown; more precisely, Figure 1 Pads 16a, 16b, and 16c in the diagram. (The rest of the text appears to be incomplete and requires further context.) Figure 1 Similarly, pad 16c is coupled to a source of the reference voltage (e.g., outside the substrate 12).

[0042] and Figure 1 Similarly, at least some pads 16 (e.g., pads 16 other than the one receiving the reference voltage) are coupled (preferably connected) to circuit 14. Each pad 16 is also coupled to substrate 12 via component 18. Figure 2 In this configuration, each component 18 includes diode 32 and diode 34.

[0043] The diodes 32 and 34 of the component 18 are coupled in parallel between the nodes 36 and 38. Thus, the diodes 32a and 34a are coupled in parallel between the nodes 36a and 38a. The diodes 32b and 34b are coupled in parallel between the nodes 36b and 38b. The diodes 32c and 34c are coupled in parallel between the nodes 36c and 38c. Each node 36 is coupled, preferably connected, to a pad 16 associated with the component 18. Each node 38 is coupled, preferably connected, to the substrate 12. Thus, the cathodes of the diodes 32 and 34 of the component are coupled, preferably connected, together and to the pads 16 associated with the component. The anodes of the diodes 32 and 34 of the component are coupled, preferably connected, together and to the substrate 12.

[0044] The cathodes of the diodes 32 and 34 of the component 18 are formed by the well 20 of the component 18. The anode of the diode 34 of the component is formed by the substrate 12. The anode of the diode 32 is formed by the well 22. The coupling between the anode of the diode 32 and the substrate 12 is formed by the connecting element 30 of the component.

[0045] As described in connection with Figure 1 the threshold voltage of the diode 32 is lower than the threshold voltage of the diode 34. Thus, during operation of the device 10, the substrate 12 is biased to the lowest voltage among the voltages received on the pads 16. Thus, the ground of the circuit 14 is the lowest voltage among the voltages delivered on the pads 16. The potential difference between the pads 16, e.g. between the pads 16a or 16b and the pad 16c, remains the same. However, all voltages are positive voltages.

[0046] It can have been chosen not to provide the component 18 in the device 10, so that the pad 16c is coupled directly to the substrate and the other pads are coupled directly to the circuit 14. However, in this case, when a negative voltage is applied to the circuit 14 and in particular to the bipolar transistor, a high leakage current will be formed between the bipolar transistor and the substrate.

[0047] According to other embodiments (not shown), the conductivity types can be reversed. Thus, in this other embodiment, the substrate 12 is N-doped, the well 20 is P-doped, and the well 22 is N-doped. The diode 32 is then configured and the doping levels of the wells 20, 22 and the substrate 12 are configured so that the saturation current of the diode 32 is at least ten times larger than the saturation current of the diode 34. This embodiment is for example suitable for a device in which the application of a positive voltage produces a more significant leakage current than the application of a negative voltage. For example, the device comprises an NPN-type bipolar transistor in the circuit 14.

[0048] One advantage of the described embodiments is that the device generates less leakage current.

[0049] Various embodiments and variants have been described. It will be appreciated by those skilled in the art that certain features of the various embodiments and variants can be combined, and other variants will occur to those skilled in the art.

[0050] Finally, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art, based on the functional indications given above.

Claims

1. An electronic device, characterized in that, include: substrate; as well as At least one first input / output pad, each first input / output pad being coupled to a substrate via a component, each component including a first well and a second well, the first well being located in the second well and the second well being located in the substrate, the substrate and the first well of each component being doped with a first conductivity type, the second well of each component being doped with a second conductivity type opposite to the first conductivity type, each component being configured such that the threshold voltage of the diode formed by the first well and the second well of the component is: (i) lower than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type P, or (ii) higher than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type N.

2. The apparatus according to claim 1, characterized in that, The first well of each component is coupled to the substrate through an external element.

3. The apparatus according to claim 2, characterized in that, The first well of each component is coupled to the substrate via a wire element.

4. The apparatus according to claim 1, characterized in that, The device includes at least two first input / output pads.

5. The apparatus according to claim 1, characterized in that, The first well of each component is separated from the substrate by the second well of the same component.

6. The apparatus according to claim 1, characterized in that, The device includes a second input / output pad coupled to a substrate via a component, the second pad being configured to receive a reference voltage.

7. The apparatus according to claim 6, characterized in that, The reference voltage is zero potential.

8. The apparatus according to claim 1, characterized in that, The at least one first input / output pad is coupled to the electronic circuit.

9. The apparatus according to claim 8, characterized in that, The electronic circuitry includes bipolar transistors.

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