Light-emitting chip substrate and display substrate

Abstract

The utility model discloses a light-emitting chip substrate and a display substrate, and relates to the technical field of display. The light-emitting chip substrate comprises a supporting substrate, a bonding supporting layer, a chip supporting layer and a plurality of light-emitting chips. The chip supporting layer comprises a plurality of chip supporting parts, virtual connection parts and connection parts. The multiple light-emitting chips in the light-emitting chip substrate are transferred to the driving back plate at a time, multiple times of transfer are not needed, and the transfer efficiency is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a light emitting chip substrate and a display substrate. BACKGROUND

[0002] The display substrate comprises a driving back plate and a plurality of light emitting chips connected with the driving back plate, wherein the driving back plate can provide driving signals for the light emitting chips to make the light emitting chips emit light, thereby realizing display.

[0003] In the related art, the plurality of light emitting chips included in the display substrate need to be transferred to the driving back plate by a mass transfer method, and the number of transfer at each time is small, so multiple transfers are needed, which is low in efficiency. CONTENT OF THE UTILITY MODEL

[0004] The present application provides a light emitting chip substrate and a display substrate, which can solve the problem of low transfer efficiency. The technical solution is as follows:

[0005] In one aspect, a light emitting chip substrate is provided, comprising:

[0006] a support substrate;

[0007] a bonding support layer located on one side of the support substrate, the bonding support layer being a first grid structure composed of a plurality of first grids;

[0008] a chip support layer located on the side of the bonding support layer away from the support substrate, the chip support layer comprising a plurality of chip support portions, a plurality of virtual connection portions, and a connection portion; wherein the plurality of chip support portions are arranged correspondingly to the plurality of first grids, the orthographic projection of the chip support portion on the support substrate is located within the orthographic projection of the corresponding first grid on the support substrate, each chip support portion corresponds to a plurality of virtual connection portions, one end of each virtual connection portion is connected with the corresponding chip support portion, and the other end is connected with the connection portion, and the chip support portion and the virtual connection portion are both spaced apart from the support substrate; the connection portion is a second grid structure composed of a plurality of second grids, the orthographic projection of the connection portion on the support substrate overlaps with the orthographic projection of the bonding support layer on the support substrate, and the connection portion is connected with the bonding support layer;

[0009] a plurality of light emitting chips located on the side of the chip support layer away from the support substrate and arranged correspondingly to the plurality of chip support portions, the orthographic projection of each light emitting chip on the support substrate is located within the orthographic projection of the corresponding chip support portion on the support substrate, and the area of the orthographic projection of the chip support portion on the support substrate is greater than the area of the orthographic projection of the light emitting chip on the support substrate.

[0010] Optionally, the light emitting chip is a vertical structure light emitting chip; the chip support layer comprises: a bonding metal layer and a reflecting metal layer stacked in a direction away from the support substrate;

[0011] The part of the bonding metal layer belonging to the connecting part is used for bonding connection with the bonding support layer, and the part of the reflecting metal layer belonging to the chip support part is used for reflecting light emitted by the light emitting chip.

[0012] Optionally, the light emitting chip comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in a direction away from the support substrate in sequence;

[0013] The first semiconductor layer comprises P-doped gallium nitride, the second semiconductor layer comprises N-doped gallium nitride, and the light emitting layer comprises a multi-quantum well layer.

[0014] Optionally, the area of the cross section of the light emitting chip parallel to the surface of the support substrate gradually decreases with the increase of the distance between the light emitting chip and the support substrate.

[0015] Optionally, the shape of the cross section of the light emitting chip is trapezoidal, and the cross section is perpendicular to the surface of the support substrate.

[0016] The length of the side of the trapezoid away from the support substrate is less than the length of the side of the trapezoid close to the support substrate.

[0017] Optionally, the light emitting chip is a flip-chip structure light emitting chip; the chip support layer comprises: a bonding metal layer;

[0018] The part of the bonding metal layer belonging to the connecting part is used for bonding connection with the bonding support layer.

[0019] Optionally, the light emitting chip comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in a direction away from the support substrate in sequence; the first semiconductor layer comprises P-doped gallium nitride, the second semiconductor layer comprises N-doped gallium nitride, and the light emitting layer comprises a multi-quantum well layer.

[0020] The light emitting layer and the second semiconductor layer expose a part of the first semiconductor layer, the light emitting chip further comprises a first electrode and a second electrode, the first electrode is electrically connected with the part of the first semiconductor layer exposed by the light emitting layer and the second semiconductor layer, and the second electrode is electrically connected with the second semiconductor layer.

[0021] Optionally, the virtual connecting part is in a strip structure, and the width of the virtual connecting part ranges from 3 microns to 10 microns.

[0022] Optionally, the shape of the second grid, the shape of the light emitting chip and the shape of the chip support portion are all square shapes.

[0023] The side length of the second grid is 1.5 to 3 times the side length of the light emitting chip.

[0024] The side length of the chip support portion is 1 to 2 times the side length of the light emitting chip.

[0025] In another aspect, a display substrate is provided, the display substrate comprising:

[0026] A driving back plate comprising a substrate, a driving unit layer and a plurality of driving connection portions, the driving unit layer comprising a plurality of driving units corresponding to the plurality of driving connection portions, the driving connection portions and the driving units being electrically connected;

[0027] A plurality of light emitting chips located at one side of the driving back plate, the plurality of light emitting chips and the plurality of driving connection portions being correspondingly arranged, the light emitting chip comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked in sequence in a direction away from the driving back plate, the first semiconductor layer comprising P-doped gallium nitride, the second semiconductor layer comprising N-doped gallium nitride, and the light emitting layer comprising a multi-quantum well layer;

[0028] and a chip support portion located between the light emitting chip and the driving connection portion.

[0029] The display substrate comprises the plurality of light emitting chips obtained by bonding the light emitting chip substrate and the driving back plate as described in the above aspect; the area of the cross section of the light emitting chip parallel to the reference plane gradually decreases as the distance between the light emitting chip and the driving back plate increases, the reference plane being parallel to the surface of the driving unit layer close to the driving connection portion;

[0030] The orthographic projection of the light emitting chip on the reference plane is located within the orthographic projection of the chip support portion on the reference plane, and the area of the orthographic projection of the chip support portion on the reference plane is greater than the area of the orthographic projection of the light emitting chip on the reference plane.

[0031] Optionally, the chip support portion comprises a bonding metal layer and a reflective metal layer, the bonding metal layer being closer to the driving connection portion than the reflective metal layer, the bonding metal layer in the chip support portion being connected to the driving connection portion, and the reflective metal layer in the chip support portion being used for reflecting light emitted by the light emitting chip.

[0032] In yet another aspect, a method for preparing a light emitting chip substrate is provided, the method comprising:

[0033] Obtaining a plurality of light emitting chip sub-substrates, the light emitting chip sub-substrates comprising a chip substrate, an epitaxial layer, and a chip support film;

[0034] Obtaining a support substrate, the support substrate comprising a support substrate and a bonding support layer on one side of the support substrate, the bonding support layer being a first grid structure composed of a plurality of first grids;

[0035] Bonding the chip support film in the plurality of light emitting chip sub-substrates and the bonding support layer in the support substrate;

[0036] Removing the chip substrate in the plurality of light emitting chip sub-substrates;

[0037] Patterning the epitaxial layer in the plurality of light emitting chip sub-substrates to obtain a plurality of light emitting chips;

[0038] Patterning the chip support film to obtain a chip support layer, the chip support layer comprising a plurality of chip support portions, a virtual connection portion, and a connection portion; the plurality of chip support portions and the plurality of first grids are correspondingly arranged, and correspondingly arranged with the plurality of light emitting chips, the orthographic projection of the chip support portion on the support substrate is located within the orthographic projection of the corresponding first grid on the support substrate, the orthographic projection of each light emitting chip on the support substrate is located within the orthographic projection of the corresponding chip support portion on the support substrate, the area of the orthographic projection of the chip support portion on the support substrate is greater than the area of the orthographic projection of the light emitting chip on the support substrate; each chip support portion corresponds to a plurality of virtual connection portions, one end of each virtual connection portion is connected to the corresponding chip support portion, the other end is connected to the connection portion, and the chip support portion and the virtual connection portion are both spaced apart from the support substrate; the connection portion is a second grid structure composed of a plurality of second grids, the orthographic projection of the connection portion on the support substrate and the orthographic projection of the bonding support layer on the support substrate overlap, and the connection portion and the bonding support layer are connected.

[0039] Optionally, the light emitting chip is a vertical structure light emitting chip; the chip support layer comprises a bonding metal layer and a reflective metal layer stacked in a direction away from the support substrate; the part of the bonding metal layer belonging to the connection portion is used for bonding connection with the bonding support layer, and the part of the reflective metal layer belonging to the chip support portion is used for reflecting light emitted by the light emitting chip;

[0040] The light emitting chip includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in a direction away from the support substrate, the first semiconductor layer, the light emitting layer, and the second semiconductor layer are sequentially stacked in the direction away from the support substrate, the first semiconductor layer includes P-doped gallium nitride, the second semiconductor layer includes N-doped gallium nitride, and the light emitting layer includes a multi-quantum well layer.

[0041] Optionally, the light emitting chip is a flip chip; the chip support layer includes a bonding metal layer for bonding connection with the bonding support layer.

[0042] The light emitting chip includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in a direction away from the support substrate, the first semiconductor layer, the light emitting layer, and the second semiconductor layer are sequentially stacked in the direction away from the support substrate, the first semiconductor layer includes P-doped gallium nitride, the second semiconductor layer includes N-doped gallium nitride, and the light emitting layer includes a multi-quantum well layer.

[0043] The light emitting layer and the second semiconductor layer expose a part of the first semiconductor layer, the light emitting chip further includes a first electrode and a second electrode, the first electrode is electrically connected with the light emitting layer and the part of the first semiconductor layer exposed by the light emitting layer and the second semiconductor layer, and the second electrode is electrically connected with the second semiconductor layer.

[0044] In another aspect, a method for manufacturing a display substrate is provided, the method includes:

[0045] Obtaining the light emitting chip substrate in the above aspect or the light emitting chip substrate manufactured by the method in the above aspect, the light emitting chip substrate includes a plurality of light emitting chips.

[0046] Obtaining a driving backplane, the driving backplane includes a substrate, a driving unit layer, and a plurality of driving connection parts, the driving unit layer includes a plurality of driving units corresponding to the plurality of driving connection parts, and the driving connection parts are electrically connected with the driving units.

[0047] Bonding the light emitting chip substrate and the driving backplane, so that the driving connection parts are connected with the light emitting chips.

[0048] Optionally, the bonding the light emitting chip substrate and the driving backplane includes:

[0049] Obtaining a pickup chip substrate, the pickup chip substrate includes a pickup substrate and a plurality of pickup parts on the pickup substrate, the number of the pickup parts is less than or equal to the number of the light emitting chips in the light emitting chip substrate, and the plurality of pickup parts correspond to at least part of the light emitting chips in the light emitting chip substrate.

[0050] bonding connection of the light emitting chip substrate and the pick-up chip substrate to pick up the multiple light emitting chips corresponding to the multiple pick-up parts on the pick-up chip substrate;

[0051] bonding connection of the pick-up chip substrate with the multiple light emitting chips picked up and the driving back plate.

[0052] The technical scheme provided by the application has at least the following beneficial effects:

[0053] The application provides a light emitting chip substrate and a display substrate. The light emitting chip substrate comprises a support substrate, a bonding support layer, a chip support layer and multiple light emitting chips. The chip support layer comprises multiple chip support parts, a virtual connection part and a connection part. The multiple light emitting chips in the light emitting chip substrate are transferred to the driving back plate at one time, without multiple transfer, and the transfer efficiency is high. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical scheme in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0055] Figure 1 is a partial cross-sectional schematic view of a light emitting chip substrate provided by the embodiments of the application;

[0056] Figure 2 is a partial top view of a light emitting chip substrate provided by the embodiments of the application;

[0057] Figure 3 is a partial top view of a bonding support layer provided by the embodiments of the application;

[0058] Figure 4 is a partial top view of a chip support layer provided by the embodiments of the application;

[0059] Figure 5 is a cross-sectional schematic view and a top view of a single light emitting chip provided by the embodiments of the application;

[0060] Figure 6 is a partial cross-sectional schematic view of another light emitting chip substrate provided by the embodiments of the application;

[0061] Figure 7 is a partial cross-sectional schematic view of still another light emitting chip substrate provided by the embodiments of the application;

[0062] Figure 8 is a partial cross-sectional schematic view of a display substrate provided by the embodiments of the application;

[0063] Figure 9 is a flowchart of a preparation method of a light emitting chip substrate provided by an embodiment of the present application;

[0064] Figure 10 is a schematic diagram of a light emitting chip sub substrate provided by an embodiment of the present application;

[0065] Figure 11 is a schematic diagram of a support substrate provided by an embodiment of the present application;

[0066] Figure 12 is a schematic diagram of a support substrate and a light emitting chip sub substrate bonded together provided by an embodiment of the present application;

[0067] Figure 13 is a schematic diagram of a chip substrate removed provided by an embodiment of the present application;

[0068] Figure 14 is a schematic diagram of an epitaxial layer etched provided by an embodiment of the present application;

[0069] Figure 15 is a schematic diagram of a current transmission layer formed provided by an embodiment of the present application;

[0070] Figure 16 is a flowchart of another preparation method of a light emitting chip substrate provided by an embodiment of the present application;

[0071] Figure 17 is a schematic diagram of another epitaxial layer etched provided by an embodiment of the present application;

[0072] Figure 18 is a schematic diagram of a first electrode and a second electrode formed provided by an embodiment of the present application;

[0073] Figure 19 is a flowchart of a preparation method of a display substrate provided by an embodiment of the present application;

[0074] Figure 20 is a schematic diagram of a drive backplane provided by an embodiment of the present application;

[0075] Figure 21 is a schematic diagram of a chip substrate picked up provided by an embodiment of the present application;

[0076] Figure 22 is a schematic diagram of a light emitting chip picked up by a chip substrate provided by an embodiment of the present application;

[0077] Figure 23 is a schematic diagram of a display substrate formed provided by an embodiment of the present application;

[0078] Figure 24is a schematic diagram of driving the bonding connection of a back plate and a light emitting chip substrate provided by an embodiment of the present application.

[0079] Figure 25 is another partial cross-sectional schematic diagram of a display substrate provided by an embodiment of the present application. DETAILED DESCRIPTION

[0080] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0081] The display market is currently booming, and as consumers' demand for various display products such as notebook computers, smart phones, televisions, tablet computers, smart watches and fitness wristbands continues to rise, more new display products will emerge in the future. Micro light emitting diode (Micro LED) display technology has the advantages of low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, ultra-power saving, long service life, and high efficiency, and is considered to be the most competitive next-generation display technology.

[0082] The mass transfer technology of Micro LED is also a hot spot of attention and research in the industry at present, and is usually realized by using a stamp type or fluid self-alignment. Since the size of the epitaxial wafer is relatively small, the number of light emitting chips obtained by using the epitaxial wafer is also small. When the light emitting chips are transferred to the driving back plate, the number of light emitting chips transferred at a time is small, and multiple transfers are required, which is low in efficiency.

[0083] The area of single transfer is small, multiple transfer is required, and how to efficiently and low-costly transfer the LED to the display substrate becomes a difficulty in the current MLED display field.

[0084] Figure 1 is a partial cross-sectional schematic diagram of a light emitting chip substrate provided by an embodiment of the present application. Figure 2 is a partial top view of a light emitting chip substrate provided by an embodiment of the present application. Referring to Figure 1 and Figure 2 It can be seen that the light emitting chip substrate 100 comprises a support substrate 101, a bonding support layer 102, a chip support layer 103 and a plurality of light emitting chips 104. Optionally, the support substrate 101 can be glass. The light emitting chip 104 can be a Micro LED.

[0085] Figure 3 is a partial top view of a bonding support layer provided by an embodiment of the present application. In combination with Figure 1 and Figure 3The bonding support layer 102 is located on one side of the support substrate 101, and the bonding support layer 102 can be a first mesh structure formed by a plurality of first meshes. In the first mesh structure, Figure 3 The shape of the first mesh can be a quadrilateral, for example, a square.

[0086] Referring to Figure 1 The chip support layer 103 is located on the side of the bonding support layer 102 away from the support substrate 101. Figure 4 is a partial top view of a chip support layer provided by an embodiment of the present application. Referring to Figure 4 It can be seen that the chip support layer 103 includes a plurality of chip support portions 1031, a plurality of virtual connection portions 1032, and a plurality of connection portions 1033.

[0087] The plurality of chip support portions 1031 and the plurality of first meshes are arranged correspondingly, and the orthographic projection of each chip support portion 1031 on the support substrate 101 is located within the orthographic projection of the corresponding first mesh on the support substrate 101. Each chip support portion 1031 corresponds to a plurality of virtual connection portions 1032, one end of each virtual connection portion 1032 is connected to the corresponding chip support portion 1031, and the other end is connected to the connection portion 1033. The chip support portion 1031 and the virtual connection portion 1032 are both spaced apart from the support substrate 101. For example, Figure 3 and Figure 4 In the embodiment, each chip support portion 1031 corresponds to four virtual connection portions 1032.

[0088] The connection portion 1033 is a second mesh structure formed by a plurality of second meshes, and the shape and size of the second mesh structure match those of the first mesh structure. The orthographic projection of the connection portion 1033 on the support substrate 101 overlaps the orthographic projection of the bonding support layer 102 on the support substrate 101, and the connection portion 1033 is connected to the bonding support layer 102.

[0089] In the embodiment, because the bonding support layer 102 has a certain height and the bonding support layer 102 is connected to the connection portion 1033, the chip support portion 1031 and the virtual connection portion 1032 that are not connected to the bonding support layer 102 are both spaced apart from the support substrate 101 due to the presence of the bonding support layer 102. That is, the chip support portion 1031 and the virtual connection portion 1032 are arranged in a suspended manner relative to the support substrate 101.

[0090] In combination with Figure 1 and Figure 2The plurality of light emitting chips 104 are located on the side of the chip supporting layer 103 away from the supporting substrate 101, and are arranged in correspondence with the plurality of chip supporting portions 1031. The orthographic projection of each light emitting chip 104 on the supporting substrate 101 is located within the orthographic projection of the corresponding chip supporting portion 1031 on the supporting substrate 101. The area of the orthographic projection of the chip supporting portion 1031 on the supporting substrate 101 is greater than the area of the orthographic projection of the light emitting chip 104 on the supporting substrate 101.

[0091] In the embodiment of the present application, the chip supporting portion 1031 can be a bonding pad for bonding the subsequent light emitting chip 104 and the driving backboard 201. Because the chip supporting portion 1031 has a large area, the difficulty of bonding the subsequent light emitting chip 104 and the driving backboard 201 can be reduced.

[0092] Further, the supporting substrate 101 in the light emitting chip substrate can correspond to the driving backboard 201, so that the plurality of light emitting chips 104 can be transferred to the driving backboard 201 at one time when the light emitting chip 104 in the light emitting chip substrate is transferred to the driving backboard 201, without the need for multiple transfers, and the transfer efficiency is high. In the process of transferring the plurality of light emitting chips 104 to the driving backboard 201, the virtual connecting portion 1032 can be broken under the action of the transfer pressure, thereby separating the chip supporting portion 1031 and the connecting portion 1033. After the light emitting chip 104 is transferred to the driving backboard 201, the supporting substrate 101 and the bonding supporting layer 102 connected to the connecting portion 1033 are removed.

[0093] In summary, the embodiment of the present application provides a light emitting chip substrate, which includes a supporting substrate, a bonding supporting layer, a chip supporting layer, and a plurality of light emitting chips. The chip supporting layer includes a plurality of chip supporting portions, a virtual connecting portion, and a connecting portion. The plurality of light emitting chips in the light emitting chip substrate can be transferred to the driving backboard at one time, without the need for multiple transfers, and the transfer efficiency is high.

[0094] In the embodiment of the present application, the virtual connecting portion 1032 can have a strip-shaped structure, and the width of the virtual connecting portion 1032 can range from 3 μm to 10 μm. The width of the virtual connecting portion 1032 in this range can ensure that the virtual connecting portion 1032 can be broken when the subsequent light emitting chip 104 and the driving backboard 201 are bonded, so as to separate the chip supporting portion 1031 and the connecting portion 1033.

[0095] Optionally, the shape of the second grid, the shape of the light emitting chip 104, and the shape of the chip supporting portion 1031 can all be square. Further, the center of the orthographic projection of the second grid on the supporting substrate 101, the center of the orthographic projection of the light emitting chip 104 on the supporting substrate 101, and the center of the orthographic projection of the chip supporting portion 1031 on the supporting substrate 101 can overlap.

[0096] Optionally, referring to Figure 5 , the side length d3 of the second grid is 1.5 times to 3 times of the side length d1 of the light emitting chip 104, for example, the side length d3 of the second grid can be 2 times or 2.5 times of the side length d1 of the light emitting chip 104. The side length d2 of the chip support part 1031 can be 1 times to 2 times of the side length d1 of the light emitting chip 104, for example, the side length d2 of the chip support part 1031 can be 1.5 times of the side length d1 of the light emitting chip 104.

[0097] In the embodiments of the present application, in addition to being square, the first grid and the second grid can also be rectangular or other polygons. The embodiments of the present application do not limit the shape of the first grid and the second grid.

[0098] Referring to Figure 5 It can be seen that each chip support part 1031 can correspond to four virtual connecting parts 1032. The four virtual connecting parts 1032 correspond to the four corners of the square, respectively. One end of each virtual connecting part 1032 is connected with the corner of one second grid of the connecting part 1033, and the other end is connected with the corner of the chip support part 1031.

[0099] Of course, each chip support part 1031 can correspond to other number of virtual connecting parts 1032, and the connection position of the virtual connecting part 1032 can also be adjusted appropriately. For example, one end of the virtual connecting part 1032 can be connected with the side of one grid of the connecting part 1033, and the other end can be connected with the side of the chip support part 1031. The embodiments of the present application do not specifically limit the number of virtual connecting parts 1032 corresponding to the chip support part 1031 and the connection position of the virtual connecting part 1032.

[0100] As an optional implementation manner, referring to Figures 1 to 5 , the light emitting chip 104 is a vertical structure light emitting chip 104. The chip support layer 103 includes a bonding metal layer a1 and a reflecting metal layer a2 which are stacked in the direction away from the support substrate 101. The part of the bonding metal layer a1 belonging to the connecting part 1033 is used to be bonded and connected with the bonding support layer 102. For example, when the part of the bonding metal layer a1 belonging to the connecting part 1033 is bonded and connected with the bonding support layer 102, an IMC intermetallic compound can be generated. The part of the reflecting metal layer a2 belonging to the chip support part 1031 is used to reflect the light emitted by the light emitting chip 104, thereby improving the light emitting efficiency of the light emitting chip 104 and improving the light utilization rate of the light emitting chip.

[0101] Optionally, the bonding metal layer a1 and the reflecting metal layer a2 can be prepared by sputtering (Sputter), electroplating or evaporation. The thickness of the bonding metal layer a1 can range from 1 μm (micron) to 3 μm, and the thickness of the reflecting metal layer a2 can range from 100 nm (nanometer) to 500 nm.

[0102] Optionally, the material of the bonding metal layer a1 can be at least one of silver (Ag), copper (Cu) and gold (Au). The bonding support layer 102 is bonded to the bonding metal layer a1, and the bonding support layer 102 can include two layers of bonding materials stacked together. The bonding material close to the support substrate 101 can be at least one of silver (Ag), copper (Cu) and gold (Au), and the bonding material far from the support substrate 101 can be at least one of indium (In) and tin (Sn).

[0103] Optionally, the bonding material close to the support substrate 101 can be the same material as the material of the bonding metal layer a1, or can be a different material. Furthermore, the material of the bonding metal layer a1 (or the bonding material close to the support substrate 101 in the bonding support layer 102) and the bonding material close to the support substrate 101 in the bonding support layer 102 can be combined in any manner.

[0104] Optionally, the material of the reflective metal layer a2 can be a high-reflectivity metal material, such as at least one of aluminum (Al) and silver (Ag), and preferably the material of the reflective metal layer a2 can be silver.

[0105] Figure 6 is another partial cross-sectional schematic view of a light-emitting substrate provided by an embodiment of the present application. Referring to Figure 6 , the light-emitting chip 104 includes a first semiconductor layer 1041, a light-emitting layer 1042 and a second semiconductor layer 1043 stacked together in the direction away from the support substrate 101. The first semiconductor layer 1041 includes P-doped gallium nitride (GaN), and can be denoted as P-GaN. The second semiconductor layer 1043 includes N-doped gallium nitride, and can be denoted as N-GaN. The light-emitting layer 1042 includes a multi-quantum well layer (MQW).

[0106] That is, in the light-emitting chip substrate 100, the first semiconductor layer 1041 (P-GaN) is closer to the support substrate 101 than the second semiconductor layer 1043 (N-GaN). In this case, the first semiconductor layer 1041 can be connected to the driving unit in the driving backboard 201 through the chip support part 1031 (bonding pad) in the future, so that the driving unit provides a driving signal for the first semiconductor layer 1041. In addition, after the light-emitting chip 104 is bonded to the driving backboard 201 to obtain a display substrate, the second semiconductor layer 1043 of the plurality of light-emitting chips 104 can be connected to the common electrode in the driving backboard 201, so that the driving backboard 201 provides a common signal for the second semiconductor layer 1043 of the plurality of light-emitting chips 104.

[0107] In the embodiment of the present application, the first semiconductor layer 1041, the light emitting layer 1042 and the second semiconductor layer 1043 of the plurality of light emitting chips 104 in the light emitting chip substrate 100 are obtained by etching the first semiconductor film b21, the light emitting film b22 and the second semiconductor film b23 on the side of the chip support layer 103 away from the support substrate 101 after the bonding support layer 102 and the chip support layer 103 are connected. In this case, since the second semiconductor film b23 is farther away from the support substrate 101, the second semiconductor film b23 is etched first in the etching process, and then the light emitting film b22 and the first semiconductor film b21 are etched in sequence.

[0108] Due to the influence of the etching process itself, the size of the film layer obtained by etching the film first is smaller, and the size of the film layer obtained by etching the film last is larger. Therefore, the area of the cross section of the light emitting chip 104 parallel to the surface of the support substrate 101 gradually decreases with the increase of the distance between the light emitting chip 104 and the support substrate 101.

[0109] Optionally, the orthographic projection of the second semiconductor layer 1043 on the support substrate 101 is located within the orthographic projection of the light emitting layer 1042 on the support substrate 101, and the area of the orthographic projection of the second semiconductor layer 1043 on the support substrate 101 is smaller than the area of the orthographic projection of the light emitting layer 1042 on the support substrate 101. The orthographic projection of the light emitting layer 1042 on the support substrate 101 is located within the orthographic projection of the first semiconductor layer 1041 on the support substrate 101, and the area of the orthographic projection of the light emitting layer 1042 on the support substrate 101 is smaller than the area of the orthographic projection of the first semiconductor layer 1041 on the support substrate 101.

[0110] With reference to Figure 6 , the cross section of the light emitting chip 104 is trapezoidal, and the cross section is perpendicular to the surface of the support substrate 101. The length of the side of the trapezoid away from the support substrate 101 is smaller than the length of the side of the trapezoid close to the support substrate 101. In this case, after the light emitting chip 104 is bonded to the driving backboard 201 through the chip support part 1031 (bonding pad), the shape of the light emitting chip 104 relative to the driving backboard 201 is a positive trapezoid.

[0111] With reference to Figure 1 and Figure 6 , the light emitting chip substrate 100 further comprises a current transmission layer 105 formed on the side of the second semiconductor layer 1043 of the light emitting chip 104 away from the support substrate 101. The material of the current transmission layer 105 can be indium tin oxide (ITO). The current transmission layer 105 can also be referred to as a transparent electrode.

[0112] As another optional implementation, with reference to Figure 7The light emitting chip 104 can be a flip chip. The chip support layer 103 can include a bonding metal layer a1, and a portion of the bonding metal layer a1 belonging to the connecting portion 1033 is used to be bonded to the bonding support layer 102. For example, when the portion of the bonding metal layer a1 belonging to the connecting portion 1033 is bonded to the bonding support layer 102, an IMC intermetallic compound can be generated.

[0113] Optionally, the bonding metal layer a1 and the reflective metal layer a2 can be prepared by sputtering, electroplating or evaporation. The thickness of the bonding metal layer a1 can range from 1 μm to 3 μm, and the thickness of the reflective metal layer a2 can range from 100 nm to 500 nm.

[0114] Optionally, the material of the bonding metal layer a1 can be at least one of silver (Ag), copper (Cu) and gold (Au). The bonding support layer 102 can be made of at least one of indium (In) and tin (Sn). In addition, the material of the bonding metal layer a1 and the material of the bonding support layer 102 can be combined arbitrarily.

[0115] Reference is made to FIG. 1, which is a schematic diagram of a light emitting chip 104 according to an embodiment of the present application. Figure 7 The light emitting chip 104 includes a first semiconductor layer 1041, a light emitting layer 1042 and a second semiconductor layer 1043, which are stacked in sequence in a direction away from the support substrate 101. The first semiconductor layer 1041 includes P-doped gallium nitride (GaN), and can be denoted as P-GaN. The second semiconductor layer 1043 includes N-doped gallium nitride, and can be denoted as N-GaN. The light emitting layer 1042 includes a multi-quantum well layer (MQW). That is, in the light emitting chip 104, the first semiconductor layer 1041 (P-GaN) is closer to the support substrate 101 than the second semiconductor layer 1043 (N-GaN).

[0116] Reference is made to FIG. 1, which is a schematic diagram of a light emitting chip 104 according to an embodiment of the present application. Figure 7 The light emitting layer 1042 and the second semiconductor layer 1043 can expose a portion of the first semiconductor layer 1041. The light emitting chip 104 can further include a first electrode 1044 and a second electrode 1045. The first electrode 1044 is electrically connected to the portion of the first semiconductor layer 1041 exposed by the light emitting layer 1042 and the second semiconductor layer 1043, and the second electrode 1045 is electrically connected to the second semiconductor layer 1043.

[0117] In this case, the first semiconductor layer 1041 can be connected to the driving unit in the driving backboard 201 through the first electrode 1044, and the driving unit can provide a driving signal for the first semiconductor layer 1041. The second semiconductor layer 1043 can be connected to the common electrode in the driving backboard 201 through the second electrode 1045, and the driving backboard 201 can provide a common signal for the second semiconductor layer 1043 of the plurality of light emitting chips 104. In addition, after the light emitting chip 104 is bonded to the driving backboard 201 to obtain the display substrate, the chip support part 1031 on the side of the first semiconductor layer 1041 away from the light emitting layer 1042 can be removed.

[0118] If the light emitting chip is a flip chip, the second semiconductor layer 1043, the light emitting layer 1042, and the first semiconductor layer 1041 in the light emitting chip 104 are stacked in the direction away from the support substrate 101. The first semiconductor layer 1041 includes P-doped gallium nitride (GaN), and the first semiconductor layer 1041 can be denoted as P-GaN. The second semiconductor layer 1043 includes N-doped gallium nitride, and the second semiconductor layer 1043 can be denoted as N-GaN. The light emitting layer 1042 includes a multi-quantum well layer (MQW). That is, in the light emitting chip substrate 100, the first semiconductor layer 1041 (P-GaN) is farther away from the support substrate 101 than the second semiconductor layer 1043 (N-GaN).

[0119] In summary, the embodiment of the present application provides a light emitting chip substrate including a support substrate, a bonding support layer, a chip support layer, and a plurality of light emitting chips. The chip support layer includes a plurality of chip support parts, a virtual connection part, and a connection part. The plurality of light emitting chips in the light emitting chip substrate are transferred to the driving backboard at one time, without the need for multiple transfers, and the transfer efficiency is relatively high.

[0120] Figure 8 is a partial cross-sectional schematic view of a display substrate provided by an embodiment of the present application. The display substrate can be obtained by transferring the plurality of light emitting chips 104 in the light emitting chip substrate provided by the above-mentioned embodiments to the driving backboard 201. Referring to Figure 8 , the display substrate 200 includes the driving backboard 201 and the plurality of light emitting chips 104 on one side of the driving backboard 201. The plurality of light emitting chips 104 included in the display substrate 200 can be obtained by bonding the light emitting chip substrate provided by the above-mentioned embodiments to the driving backboard 201.

[0121] The driving backboard 201 includes a substrate substrate 2011, a driving unit layer 2012, and a plurality of driving connection parts 2013. The driving unit layer 2012 includes a plurality of driving units corresponding to the plurality of driving connection parts 2013, and the driving connection part 2013 and the driving unit are electrically connected. Optionally, the substrate substrate 2011 can be glass.

[0122] Optionally, the driving connection part 2013 includes two layers of bonding materials which are stacked, and the layer of bonding material close to the substrate 2011 can be at least one of silver (Ag), copper (Cu) and gold (Au), and the layer of bonding material far from the substrate 2011 can be at least one of indium (In) and tin (Sn).

[0123] The plurality of light emitting chips 104 are located on one side of the driving backboard 201, and the plurality of light emitting chips 104 and the plurality of driving connection parts 2013 are correspondingly arranged. The light emitting chip 104 includes a first semiconductor layer 1041, a light emitting layer 1042 and a second semiconductor layer 1043 which are stacked in turn in the direction away from the driving backboard 201. The first semiconductor layer 1041 includes P-doped gallium nitride (GaN), and the first semiconductor layer 1041 can be denoted as P-GaN. The second semiconductor layer 1043 includes N-doped gallium nitride, and the second semiconductor layer 1043 can be denoted as N-GaN. The light emitting layer 1042 includes a multi-quantum well layer (MQW). That is, in the display substrate 200, the first semiconductor layer 1041 (P-GaN) is closer to the driving backboard 201 than the second semiconductor layer 1043 (N-GaN).

[0124] In the case that the light emitting chip 104 is a vertical structure light emitting chip 104, with reference to Figure 8 The display substrate further includes a chip support part 1031 located between the light emitting chip 104 and the driving connection part 2013. The area of the cross section of the light emitting chip 104 parallel to the reference plane gradually decreases as the distance between the light emitting chip 104 and the driving backboard 201 increases. The reference plane is parallel to the surface of the driving unit layer 2012 close to the driving connection part 2013. The orthographic projection of the light emitting chip 104 on the reference plane is located within the orthographic projection of the chip support part 1031 on the reference plane, and the area of the orthographic projection of the chip support part 1031 on the reference plane is greater than the area of the orthographic projection of the light emitting chip 104 on the reference plane.

[0125] That is, the chip support part 1031 can be a bonding pad when the light emitting chip 104 and the driving backboard 201 are bonded. Since the area of the chip support part 1031 is large, the bonding difficulty when the light emitting chip 104 and the driving backboard 201 are bonded subsequently can be reduced.

[0126] Optionally, the chip support part 1031 includes a bonding metal layer a1 and a reflective metal layer a2. The bonding metal layer a1 is close to the driving connection part 2013 relative to the reflective metal layer a2, the bonding metal layer a1 in the chip support part 1031 is connected with the driving connection part 2013, and the reflective metal layer a2 in the chip support part 1031 is used to reflect the light emitted by the light emitting chip 104.

[0127] In summary, the display substrate provided by the embodiments of the present application includes a driving backplane and a plurality of light emitting chips. The plurality of light emitting chips can be transferred from the light emitting chip substrate to the driving backplane at one time, without the need for multiple transfers, thereby improving the transfer efficiency.

[0128] Figure 9 is a flowchart of a method for manufacturing a light emitting chip substrate provided by the embodiments of the present application. Take a light emitting chip 104 as a vertical structure light emitting chip 104 as an example. Referring to Figure 9 , the method includes the following steps.

[0129] In step S101, a plurality of light emitting chip sub-substrates are obtained.

[0130] In the embodiments of the present application, referring to Figure 10 , the light emitting chip sub-substrate can include a chip substrate b1, an epitaxial layer b2, and a chip support film b3. The chip substrate b1 and the epitaxial layer b2 in the light emitting chip sub-substrate can be an epitaxial wafer of a silicon-based (or sapphire) substrate. The light emitting chip sub-substrate can be a chip support film b3 prepared on the basis of the epitaxial wafer.

[0131] Optionally, the epitaxial layer b2 can include a second semiconductor film b23, a light emitting film b22, and a first semiconductor film b21 stacked in sequence in a direction away from the chip substrate b1. The first semiconductor film b21 includes P-doped gallium nitride, the second semiconductor film b23 includes N-doped gallium nitride, and the light emitting film b22 includes a multi-quantum well (MQW) film. The first semiconductor film b21 is used to form a first semiconductor layer 1041 in the light emitting chip 104, the second semiconductor film b23 is used to form a second semiconductor layer 1043 in the light emitting chip 104, and the light emitting film b22 is used to form a light emitting layer 1042 in the light emitting chip 104.

[0132] Optionally, the chip support film b3 can include a bonding metal film b31 and a reflective metal film b32 stacked in a direction away from the chip substrate b1. The bonding metal film b31 and the reflective metal film b32 can be prepared by sputtering (Sputter), electroplating, or evaporation. The thickness of the bonding metal film b31 can range from 1 μm to 3 μm, and the thickness of the reflective metal film b32 can range from 100 nm to 500 nm.

[0133] The material of the reflective metal film b32 can be a high-reflectivity metal material, such as at least one of aluminum (Al) and silver (Ag), and preferably the material of the reflective metal film b32 can be silver. The material of the bonding metal film b31 can be at least one of silver (Ag), copper (Cu), and gold (Au).

[0134] In step S102, a support substrate is obtained.

[0135] With reference to Figure 11 The support substrate includes a support substrate 101 and a bonding support layer 102 on one side of the support substrate 101. The bonding support layer 102 is a first grid-shaped structure formed by a plurality of first grids. The area of the support substrate 101 can be greater than the area of the light-emitting chip sub-substrate. Optionally, the support substrate 101 can be glass.

[0136] Optionally, the support substrate can be a grid-shaped bonding support layer 102 prepared on glass by electroplating, sputtering or lift-off.

[0137] In step S103, the chip support film in the plurality of light-emitting chip sub-substrates and the bonding support layer in the support substrate are bonded and connected.

[0138] In the embodiments of the present application, with reference to Figure 12 The plurality of light-emitting chip sub-substrates can be bonded and connected to the support substrate by a bonding device. During the process of thermal compression bonding, the bonding support layer 102 in the support substrate reacts with the bonding metal film b31 in the light-emitting chip sub-substrate to form an IMC intermetallic compound.

[0139] Optionally, the support substrate 101 can correspond to bonding of a plurality of light-emitting chip sub-substrates. The bonding metal film b31 in the chip support film b3 and the bonding support layer 102 are bonded and connected. The material of the bonding metal film b31 can be at least one of indium (In) and tin (Sn). Moreover, the material of the bonding metal film b31 and the material of the bonding support layer 102 can be arbitrarily combined.

[0140] The part of the bonding metal film b31 and the bonding support layer 102 that are directly bonded and connected can be the connecting part 1033 in the chip support layer 103 of the light-emitting chip substrate.

[0141] In the embodiments of the present application, the grid-shaped bonding support layer 102 is prepared on the support substrate 101. The bonding support layer 102 is regionally bonded with the entire surface of the epitaxial wafer, solving the problem of wafer cracking caused by stress after the epitaxial layer is transferred to the glass substrate.

[0142] In step S104, the chip substrate in the plurality of light-emitting chip sub-substrates is removed.

[0143] With reference to Figure 13 The chip substrate b1 in the light-emitting chip sub-substrate is removed, and the epitaxial layer b2 in the light-emitting chip sub-substrate is exposed.

[0144] In a case where the chip substrate b1 in the light emitting chip sub-substrate is a silicon substrate, the chip substrate b1 can be removed by using a silicon etching method. In a case where the chip substrate b1 in the light emitting chip sub-substrate is sapphire, the chip substrate b1 can be removed by using a laser lift-off (LLO) method.

[0145] In step S105, the epitaxial layer in the plurality of light emitting chip sub-substrates is patterned to obtain a plurality of light emitting chips.

[0146] In the embodiment of the present application, the epitaxial layer b2 can be patterned by using an inductively coupled plasma (ICP) dry etching device to obtain the first semiconductor layer 1041, the light emitting layer 1042 and the second semiconductor layer 1043 of the plurality of light emitting chips 104. Referring to Figure 14 , the first semiconductor layer 1041, the light emitting layer 1042 and the second semiconductor layer 1043 are sequentially stacked in a direction away from the support substrate 101. The first semiconductor layer 1041 includes P-type doped gallium nitride, the second semiconductor layer 1043 includes N-type doped gallium nitride, and the light emitting film b22 includes a multi-quantum well layer (MQW).

[0147] In the etching process, the second semiconductor film b23 is etched first, and then the light emitting film b22 and the first semiconductor film b21 are etched in sequence. Due to the influence of the etching process itself, the size of the film layer obtained by etching the first film will be smaller, and the size of the film layer obtained by etching the last film will be larger. Therefore, the area of the light emitting chip 104 in the cross section parallel to the surface of the support substrate 101 gradually decreases with the increase of the distance between the light emitting chip 104 and the support substrate 101.

[0148] Optionally, the orthographic projection of the second semiconductor layer 1043 on the support substrate 101 is located within the orthographic projection of the light emitting layer 1042 on the support substrate 101, and the area of the orthographic projection of the second semiconductor layer 1043 on the support substrate 101 is smaller than the area of the orthographic projection of the light emitting layer 1042 on the support substrate 101. The orthographic projection of the light emitting layer 1042 on the support substrate 101 is located within the orthographic projection of the first semiconductor layer 1041 on the support substrate 101, and the area of the orthographic projection of the light emitting layer 1042 on the support substrate 101 is smaller than the area of the orthographic projection of the first semiconductor layer 1041 on the support substrate 101.

[0149] In the embodiment of the present application, referring to Figure 15 After the epitaxial layer b2 is etched, a current transmission layer can be formed on the side of the second semiconductor layer 1043 of the light emitting chip 104 away from the support substrate 101. The material of the current transmission layer can be indium tin oxide (ITO). The current transmission layer can also be referred to as a transparent electrode.

[0150] Step S106, the chip support film is patterned to obtain a chip support layer.

[0151] In the embodiments of the present application, the chip support film b3 can be patterned by exposure, development and etching. Referring to Figure 6 , the chip support layer 103 obtained after the patterning includes a plurality of chip support portions 1031, a plurality of dummy connection portions 1032 and a plurality of connection portions 1033. The plurality of chip support portions 1031 and the plurality of first grids are arranged correspondingly, and are arranged correspondingly to the plurality of light emitting chips 104. The orthographic projection of the chip support portion 1031 on the support substrate 101 is located within the orthographic projection of the corresponding first grid on the support substrate 101. The orthographic projection of each light emitting chip 104 on the support substrate 101 is located within the orthographic projection of the corresponding chip support portion 1031 on the support substrate 101. The area of the orthographic projection of the chip support portion 1031 on the support substrate 101 is greater than the area of the orthographic projection of the light emitting chip 104 on the support substrate 101.

[0152] Each chip support portion 1031 corresponds to a plurality of dummy connection portions 1032. One end of each dummy connection portion 1032 is connected to the corresponding chip support portion 1031, and the other end is connected to the connection portion 1033. The chip support portion 1031 and the dummy connection portion 1032 are both spaced apart from the support substrate 101. The connection portion 1033 is a second grid structure formed by a plurality of second grids. The orthographic projection of the connection portion 1033 on the support substrate 101 overlaps with the orthographic projection of the bonding support layer 102 on the support substrate 101, and the connection portion 1033 is connected to the bonding support layer 102.

[0153] Figure 16 is a flowchart of a method for preparing a light emitting chip substrate provided by an embodiment of the present application. Taking a flip-chip structure light emitting chip 104 as an example. Referring to Figure 16 , the method comprises the following steps:

[0154] Step S201, a plurality of light emitting chip sub-substrates are obtained.

[0155] In the embodiments of the present application, referring to Figure 10 , the light emitting chip sub-substrate can include a chip substrate b1, an epitaxial layer b2 and a chip support film b3. The chip substrate b1 and the epitaxial layer b2 in the light emitting chip sub-substrate can be an epitaxial wafer based on a silicon substrate (or sapphire substrate). The light emitting chip sub-substrate can be a chip support film b3 prepared on the basis of the epitaxial wafer.

[0156] Optionally, the epitaxial layer b2 can include a second semiconductor thin film b23, a light emitting thin film b22 and a first semiconductor thin film b21 stacked in sequence in a direction away from the chip substrate b1. The first semiconductor thin film b21 includes P-doped gallium nitride, the second semiconductor thin film b23 includes N-doped gallium nitride, and the light emitting thin film b22 includes a multi-quantum well (MQW) thin film. The first semiconductor thin film b21 is used to form the first semiconductor layer 1041 in the light emitting chip 104, the second semiconductor thin film b23 is used to form the second semiconductor layer 1043 in the light emitting chip 104, and the light emitting thin film b22 is used to form the light emitting layer 1042 in the light emitting chip 104.

[0157] Optionally, the chip support thin film b3 can include a bonding metal thin film b31. The bonding metal thin film b31 and the reflective metal thin film b32 can be prepared by sputtering, electroplating or evaporation. The thickness of the bonding metal thin film b31 can range from 1 μm to 3 μm.

[0158] In step S202, a support substrate is obtained.

[0159] Reference Figure 11 The support substrate includes a support substrate 101 and a bonding support layer 102 on one side of the support substrate 101. The bonding support layer 102 is a first grid-shaped structure composed of a plurality of first grids. The area of the support substrate 101 can be larger than the area of the light emitting chip sub-substrate. Optionally, the support substrate 101 can be glass.

[0160] Optionally, the support substrate can be a grid-shaped bonding support layer 102 prepared by electroplating, sputtering or lift-off on glass.

[0161] Optionally, the order of steps S202 and S201 can be exchanged.

[0162] In step S203, the chip support thin film in the plurality of light emitting chip sub-substrates and the bonding support layer in the support substrate are bonded and connected.

[0163] In the embodiments of the present application, reference Figure 12 The plurality of light emitting chip sub-substrates can be hot-pressed bonded with the support substrate by a bonding device. During the hot-press bonding process, the bonding support layer 102 in the support substrate reacts with the bonding metal thin film b31 in the light emitting chip sub-substrate to generate an IMC intermetallic compound.

[0164] Optionally, the support substrate 101 can correspond to bonding multiple light-emitting chip sub-substrates. The bonding metal film b31 in the chip support film b3 and the bonding support layer 102 are bonded and connected, and the material of the bonding support film can be at least one of indium (In) and tin (Sn). Moreover, the material of the bonding metal film b31 and the material of the bonding support layer 102 can be arbitrarily combined.

[0165] In the embodiment of the present application, the grid-shaped bonding support layer 102 is prepared on the support substrate 101, and the bonding support layer 102 is regionally bonded with the entire surface of the epitaxial wafer, thereby solving the problem of wafer cracking caused by stress after the epitaxial layer is transferred to the glass substrate.

[0166] In step S204, the chip substrate in the multiple light-emitting chip sub-substrates is removed.

[0167] Reference Figure 13 The chip substrate b1 in the light-emitting chip sub-substrate is removed, and the epitaxial layer b2 in the light-emitting chip sub-substrate is exposed.

[0168] In the case where the chip substrate b1 in the light-emitting chip sub-substrate is a silicon substrate, the chip substrate b1 can be removed by silicon etching. In the case where the chip substrate b1 in the light-emitting chip sub-substrate is sapphire, the chip substrate b1 can be removed by laser lift-off (LLO).

[0169] In step S205, the epitaxial layer in the multiple light-emitting chip sub-substrates is patterned to obtain multiple light-emitting chips.

[0170] In the embodiment of the present application, the epitaxial layer b2 can be patterned by an inductively coupled plasma (ICP) dry etching device to obtain a first semiconductor layer 1041, a light-emitting layer 1042 and a second semiconductor layer 1043 of multiple light-emitting chips 104. In the embodiment of the present application, the first semiconductor layer 1041, the light-emitting layer 1042 and the second semiconductor layer 1043 are sequentially stacked in the direction away from the support substrate 101. Figure 17 The first semiconductor layer 1041 includes P-type doped gallium nitride, the second semiconductor layer 1043 includes N-type doped gallium nitride, and the light-emitting film b22 includes a multiple quantum well layer (MQW). The light-emitting layer 1042 and the second semiconductor layer 1043 expose a part of the first semiconductor layer 1041.

[0171] After that, referring to Figure 18The first electrode 1044 and the second electrode 1045 of the light emitting chip 104 can be formed by a metal deposition (deposition) process and a patterning process. The first electrode 1044 is electrically connected to a part of the first semiconductor layer 1041, the light emitting layer 1042 and the second semiconductor layer 1043 exposed. The second electrode 1045 is electrically connected to the light emitting layer 1042 and the second semiconductor layer 1043.

[0172] In step S206, the chip support film is subjected to a patterning process to obtain a chip support layer.

[0173] In the embodiment of the present application, the chip support film b3 can be subjected to a patterning process by exposure, development and etching. Referring to Figure 7 , the chip support layer 103 obtained after the patterning process includes a plurality of chip support portions 1031, a plurality of dummy connection portions 1032 and a plurality of connection portions 1033. The plurality of chip support portions 1031 are arranged correspondingly to the plurality of first grids and correspondingly to the plurality of light emitting chips 104. The orthographic projection of the chip support portion 1031 on the support substrate 101 is located within the orthographic projection of the corresponding first grid on the support substrate 101. The orthographic projection of each light emitting chip 104 on the support substrate 101 is located within the orthographic projection of the corresponding chip support portion 1031 on the support substrate 101. The area of the orthographic projection of the chip support portion 1031 on the support substrate 101 is greater than the area of the orthographic projection of the light emitting chip 104 on the support substrate 101.

[0174] Each chip support portion 1031 corresponds to a plurality of dummy connection portions 1032. One end of each dummy connection portion 1032 is connected to the corresponding chip support portion 1031, and the other end is connected to the connection portion 1033. The chip support portion 1031 and the dummy connection portion 1032 are both spaced apart from the support substrate 101. The connection portion 1033 is a second grid structure formed by a plurality of second grids. The orthographic projection of the connection portion 1033 on the support substrate 101 overlaps with the orthographic projection of the bonding support layer 102 on the support substrate 101, and the connection portion 1033 is connected to the bonding support layer 102.

[0175] In summary, the embodiment of the present application provides a preparation method of a light emitting chip substrate. The light emitting chip substrate prepared by the method includes a support substrate, a bonding support layer, a chip support layer and a plurality of light emitting chips. The chip support layer includes a plurality of chip support portions, a plurality of dummy connection portions and a plurality of connection portions. The plurality of light emitting chips in the light emitting chip substrate are transferred to the driving backplane at one time, without the need for multiple transfers, and the transfer efficiency is high.

[0176] Figure 19 is a flowchart of a preparation method of a display substrate provided by the embodiment of the present application. Take the light emitting chip 104 as a vertical structure light emitting chip 104 as an example. Referring to Figure 19 , the method comprises:

[0177] Step S301: Obtain the light-emitting chip substrate.

[0178] In this embodiment of the application, the obtained light-emitting chip substrate can be Figure 1 , Figure 6 and Figure 7 The light-emitting chip substrate shown. That is, the obtained light-emitting chip substrate includes multiple light-emitting chips 104.

[0179] Step S302: Obtain the driver backplane.

[0180] refer to Figure 20 The driving backplane 201 includes a substrate 2011, a driving unit layer 2012, and a plurality of driving connection portions 2013. The driving unit layer 2012 includes a plurality of driving units corresponding to the plurality of driving connection portions 2013, and the driving connection portions 2013 are electrically connected to the driving units. Optionally, the substrate 2011 can be glass.

[0181] Optionally, the order of steps S301 and S302 can be interchanged.

[0182] Step S303: Bond the light-emitting chip substrate to the driving backplate so that the driving connection part is connected to the light-emitting chip.

[0183] If the light-emitting chip 104 is a vertically structured light-emitting chip 104, when the arrangement density of the light-emitting chip 104 in the light-emitting chip substrate corresponds to the arrangement density of the driving unit in the driving back plate 201, the light-emitting chip substrate and the driving back plate 201 can be directly aligned and bonded, so that the light-emitting chip 104 in the light-emitting chip substrate and the driving connection portion 2013 in the driving back plate 201 are bonded and connected.

[0184] When the arrangement density of the light-emitting chips 104 in the light-emitting chip substrate corresponds to the arrangement density of the driving units in the driving backplane 201, the pickup chip substrate can also be acquired. Taking a light-emitting chip 104 with a vertical structure as an example, refer to... Figure 21 The pickup chip substrate includes a pickup substrate c1 and a plurality of pickup portions c2 located on the pickup substrate c1. Optionally, the pickup substrate c1 can be glass.

[0185] The number of pickup units c2 is less than or equal to the number of light-emitting chips 104 in the light-emitting chip substrate, and the arrangement density of the pickup units c2 corresponds to the arrangement density of the driving units in the driving backplane 201. Multiple pickup units c2 correspond to at least a portion of the light-emitting chips 104 in the light-emitting chip substrate. For example... Figure 21 The diagram illustrates two pickup units, c2, while... Figure 6Three light emitting chips 104 are shown in the middle, two pickup portions c2 correspond to the first light emitting chip and the third light emitting chip respectively.

[0186] After the pickup substrate c1 is obtained, referring to Figure 22 The light emitting chip substrate can be bonded to the pickup chip substrate to pick up the multiple light emitting chips 104 corresponding to the multiple pickup portions c2 on the pickup chip substrate. For example Figure 22 The first light emitting chip 104 and the third light emitting chip 104 are picked up on the pickup chip substrate in the middle.

[0187] Optionally, the pickup portion c2 can be an adhesive bump, which can be a Polydimethylsiloxan (PDMS) stamp structure, or can be composed of a non-adhesive bump and an adhesive coating. When picking up the light emitting chip 104, the pickup portion c2 can be in contact with the light emitting chip 104 to be picked up, and under the action of pressure, the virtual connection portion 1032 around the light emitting chip 104 to be picked up is broken, thereby realizing the separation of the light emitting chip 104 from the support substrate 101 and completing the selective mass transfer of the light emitting chip 104. The light emitting chip substrate with the virtual connection portion 1032 can contact the laser dissociation process in the normal transfer process, simplifying the transfer process and improving the transfer yield.

[0188] After the pickup of the light emitting chip 104 on the pickup chip substrate is completed, referring to Figure 23 The pickup chip substrate with multiple light emitting chips 104 can be thermally and press-bonded to the driving backboard 201. During the bonding process, since the chip support portion 1031 acts as a bonding pad, its size is larger, which can effectively reduce the alignment accuracy requirement and improve the bonding yield.

[0189] If the light emitting chip 104 is a flip-chip light emitting chip 104, referring to Figure 24 When the arrangement density of the light emitting chips 104 in the light emitting chip substrate corresponds to the arrangement density of the driving units in the driving backboard 201, the light emitting chip substrate and the driving backboard 201 can be directly aligned and bonded, so that the light emitting chips 104 in the light emitting chip substrate are bonded to the driving connection portions 2013 in the driving backboard 201, and finally the support substrate 101 is removed.

[0190] If the light emitting chip 104 is a flip chip, the arrangement density of the light emitting chip 104 in the light emitting chip substrate and the arrangement density of the driving unit in the driving back plate 201 do not correspond, and the pick-up chip substrate can be designed to pick up part of the light emitting chip 104 in the light emitting chip substrate. After the pick-up is completed, the first electrode 1044 and the second electrode 1045 are close to the pick-up substrate c1 relative to the light emitting chip 104, and therefore need to be transferred again. For example, the picked-up multiple light emitting chips 104 are transferred to a temporary substrate again, and after the transfer, the first electrode 1044 and the second electrode 1045 are away from the temporary substrate relative to the light emitting chip 104. Finally, the multiple light emitting chips 104 transferred to the temporary substrate and the driving back plate 201 are bonded and connected.

[0191] Optionally, referring to Figure 25 After the light emitting chip 104 and the driving back plate 201 are bonded and connected, the chip support part 1031 on the side of the light emitting chip 104 away from the driving back plate 201 can be removed by using a wet etching process.

[0192] Optionally, in the case of the light emitting chip 104 being a vertical structure, the light emitting chip 104 can be connected through the chip support part 1031 and the driving connection part 2013. For example, the bonding metal layer a1 in the chip support part 1031 and the driving connection part 2013 generate an IMC intermetallic compound to realize the bonding connection. In the case of the light emitting chip 104 being a flip chip, the light emitting chip 104 can be connected through the first electrode 1044 and the second electrode 1045 and the driving connection part 2013. For example, an IMC intermetallic compound is generated between the first electrode 1044 and the driving connection part 2013, and between the second electrode 1045 and the driving connection part 2013 to realize the bonding connection.

[0193] In summary, the embodiment of the present application provides a preparation method of a display substrate. The display substrate prepared by the method includes a driving back plate and multiple light emitting chips. The multiple light emitting chips can be transferred from a light emitting chip substrate to the driving back plate at one time, without multiple transfer, and the transfer efficiency is high.

[0194] The terms used in the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the general meaning understood by those skilled in the art in the field of the present application.

[0195] The terms used in the description of the embodiments of the present application are only used to explain the embodiments of the present application and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the common meanings to those having ordinary skills in the art to which the present application pertains. The terms "first", "second", "third" and the like used in the description of the present patent application and the claims are not intended to denote any sequence, quantity, or importance, but are only used to distinguish different components. Similarly, the terms "one" or "a" and the like do not denote a quantity limitation, but denote the presence of at least one. The terms "include" or "contain" and the like mean that the elements or objects appearing before the "include" or "contain" cover the elements or objects listed after the "include" or "contain" and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships may also be changed accordingly.

[0196] The above is only an optional embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A light-emitting chip substrate, characterized in that, The light-emitting chip substrate includes: Support substrate; A bonding support layer located on one side of the supporting substrate, the bonding support layer being a first grid-like structure composed of multiple first grids; A chip support layer located on the side of the bonding support layer away from the support substrate includes multiple chip support portions, dummy connections, and connecting portions. The multiple chip support portions and multiple first grids are correspondingly arranged. The orthographic projection of each chip support portion on the support substrate lies within the orthographic projection of the corresponding first grid on the support substrate. Each chip support portion corresponds to multiple dummy connections. One end of each dummy connection is connected to the corresponding chip support portion, and the other end is connected to the connecting portion. There is a gap between the chip support portions and the dummy connections and the support substrate. The connecting portion is a second grid-like structure composed of multiple second grids. The orthographic projection of the connecting portion on the support substrate overlaps with the orthographic projection of the bonding support layer on the support substrate, and the connecting portion is connected to the bonding support layer. A plurality of light-emitting chips are located on the side of the chip support layer away from the support substrate and are disposed corresponding to the plurality of chip support portions. The orthographic projection of each light-emitting chip on the support substrate is located within the orthographic projection of the corresponding chip support portion on the support substrate. The area of ​​the orthographic projection of the chip support portion on the support substrate is larger than the area of ​​the orthographic projection of the light-emitting chip on the support substrate.

2. The light-emitting chip substrate according to claim 1, characterized in that, The light-emitting chip is a vertically structured light-emitting chip; the chip support layer includes: a bonding metal layer and a reflective metal layer stacked along a direction away from the support substrate; The portion of the bonding metal layer belonging to the connecting portion is used for bonding with the bonding support layer, and the portion of the reflective metal layer belonging to the chip support portion is used for reflecting the light emitted by the light-emitting chip.

3. The light-emitting chip substrate according to claim 2, characterized in that, The light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along a direction away from the supporting substrate; The first semiconductor layer comprises P-type doped gallium nitride, the second semiconductor layer comprises N-type doped gallium nitride, and the light-emitting layer comprises a multi-quantum-well layer.

4. The light-emitting chip substrate according to claim 3, characterized in that, The area of ​​the cross-section of the light-emitting chip on the surface parallel to the supporting substrate gradually decreases as the distance between the chip and the supporting substrate increases.

5. The light-emitting chip substrate according to claim 4, characterized in that, The cross-sectional shape of the light-emitting chip is trapezoidal, and the cross-section is perpendicular to the surface of the supporting substrate; The length of the trapezoid on the side furthest from the supporting substrate is less than the length of the trapezoid on the side closest to the supporting substrate.

6. The light-emitting chip substrate according to claim 1, characterized in that, The light-emitting chip is a flip-chip structured light-emitting chip; the chip support layer includes: a bonding metal layer; The portion of the bonding metal layer belonging to the connecting portion is used for bonding connection with the bonding support layer.

7. The light-emitting chip substrate according to claim 6, characterized in that, The light-emitting chip includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially along a direction away from the supporting substrate; the first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum-well layer; The light-emitting layer and the second semiconductor layer expose a portion of the first semiconductor layer. The light-emitting chip also includes a first electrode and a second electrode. The first electrode is electrically connected to the portion of the first semiconductor layer exposed by the light-emitting layer and the second semiconductor layer, and the second electrode is electrically connected to the second semiconductor layer.

8. The light-emitting chip substrate according to any one of claims 1 to 7, characterized in that, The dummy joint is a strip-shaped structure, and the width of the dummy joint ranges from 3 micrometers to 10 micrometers.

9. The light-emitting chip substrate according to any one of claims 1 to 7, characterized in that, The shapes of the second grid, the light-emitting chip, and the chip support are all square. The side length of the second grid is 1.5 to 3 times the side length of the light-emitting chip; The side length of the chip support is 1 to 2 times the side length of the light-emitting chip.

10. A display substrate, characterized in that, The display substrate includes: A driving backplane includes a substrate, a driving unit layer, and a plurality of driving connection portions. The driving unit layer includes a plurality of driving units corresponding to the plurality of driving connection portions, and the driving connection portions are electrically connected to the driving units. Multiple light-emitting chips are located on one side of the driving backplate, and the multiple light-emitting chips and the multiple driving connection portions are correspondingly arranged. Each light-emitting chip includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked sequentially in a direction away from the driving backplate. The first semiconductor layer includes P-type doped gallium nitride, the second semiconductor layer includes N-type doped gallium nitride, and the light-emitting layer includes a multi-quantum well layer. And a chip support portion located between the light-emitting chip and the driving connection portion; The display substrate includes a plurality of light-emitting chips that are bonded to a light-emitting chip substrate as described in any one of claims 1 to 9 and a driving backplane; the area of ​​the cross section of the light-emitting chip parallel to the reference plane gradually decreases as the distance between it and the driving backplane increases, and the reference plane is parallel to the surface of the driving unit layer near the driving connection portion. The orthographic projection of the light-emitting chip on the reference plane is located within the orthographic projection of the chip support on the reference plane, and the area of ​​the orthographic projection of the chip support on the reference plane is larger than the area of ​​the orthographic projection of the light-emitting chip on the reference plane.

11. The display substrate according to claim 10, characterized in that, The chip support includes a bonding metal layer and a reflective metal layer. The bonding metal layer is close to the driving connection relative to the reflective metal layer. The bonding metal layer in the chip support is connected to the driving connection. The reflective metal layer in the chip support is used to reflect the light emitted by the light-emitting chip.

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