Circuit for realizing ultra-fast start and low standby

Abstract

The utility model relates to the technical field of switching power supply conversion, in particular to a circuit for realizing ultrafast start and low standby, which comprises a transformer T1, a controller unit, a starting resistor Rs, a first power tube NPN1 and a second power tube NPN2, through a specific circuit connection relation, a starting resistor Rs with a specific resistance value range and a first power tube NPN1 and a second power tube NPN2 which can form a specific current amplification multiple range are selected, the starting resistor Rs obtains starting current from a transformer T1, the starting current is 10 uA or above, and after the starting current is subjected to two-stage amplification through the first power tube NPN1 and the second power tube NPN2, the starting current is converted into the starting current. The emitter output current of the second power tube NPN2 reaches 10mA, the chip is charged to 5V, only 10ms is needed, so that 10ms-level quick starting is realized, the loss of the starting resistor Rs is only 20mW, and the balance between the starting speed and the standby power consumption is realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to switching power supply conversion technical field, specifically a kind of circuit of realization superfast start low standby. BACKGROUND

[0002] With the massive development of portable electronic equipment, the market demand of adapter is more and more big, the output power of previous adapter is mostly between 12W-24W, and ordinary NMOS is used as power tube, which needs to increase starting resistance externally, even if small starting resistance is used, its starting time is more than 1s, and standby power consumption is large. In AC-DC system, to realize fast start, method one is to use high-voltage JFET (i.e. junction field effect transistor), however, this method will increase the system cost, and the integrated JFET withstand voltage is mostly capped at 700V, which cannot meet the market requirement of 800V withstand voltage. Method two is to use starting resistance plus NMOS combination start, this starting structure can realize superfast start, but the cost is relatively high, and there is still a withstand voltage problem, because the withstand voltage of NMOS itself is only 650V, which leads to the withstand voltage of the starting structure only 650V. SUMMARY

[0003] Therefore, the utility model aims at providing a kind of circuit of realization superfast start low standby to solve the above technical problems.

[0004] In order to achieve the above purpose, the utility model adopts the technical scheme that:

[0005] A kind of circuit of realization superfast start low standby, including transformer T1, controller unit, starting resistance Rs, first power tube NPN1 and second power tube NPN2;The resistance range of starting resistance Rs is 15MΩ-25MΩ, one end of transformer T1 is respectively connected with one end of starting resistance Rs, the collector of first power tube NPN1 and the collector of second power tube NPN2, the other end of transformer T1 provides energy output for external load;The base of first power tube NPN1 and the base of second power tube NPN2 are respectively connected with controller unit, the emitter of first power tube NPN1 is connected with the base of second power tube NPN2;The current amplification multiple range formed by first power tube NPN1 and second power tube NPN2 is 600 times-1200 times.

[0006] Preferably, the resistance range of starting resistance Rs is 20MΩ, and the current amplification multiple of first power tube NPN1 and second power tube NPN2 is 1000 times.

[0007] Preferably, it further includes drive tube N1, drive tube N2, drive tube N3, comparator A1, and gate X1 and diode D2.

[0008] The controller unit is respectively electrically connected with two input ends of the AND gate X1, an output end of the AND gate X1 is respectively electrically connected with a gate of a driving tube N1, a gate of a driving tube N2 and a gate of a driving tube N3, a drain of the driving tube N1 is electrically connected with a base of a first power tube NPN1, a drain of the driving tube N2 is electrically connected with an emitter of the first power tube NPN1, a drain of the driving tube N3 is electrically connected with an emitter of a second power tube NPN2, and a source of the driving tube N1, a source of the driving tube N2 and a source of the driving tube N3 are all grounded.

[0009] The emitter of the second power tube NPN2 is electrically connected with a positive electrode of a diode D2, the negative electrode of the diode D2 is electrically connected with a positive input end of a comparator A1, a negative input end of the comparator A1 is connected with a preset reference voltage, and an output end of the comparator A1 is electrically connected with one of two input ends of the AND gate X1.

[0010] Preferably, a first capacitor C1 is further included, one end of the first capacitor C1 is electrically connected with a negative electrode of the diode D2, and the other end of the first capacitor C1 is grounded.

[0011] Preferably, a diode D1 and a second capacitor C2 are further included, and the transformer T1 includes a primary winding LP and a secondary winding LS.

[0012] One end of the starting resistor Rs is electrically connected with the primary winding LP, one end of the secondary winding LS is electrically connected with a positive electrode of the diode D1, a negative electrode of the diode D1 is electrically connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is electrically connected with the other end of the secondary winding LS.

[0013] The utility model discloses the beneficial effect is:

[0014] The utility model provides a kind of circuit of realizing superfast start low standby, including transformer T1, controller unit, starting resistance Rs, first power tube NPN1 and second power tube NPN2;Through specific circuit connection relationship, select the starting resistance Rs of specific resistance value range 15MΩ-25MΩ and the first power tube NPN1 and second power tube NPN2 that can form specific current amplification multiple range 600 times-1200 times, starting resistance Rs obtains starting current from transformer T1, starting current is above 10uA, starting current is amplified by first power tube NPN1 and second power tube NPN2 two stages, amplification multiple is between 600 times-1200 times, after amplification, second power tube NPN2 emitter output current reaches 10mA, charges chip, charges to 5V, only needs 10ms, to realize 10ms level fast start, and the loss of starting resistance Rs is only 20mW, realizes the balance between starting speed and standby power consumption.In addition, the withstand voltage of first power tube NPN1 and second power tube NPN2 is 850V, guarantees that system can work at 850V, and first power tube NPN1 and second power tube NPN2 are power BJT, and several only half of 650V field effect tube, so the technical scheme of the utility model is adopted, realizes high withstand voltage work, also realizes 10ms level fast start, starting resistance loss 20mW, reaches JFET loss level, realizes perfect compromise. BRIEF DESCRIPTION OF DRAWINGS

[0015] Fig. 1 It is the connection diagram of the utility model's a kind of circuit of realizing superfast start low standby;

[0016] Fig. 2 It is the internal circuit connection diagram of the comparator A1 of the utility model;

[0017] Fig. 3 It is the internal circuit connection diagram of the AND gate X1 of the utility model. DETAILED DESCRIPTION

[0018] The utility model is further explained as follows in connection with the drawings and specific embodiment:

[0019] Reference Figs. 1 to 3 The utility model provides a kind of circuit of realizing superfast start low standby, including transformer T1, controller unit, starting resistance Rs, first power tube NPN1, second power tube NPN2, drive tube N1, drive tube N2, drive tube N3, comparator A1, AND gate X1, diode D2, first capacitor C1, diode D1 and second capacitor C2;

[0020] The starting resistor Rs has a resistance ranging from 15MΩ to 25MΩ, preferably 20MΩ; the current amplification factor of the first power tube NPN1 and the second power tube NPN2 ranges from 600 times to 1200 times, preferably 1000 times. In the embodiment, the first power tube NPN1 is of the model W2XN1118 or W2XN937, and the second power tube NPN2 is of the model W2XN1180 or W2XN1205.

[0021] One end of the transformer T1 is electrically connected with one end of the starting resistor Rs, the collector of the first power tube NPN1 and the collector of the second power tube NPN2 respectively, and the other end of the transformer T1 provides energy output for an external load; the controller unit is electrically connected with the base of the first power tube NPN1 and the base of the second power tube NPN2 respectively, and the emitter of the first power tube NPN1 is electrically connected with the base of the second power tube NPN2;

[0022] The controller unit is electrically connected with two input ends of the AND gate X1 respectively, specifically, the two input ends of the AND gate X1 are IN1 terminal and IN2 terminal respectively. The controller unit is provided with Ctr1 terminal and Ctr2 terminal, the Ctr1 terminal is used for electrical connection with the IN2 terminal, and the Ctr2 terminal is used for electrical connection with the IN1 terminal.

[0023] The output end of the AND gate X1 is electrically connected with the gate of the driving tube N1, the gate of the driving tube N2 and the gate of the driving tube N3 respectively, the drain of the driving tube N1 is electrically connected with the base of the first power tube NPN1, the drain of the driving tube N2 is electrically connected with the emitter of the first power tube NPN1, the drain of the driving tube N3 is electrically connected with the emitter of the second power tube NPN2, and the source of the driving tube N1, the source of the driving tube N2 and the source of the driving tube N3 are all grounded;

[0024] The emitter of the second power tube NPN2 is electrically connected with the anode of the diode D2, the cathode of the diode D2 is electrically connected with the positive input end of the comparator A1, the negative input end of the comparator A1 is connected with a preset reference voltage (VREF), and the output end of the comparator A1 is electrically connected with one of the two input ends of the AND gate X1, i.e. the IN2 terminal.

[0025] One end of the first capacitor C1 is electrically connected with the cathode of the diode D2, and the other end of the first capacitor C1 is grounded.

[0026] The transformer T1 includes a primary winding LP and a secondary winding LS; one end of the starting resistor Rs is electrically connected to one end of the primary winding LP, and the other end of the primary winding LP is connected to an external line voltage to provide an energy source; one end of the secondary winding LS is electrically connected to the anode of the diode D1, the cathode of the diode D1 is electrically connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is electrically connected to the other end of the secondary winding LS.

[0027] In the embodiment, the starting resistor Rs and the first power tube NPN1 are integrated together. The first power tube NPN1 and the second power tube NPN2 are both starting tubes and power tubes. The withstand voltage of the first power tube NPN1 and the second power tube NPN2 is 850V. The resistance value of the starting resistor Rs is 20MΩ, and when the voltage at the LP end is 200V, the current of the starting resistor Rs is 10μA.

[0028] The specific structure of the comparator A1 is as shown in Fig. 2 The specific structure of the comparator A1 is as shown in

[0029] The comparator A1 detects the voltage of the first capacitor C1, and when the voltage of the first capacitor C1 reaches VREF, the comparator A1 outputs a logic high level. Of course, the comparator A1 is only one kind of comparator structure, and other comparators that can achieve the effect of level comparison can also be applicable.

[0030] The specific structure of the comparator A1 is as shown in Fig. 3The shown, including: pmos tube P5, pmos tube P6, pmos tube P7, nmos tube N7, nmos tube N8 and nmos tube N9. The gate of the pmos tube P5 is electrically connected to the gate of nmos tube N8 and connected to the input IN1 of the NAND gate X1, the gate of the pmos tube P6 is electrically connected to the gate of nmos tube N7 and connected to the input IN2 of the NAND gate X1, the source of the pmos tube P5 is electrically connected to the source of the pmos tube P6 and the source of the pmos tube P7, the drain of the pmos tube P5 is electrically connected to the drain of the pmos tube P6 and the drain of the nmos tube N7, the source of the nmos tube N7 is electrically connected to the drain of the nmos tube N8, the source of the nmos tube N8 is electrically connected to GND, the gate of the pmos tube P7 is electrically connected to the gate of the nmos tube N9 and connected to the drain of the pmos tube P6, the drain of the nmos tube N7. The drain of the pmos tube P7 is electrically connected to the drain of the nmos tube N9 and connected to the output of the NAND gate X1.

[0031] The controller unit is the ACDC master unit, the controller unit Vcc end is connected to the external capacitor C1, the starting circuit, when power on to charge the external capacitor C1. The output of the comparator A1 is connected to the Ctr1 of the controller unit, the IN1 of the NAND gate X1 is connected to the Ctr2 of the controller unit, the base of the first power tube NPN1 is connected to the Drv1 of the controller unit, the base of the second power tube NPN2 is connected to the Drv2 of the controller unit, when the voltage of the first capacitor C1 is greater than VREF, the comparator A1 outputs logic high, when the controller unit receives high level signal through the Ctr1 end, it starts to enter the normal switching control, through the Drv1, Drv2 control the conduction of the first power tube NPN1, the second power tube NPN2, through the Ctr2 control the NAND gate X1, and then control the drive tube N1, the drive tube N2, the drive tube N3. After the start, the Ctr2 output of the controller is low level, and then the NAND gate X1 outputs low level, the drive tube N1, the drive tube N2 and the drive tube N3 are closed, and the first power tube NPN1 and the second power tube NPN2 are not controlled.

[0032] The utility model discloses a novel through starting resistance Rs obtains starting current from transformer LP one end, and starting current is above 10muA, and starting current is amplified through NPN1, NPN2 two stage, and the amplification multiple is above 1000, after amplification, NPN2 emitter output circuit reaches 10mA, and the chip Vcc capacitor C1 is charged, and charges to 5V, and C1 is when the capacity is 20muF, and starting time T = c * U / I, wherein c = 20muF, I = 10mA, U = 5V, obtains T = 10ms, to realize 10ms level fast start, and starting resistance loss calculates as follows, p = u * u / R, u = 200V, R = 20M omega, calculates and obtains p = 20mW, and starting resistance loss is only 20mW, and the compromise of starting speed and standby power consumption is realized. In addition, the withstand voltage of the first power tube NPN1 and the second power tube NPN2 is 850V, which ensures that the system can work at 850V, and the first power tube NPN1 and the second power tube NPN2 are power BJT, which is only half of the field effect tube of 650V, therefore, by using the technical scheme of the utility model, high voltage work is realized, and 10ms level fast start is realized, starting resistance loss is 20mW, reaches the JFET loss level, and perfect compromise is realized.

[0033] The utility model has been described by the above related embodiments and drawings, however the above embodiment is only the example of implementation of the utility model. It must be pointed out that the disclosed embodiment does not limit the scope of the utility model. On the contrary, the modification and equivalent setting included in the spirit and scope of the claims are included in the scope of the utility model.

Claims

1. A circuit for implementing ultra-fast start-up low standby, characterized by, The transformer T1, the controller unit, the starting resistor Rs, the first power tube NPN1 and the second power tube NPN2 are included; the resistance value of the starting resistor Rs ranges from 15MΩ to 25MΩ, one end of the transformer T1 is electrically connected with one end of the starting resistor Rs, the collector of the first power tube NPN1 and the collector of the second power tube NPN2 respectively, and the other end of the transformer T1 provides energy output for an external load; the controller unit is electrically connected with the base of the first power tube NPN1 and the base of the second power tube NPN2 respectively, the emitter of the first power tube NPN1 is electrically connected with the base of the second power tube NPN2; the current amplification multiple of the first power tube NPN1 and the second power tube NPN2 ranges from 600 times to 1200 times.

2. The circuit for implementing ultrafast start-up low standby according to claim 1, wherein, The resistance value of the starting resistor Rs is 20MΩ, and the current amplification multiple of the first power tube NPN1 and the second power tube NPN2 is 1000 times.

3. The circuit of claim 1, wherein, The driving tube N1, the driving tube N2, the driving tube N3, the comparator A1, the AND gate X1 and the diode D2 are further included. The controller unit is electrically connected with two input ends of the AND gate X1 respectively, the output end of the AND gate X1 is electrically connected with the gate of the driving tube N1, the gate of the driving tube N2 and the gate of the driving tube N3 respectively, the drain of the driving tube N1 is electrically connected with the base of the first power tube NPN1, the drain of the driving tube N2 is electrically connected with the emitter of the first power tube NPN1, the drain of the driving tube N3 is electrically connected with the emitter of the second power tube NPN2, and the source of the driving tube N1, the source of the driving tube N2 and the source of the driving tube N3 are grounded. The emitter of the second power tube NPN2 is electrically connected with the anode of the diode D2, the cathode of the diode D2 is electrically connected with the positive input end of the comparator A1, the negative input end of the comparator A1 is connected with a preset reference voltage, and the output end of the comparator A1 is electrically connected with one of the two input ends of the AND gate X1.

4. The circuit of claim 3, wherein, The first capacitor C1 is further included, one end of the first capacitor C1 is electrically connected with the cathode of the diode D2, and the other end of the first capacitor C1 is grounded.

5. The circuit of claim 1, wherein, The diode D1 and the second capacitor C2 are further included, and the transformer T1 includes a primary winding LP and a secondary winding LS; One end of the starting resistor Rs is electrically connected with the primary winding LP, one end of the secondary winding LS is electrically connected with the anode of the diode D1, the cathode of the diode D1 is electrically connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is electrically connected with the other end of the secondary winding LS.

Images