Packaging structure and photoelectric device

Abstract

The utility model provides a packaging structure and a photoelectric device. The packaging structure comprises: a packaging substrate; the electronic integrated circuit structure is arranged on the upper surface of the packaging substrate and comprises a first rewiring layer, an electronic integrated circuit chip arranged on the rewiring layer and an insulating material layer, and the insulating material layer comprises underfill and a plastic packaging layer only surrounding the side face of the electronic integrated circuit chip; a photonic integrated circuit chip disposed over the upper surface of the electronic integrated circuit structure, including an edge coupler; the optical coupling protection structure is located below the photon integrated circuit chip, the top of the optical coupling protection structure is in contact with the lower surface of the photon integrated circuit chip, the bottom of the optical coupling protection structure is in contact with the first rewiring layer, so that a cavity with an opening facing the first side face away from the electronic integrated circuit structure is formed, and the edge coupler protrudes from the top of the optical coupling protection structure to the side direction; and the optical coupling protection structure is in a suspended state in the cavity and separates the edge coupler from the insulating material layer.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and more specifically, to a packaging structure and an optoelectronic device. Background Technology

[0002] With the continuous evolution of photonic computing technology, the field of high-speed interconnect and computing is accelerating the introduction of hybrid packaging architectures of optical chips and electrical chips. In traditional optoelectronic hybrid packaging, in order to avoid interference from the electrical chip packaging process to the optical coupling area of ​​the optical chip, a grating coupler is usually fabricated on the upper surface of the optical chip to couple external optical fibers. For example, Chinese utility model patent CN219642829U discloses such a packaging structure.

[0003] However, with the continuous improvement of packaging integration, chip-on-chip (CPC) packaging is becoming increasingly popular. In this architecture, photonic integrated circuit chips are typically flip-chip mounted on top of reconstructed electronic integrated circuit chips and optically coupled to external optical fibers using edge couplers. However, during the underfill process, the underfill adhesive between the photonic integrated circuit chip and the electronic integrated circuit chip is prone to overflow, intruding into the area where the edge coupler is located, leading to coupling interface contamination, which in turn severely reduces packaging yield and optical performance.

[0004] Therefore, how to effectively protect the coupling interface of the edge coupler of a photonic integrated circuit chip from contamination by the underfill adhesive in a chip-on-chip packaging architecture has become an urgent technical problem to be solved. Utility Model Content

[0005] This invention provides a packaging structure and optoelectronic device with an optical coupling protection structure to solve the technical problem of contamination of the coupling interface of the edge coupler of the photonic integrated circuit chip in the chip-on-chip packaging architecture by the underfill adhesive.

[0006] One embodiment of this utility model relates to a packaging structure, which includes:

[0007] Packaging substrate;

[0008] An electronic integrated circuit structure is disposed on the upper surface of the packaging substrate, comprising a first redistribution layer, an electronic integrated circuit chip disposed on the redistribution layer, and an insulating material layer, wherein the insulating material layer comprises: an underfill, which is located on the upper surface of the electronic integrated circuit chip, and a molding compound, which surrounds only the side of the electronic integrated circuit chip and the side of the underfill.

[0009] A photonic integrated circuit chip, disposed above the upper surface of the electronic integrated circuit structure, includes an edge coupler disposed on the lower surface of the photonic integrated circuit chip; and

[0010] An optical coupling protection structure is located below the photonic integrated circuit chip, with its top contacting the lower surface of the photonic integrated circuit chip and its bottom contacting the first redistribution layer, to form a cavity that opens toward a first side away from the electronic integrated circuit structure.

[0011] The edge coupler protrudes laterally from the top of the optical coupling protection structure and is suspended in the cavity. The optical coupling protection structure isolates the edge coupler from the insulating material layer to prevent the coupling interface of the edge coupler from being contaminated by the insulating material.

[0012] In some embodiments, the lower surface of the photonic integrated circuit chip is provided with a second redistribution layer and a raised under-metal layer. The raised under-metal layer is disposed below a first portion of the second redistribution layer and electrically connected to that portion of the redistribution layer. The upper surface of the electronic integrated circuit chip is provided with a first conductive pillar. The raised under-metal layer is connected to the first conductive pillar to form a conductive path.

[0013] In some embodiments, the electronic integrated circuit structure further includes a dielectric layer located below the first redistribution layer.

[0014] In some embodiments, the molding compound has an in-hole conductive structure that electrically connects a second portion of the second redistribution layer of the photonic integrated circuit chip to a conductive path in the first redistribution layer.

[0015] In some embodiments, the optical coupling protection structure is made of silicon.

[0016] In some embodiments, the optical coupling protection structure has a bottom structure and three sidewalls surrounding the bottom structure, the tops of which are in contact with the lower surface of the photonic integrated circuit chip.

[0017] Furthermore, another embodiment of this utility model relates to an optoelectronic device, which includes the packaging structure described in any embodiment of this utility model.

[0018] This utility model has at least the following beneficial effects.

[0019] According to the embodiments, the packaging structure of this utility model has an optical coupling protection structure, which can prevent the insulating material (including molding material and underfill, etc.) at the bottom of the photonic integrated circuit chip from overflowing to the edge coupler during the chip-to-chip packaging process, so as to avoid contaminating the coupling interface of the edge coupler. Once the coupling interface of the edge coupler is contaminated by other materials, the optical coupling performance will decrease, resulting in a low packaging yield. This utility model can effectively protect the coupling interface of the edge coupler through the optical coupling protection structure, thus greatly improving the packaging yield.

[0020] One embodiment of this invention employs a silicon-based protective structure to protect the coupling interface of the edge coupler of the optical chip. It is compatible with traditional CoWoS advanced packaging equipment platforms and processes, reducing the difficulty of process fabrication and manufacturing costs.

[0021] The various aspects, features, and advantages of the embodiments of this utility model will become clearer in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating an exemplary embodiment of the packaging structure of this utility model.

[0023] Figures 2 to 11 This is a schematic diagram illustrating an exemplary manufacturing process of the packaging structure of this utility model.

[0024] Figure 12 This is a schematic diagram illustrating an application example of the packaging structure of this utility model. Detailed Implementation

[0025] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. It should be noted that the present invention can be implemented in various forms and is not limited to the specific embodiments described herein or shown in the accompanying drawings.

[0026] The descriptions of element positions in this document (such as "top", "bottom", "above", "below", "left", "right", etc.) are used only to indicate the relative orientation of elements in the accompanying drawings. These descriptions are exemplary only and are not limiting. In other exemplary embodiments, the orientation of the elements may differ, and these variations are also included within the scope of this disclosure.

[0027] The terms “comprising,” “including,” “having,” and “having” are used herein to indicate the presence of certain features, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, steps, operations, elements, components, or combinations thereof. Unless explicitly defined by context, the terms “first,” “second,” and similar terms do not indicate any priority or order, but are used only to distinguish different objects in the description.

[0028] Figure 1 The packaging structure of an exemplary embodiment of the present invention is shown. As shown, the packaging structure 1000 includes at least a photonic integrated circuit chip 100, an electronic integrated circuit structure (which includes at least a first redistribution layer 700, an insulating material layer 200, and an electronic integrated circuit chip 400), an optical coupling protection structure 300, and a packaging substrate 500. The specific configuration of these components or structures is described below.

[0029] In an exemplary embodiment, the photonic integrated circuit chip 100 and the electronic integrated circuit chip 400 are supported on the packaging substrate 500. The photonic integrated circuit chip 100 includes an edge coupler 101. In some embodiments, the photonic integrated circuit chip 100 is fabricated via an SOI wafer and may include one or more optical devices formed in the wafer, such as waveguides, optical couplers, optical modulators, directional couplers, multimode interferometers (MMIs), photodetectors, and optical beam splitters. The photonic integrated circuit chip can achieve electro-optic conversion using the optical modulator therein and photoelectric conversion using the photodetector. In an exemplary embodiment, the edge coupler 101 is positioned relative to a first side of the electronic integrated circuit structure ( Figure 1 The right side of the structure protrudes to the side and is suspended in mid-air.

[0030] In an exemplary embodiment, the insulating material layer 200 is located below and connected to the photonic integrated circuit chip 100, and at least surrounds the side of the electronic integrated circuit chip 400. The optical coupling protection structure 300 is located below the photonic integrated circuit chip 100, separating the edge coupler 101 from the insulating material layer 200, so that the edge coupler does not directly contact the insulating material layer 200. Figure 1As shown, the edge coupler 101 is not in direct contact with the insulating material layer 200. In an exemplary embodiment, the optical coupling protection structure 300 and the photonic integrated circuit chip 100 together form a cavity facing away from the first side opening, in which the edge coupler 101 is suspended. In some embodiments, the optical coupling protection structure 300 has a bottom structure and three sidewalls surrounding the bottom structure, the tops of which contact the lower surface of the photonic integrated circuit chip 100. Figure 1 As shown, in the cross-sectional view, the optical coupling protection structure 300 is approximately L-shaped.

[0031] In some embodiments, the electronic integrated circuit structure includes at least one electronic integrated circuit chip 400 disposed on a first redistribution layer 700. The electronic integrated circuit chip 400 is located below the photonic integrated circuit chip 100, and at least a portion of it is surrounded by the insulating material layer 200. In some embodiments, the lower surface of the photonic integrated circuit chip 100 has a second redistribution layer 110 and an under-bump metal layer 120. The under-bump metal layer 120 is disposed below a first portion of the second redistribution layer 110 and electrically connected to that portion of the redistribution layer. The upper surface of the electronic integrated circuit chip 400 has a first conductive post 410, and the under-bump metal layer 120 is connected to the first conductive post 410 to form a conductive path. In some embodiments, the first conductive post 410 is connected to the under-bump metal layer 120 via solder bumps 800. For example, the solder bump 800 may be a C4 bump (C4 is an abbreviation for Controlled Collapse Chip Connection).

[0032] In some implementations, such as Figure 1 As shown, the insulating material layer 200 includes an underfill 210 and a molding compound 220. The underfill 210 is located on the upper surface of the electronic integrated circuit chip 400. The underfill 210 is disposed between the photonic integrated circuit chip 100 and the electronic integrated circuit chip 400. The molding compound 220 surrounds the electronic integrated circuit chip 400 and the underfill 210.

[0033] In some embodiments, the electronic integrated circuit structure further includes a dielectric layer 600 located below the first redistribution layer 700. The first redistribution layer 700 is located between the insulating material layer 200 and the electronic integrated circuit chip 400 and the dielectric layer 600. In some embodiments, the first redistribution layer 700 may be surrounded by the material forming the dielectric layer 600.

[0034] In some embodiments, a portion of the molding compound 220 is provided between the first redistribution layer 700 and the photonic integrated circuit chip 100, and this portion includes an in-hole conductive structure 221. The in-hole conductive structure 221 electrically connects a second portion of the second redistribution layer 110 of the photonic integrated circuit chip 100 to a conductive path in the first redistribution layer 700. The in-hole conductive structure 221 includes a hole passing through the molding compound 220 and a second conductive post located in the hole, which will be described below.

[0035] In some embodiments, solder balls 900 protrude from the dielectric layer 600 and are electrically connected to the first redistribution layer 700. The solder balls 900 are soldered to the packaging substrate 500, thereby supporting the package including the photonic integrated circuit chip 100 and the electronic integrated circuit chip 400 on the packaging substrate 500. In some embodiments, the conductive path from the electronic integrated circuit chip 400 to the packaging substrate 500 sequentially passes through the first conductive post 410, solder bumps 800, under-bump metal layer 120, second redistribution layer 110, in-hole conductive structure 221, first redistribution layer 700, and solder balls 900 to reach the wiring structure in the packaging substrate 500. The conductive path from the photonic integrated circuit chip 100 to the packaging substrate 500 sequentially passes through the second redistribution layer 110, in-hole conductive structure 221, first redistribution layer 700, and solder balls 900 to reach the wiring structure in the packaging substrate 500.

[0036] In some embodiments, the top of the optical coupling protection structure 300 contacts the lower surface of the photonic integrated circuit chip 100, its bottom contacts the first redistribution layer 700, and its side contacts the molding compound layer 220, thereby isolating the molding compound layer 220 from the edge coupler 101 and its surrounding space. Specifically, the optical coupling protection structure 300 and a portion of the photonic integrated circuit chip 100 together form a cavity facing away from the first side opening, in which the edge coupler 101 is located. Optionally, in Figure 1 In the cross-sectional view shown, the optical coupling protection structure 300 is an L-shaped structure. Furthermore, the edge coupler 101 protrudes laterally from the top of the optical coupling protection structure 300, suspended within the cavity. In some embodiments, the optical coupling protection structure is made of silicon. It should be understood that the present invention is not limited thereto, and the optical coupling protection structure can be made of any suitable material known in the art. For example, the suitable material can be a metallic material such as copper, or other non-metallic materials. For example, optionally, when forming the protruding under-metal layer 120, a barrier structure is formed around the edge coupler using the same metallic material as the optical coupling protection structure.

[0037] The following is combined Figures 2 to 11 The effects of the packaging structure of this utility model will be explained.

[0038] An exemplary fabrication process of the packaging structure of this utility model includes: as follows Figure 2 As shown, wafer 100' is processed to form optical elements, including edge couplers (e.g., edge coupler 101). A second redistribution layer 110 is then formed on the front side (upper side in the figure) of wafer 100', and a subsurface metallization layer (UBM) 120 is formed on a portion of the surface of the second redistribution layer 110. The exemplary fabrication process then includes forming a second conductive pillar 221' (e.g., on another portion of the second redistribution layer 110) on another portion of the second redistribution layer 110. Figure 3 As shown), the second conductive pillar is, for example, a copper pillar; then, the silicon mask 300' (as shown) is placed... Figure 4 The silicon mask 300' is mounted on the wafer 100', completely covering the edge coupler 101 to isolate the edge coupler from the external space. In some embodiments, the silicon mask 300' is bonded to the wafer 100' using organic adhesive. In alternative embodiments, the silicon mask 300' can be soldered to the wafer 100' using metal solder or the like.

[0039] Next, the exemplary manufacturing process proceeds to... Figure 5 In the intermediate state shown, the electronic integrated circuit chip 400 is mounted on the wafer 100'. Specifically, a first conductive pillar 410 (e.g., a copper pillar) is formed on the electronic integrated circuit chip 400, and the first conductive pillar 410 is soldered to the under-bump metal layer 120 via solder bumps 800; then, an underfill 210 is filled between the electronic integrated circuit chip 400 and the wafer 100'. Since the silicon mask 300' blocks the connection between the edge coupler 101 and the external space, the underfill material cannot reach the edge coupler 101 inside the silicon mask 300' during the filling process, thereby protecting the edge coupler 101 from the potential influence of the underfill material.

[0040] In this implementation, the electronic integrated circuit chip 400 can be one or more chips, and can be of different types and sizes, depending on the actual needs. Furthermore, the mounting scheme for the electronic integrated circuit chip 400 can be flip-chip reflow, thermoforming, etc. In addition, the order in which the electronic integrated circuit chip 400 and the silicon mask 300' are mounted onto the wafer 100' is not fixed and can be changed according to actual needs.

[0041] Then, the exemplary manufacturing process proceeds to... Figure 6 The intermediate state shown is achieved using a plastic sealing material. Figure 5The structure shown is encapsulated to form an encapsulation layer 220. During the encapsulation process, encapsulation material fills the upper surface of wafer 100' and encapsulates the second conductive pillar 221', the electronic integrated circuit chip 400, the underfill 210, and the silicon mask 300'. Because the silicon mask 300' blocks the connection between the edge coupler 101 and the external space, the encapsulation material cannot reach the edge coupler 101 inside the silicon mask, thus protecting the edge coupler 101 from the influence of the encapsulation material. Therefore, the encapsulation layer 220 does not directly contact the edge coupler 101.

[0042] Next, as Figure 7 As shown, the encapsulated body is thinned after molding to expose the second conductive post 221', thereby obtaining... Figure 1 The conductive structure 221 in the hole is shown. Specifically, the conductive structure includes a hole 222' formed in the molding compound 220 and a second conductive post 221' located in the hole. Furthermore, after thinning, the surface of the molding compound 220 exposes the back side of the electronic integrated circuit chip 400, such that the molding compound 220 only surrounds the side surface of the electronic integrated circuit chip 400. The molding compound 220 has low thermal conductivity; by only surrounding the side surface of the electronic integrated circuit chip 400 and exposing the back side of the electronic integrated circuit chip 400, heat dissipation of the electronic integrated circuit chip 400 is facilitated.

[0043] Next, as Figure 8 As shown, a first redistribution layer 700 and a dielectric layer 600 are formed on the surface of the thinned molding compound 220 and the back side of the electronic integrated circuit chip 400, and solder balls 900 are provided. Simultaneously, dicing alignment marks X are set on the silicon mask 300' using redistribution metal, so that the dicing equipment can align with the wafer 100' and slice it according to the specified dicing lines. Figure 9 and 10 As shown, the cutting equipment aligns the silicon mask 300' with the alignment mark and cuts the wafer 100' to obtain a single module 1001 including a photonic integrated circuit chip 100, an electronic integrated circuit chip 400, an insulating material layer 200 and an optical coupling protection structure 300.

[0044] Then, as Figure 11 As shown, a single module 1001 is soldered onto the packaging substrate 500 to obtain... Figure 1 The packaging structure shown is 1000.

[0045] Furthermore, such as Figure 12 As shown, the encapsulation structure 1000 and the optical fiber 1003 can be optically encapsulated. Specifically, the optical fiber 1003 is connected to the edge coupler 101 to achieve optical coupling.

[0046] Furthermore, it should be understood that the packaging structure 1000 of this invention can be widely applied to next-generation high-speed interconnects and computing. Therefore, this invention also relates to optoelectronic devices including the packaging structure 1000. In some embodiments, the optoelectronic device can be used for high-speed interconnects to meet the requirements of high bandwidth and low latency data transmission. In some embodiments, the optoelectronic device can be used for the computation of large artificial intelligence models to meet the demand for high computing power.

[0047] Those skilled in the art should understand that the above disclosure is merely illustrative of embodiments of the present invention, and the scope of patent protection claimed in this application is not limited thereto. Various modifications, alterations, substitutions, and other changes can be made to the disclosed embodiments without departing from the spirit and essence of the present invention, and such changes are within the scope covered by the claims of this application.

Claims

1. A package structure, characterized by, The package structure comprises: a package substrate; an electronic integrated circuit structure disposed on an upper surface of the package substrate, comprising a first redistribution layer, an electronic integrated circuit chip disposed on the redistribution layer, and an insulating material layer, wherein the insulating material layer comprises: an underfilling glue disposed on an upper surface of the electronic integrated circuit chip, and a molding layer disposed only around a side surface of the electronic integrated circuit chip and a side surface of the underfilling glue; a photonic integrated circuit chip disposed above an upper surface of the electronic integrated circuit structure, comprising an edge coupler disposed on a lower surface of the photonic integrated circuit chip; and a light coupling protection structure disposed below the photonic integrated circuit chip, a top of the light coupling protection structure being in contact with the lower surface of the photonic integrated circuit chip, and a bottom of the light coupling protection structure being in contact with the first redistribution layer to form a cavity open towards a first side surface away from the electronic integrated circuit structure, the edge coupler protruding laterally from the top of the light coupling protection structure and being in a suspended state in the cavity, the light coupling protection structure separating the edge coupler from the insulating material layer to prevent a coupling interface of the edge coupler from being contaminated by the insulating material. The lower surface of the photonic integrated circuit chip is provided with a second redistribution layer and a bump-down metal layer, the bump-down metal layer being disposed below a first portion of the second redistribution layer and being electrically connected to the redistribution layer of the first portion.

2. The package structure of claim 1, wherein, The upper surface of the electronic integrated circuit chip is provided with a conductive pillar, the bump-down metal layer being connected to the conductive pillar and forming a conductive path. The electronic integrated circuit structure further comprises a dielectric layer disposed below the first redistribution layer.

3. The package structure of claim 2, wherein, The molding layer is provided with a hole conductive structure, 4. The package structure of claim 2, wherein, the hole conductive structure electrically connecting a second portion of the second redistribution layer of the photonic integrated circuit chip to the conductive path in the first redistribution layer. The light coupling protection structure is made of silicon.

5. The package structure of claim 1, wherein, The light coupling protection structure has a bottom structure and three side walls surrounding the bottom structure, a top of the three side walls being in contact with the lower surface of the photonic integrated circuit chip.

6. The package structure of claim 5, wherein, The package structure comprises the package structure according to any one of claims 1 to 6.

7. An optoelectronic device, characterized by The package structure comprises the package structure according to any one of claims 1 to 6.

Images