Electronic device

Abstract

An electronic device is disclosed. The electronic device includes: a display panel including a base layer including an active area including a hole area, an encapsulation layer covering a light emitting element and including a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer, and a dam pattern disposed in the hole area; and an input sensor including a first sensing insulating layer, a first conductive pattern, a second sensing insulating layer, a second conductive pattern, a third sensing insulating layer, and an organic pattern layer overlapping the hole region, disposed on the first sensing insulating layer, and covered by the second sensing insulating layer. A module hole overlapping the hole region is defined, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are in contact with each other on at least one top surface of the dam pattern. Accordingly, an electronic device having improved reliability may be provided.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0048592, filed on April 11, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosure herein relates to an electronic device with improved quality. Background Technology

[0003] The electronic device is activated by an electrical signal. Such an electronic device may comprise a range of electronic components, such as a display panel for displaying images and input sensors for sensing external inputs. These electronic components can be electrically connected to each other via signal lines arranged in various ways. Utility Model Content

[0004] An electronic device with improved quality is disclosed.

[0005] An embodiment of the utility model provides an electronic device comprising: a display panel including a substrate layer, a light-emitting element, an encapsulation layer, and a dam pattern; the substrate layer including an effective region comprising a hole region and a pixel region surrounding the hole region; the light-emitting element disposed in the pixel region; the encapsulation layer covering the light-emitting element and including a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer; and the dam pattern disposed in the hole region; an input sensor disposed on the encapsulation layer and including a first sensing insulating layer, a first conductive pattern, a second sensing insulating layer, a second conductive pattern, a third sensing insulating layer, and an organic pattern layer; the organic pattern layer being superimposed on the hole region and disposed on the first sensing insulating layer and covered by the second sensing insulating layer; a cover organic layer disposed on the input sensor; and a window disposed on the cover organic layer, wherein a module hole is defined, the module hole passing through the display panel, the input sensor, and the cover organic layer and superimposed on the hole region; each of the dam patterns surrounding the module hole; and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer contacting each other on at least one top surface of the dam pattern.

[0006] In an embodiment, the dam pattern may include a first dam pattern to a fifth dam pattern that are spaced apart from each other in the direction from the pixel region toward the module hole, and each of the first dam pattern to the fifth dam pattern may include a first insulating pattern, a first pattern disposed on the first insulating pattern, a second pattern contacting the first pattern, and a second insulating pattern covering the second pattern, wherein the second pattern protrudes between the side surface of the first insulating pattern and the side surface of the second insulating pattern and defines a tip.

[0007] In an embodiment, the boundary of the organic patterned layer may be defined by a fourth dam pattern within the hole region, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer may contact each other on the fourth dam pattern.

[0008] In an embodiment, the display panel may include: a first insulating layer disposed on a substrate layer; a first semiconductor pattern disposed on the first insulating layer; a second insulating layer covering the first semiconductor pattern and disposed on the first insulating layer; a first gate superimposed on the first semiconductor pattern and disposed on the second insulating layer; a third insulating layer covering the first gate and disposed on the second insulating layer; a second semiconductor pattern disposed on the third insulating layer; a fourth insulating layer covering the second semiconductor pattern and disposed on the third insulating layer; a second gate superimposed on the second semiconductor pattern and disposed on the fourth insulating layer; a fifth insulating layer covering the second gate and disposed on the fourth insulating layer; a first connecting electrode disposed on the fifth insulating layer and connected to the first semiconductor pattern through a first contact hole, the first contact hole passing through the second insulating layer to the fifth insulating layer; a sixth insulating layer covering the first connecting electrode and disposed on the fifth insulating layer; a second connecting electrode disposed on the sixth insulating layer and connected to the first connecting electrode through a second contact hole, the second contact hole passing through the sixth insulating layer; and a seventh insulating layer covering the second connecting electrode and disposed on the sixth insulating layer, wherein one of the light-emitting elements can be connected to the second connecting electrode through a third contact hole, the third contact hole passing through the seventh insulating layer.

[0009] In an embodiment, the substrate layer may include a first organic layer, a first inorganic layer disposed on the first organic layer, a second organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the second organic layer, wherein each of the first organic layer and the second organic layer may be composed of polyimide, and each of the first inorganic layer and the second inorganic layer may be composed of inorganic material.

[0010] In an embodiment, the electronic device may further include a light-blocking pattern superimposed on the first semiconductor pattern and disposed within the second inorganic layer.

[0011] In an embodiment, each of the first to fifth insulating layers may be composed of inorganic materials, and each of the sixth and seventh insulating layers may be composed of organic materials.

[0012] In an embodiment, the first insulating pattern may be composed of the same material as the sixth insulating layer, and the second insulating pattern may be composed of the same material as the seventh insulating layer. The first pattern may be composed of the same material as the first connecting electrode, and the second pattern may be composed of the same material as the second connecting electrode.

[0013] In an embodiment, each of the first to fourth dam patterns may further include a first dummy pattern superimposed on the first pattern and disposed on the second insulating layer, and a second dummy pattern superimposed on the first dummy pattern and disposed on the third insulating layer.

[0014] In an embodiment, the fifth dam pattern may further include a dummy pattern disposed within the second inorganic layer, and the first pattern of the fifth dam pattern may be connected to the dummy pattern through a contact hole, the contact hole passing through the second inorganic layer, the first insulating layer to the fifth insulating layer and the first insulating pattern.

[0015] In an embodiment, the organic pattern layer may be disposed in the region between the first dam pattern and the second dam pattern, the region between the second dam pattern and the third dam pattern, and the region between the third dam pattern and the fourth dam pattern.

[0016] In an embodiment, the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer may be in contact with each other on the top surfaces of the second dam pattern, the third dam pattern, and the fourth dam pattern.

[0017] In an embodiment, the fourth dam pattern may further include a first additional pattern disposed on the second insulating pattern and a second additional pattern disposed on the first additional pattern, and the fifth dam pattern may further include a third additional pattern disposed on the second insulating pattern, wherein each of the first to third additional patterns may be composed of organic materials.

[0018] In one embodiment, a portion of the organic patterned layer may be disposed between the fourth dam pattern and the fifth dam pattern, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer and the third sensing insulating layer may be in contact with each other on the top surface of the fourth dam pattern and the top surface of the fifth dam pattern.

[0019] In one embodiment, the first encapsulation inorganic layer may cover the first dam pattern to the fifth dam pattern.

[0020] In an embodiment, at least two of the tips included in the first to fifth dam patterns may face each other.

[0021] In an embodiment, the first encapsulation inorganic layer and the second encapsulation inorganic layer may be in contact with each other on at least one top surface of the dam pattern, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer and the third sensing insulating layer are in contact with each other on the at least one top surface.

[0022] In an embodiment, each of the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer may be composed of inorganic materials.

[0023] In an embodiment, the electronic device may further include a fourth sensing insulating layer disposed between the cover organic layer and the third sensing insulating layer and composed of organic material.

[0024] In one embodiment, the electronic device may further include a camera module stacked with the module aperture. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0026] Figure 1 This is a perspective view of an embodiment of an electronic device based on a utility model concept;

[0027] Figure 2 This is an exploded perspective view of an embodiment of an electronic device based on a utility model concept;

[0028] Figure 3 This is a block diagram of an embodiment of an electronic device based on a utility model concept;

[0029] Figure 4 This is a plan view of an embodiment of a display panel adjacent to (beside) a hole, based on a utility model concept;

[0030] Figure 5 It is along Figure 2 A cross-sectional view of the electronic device taken by line I-I';

[0031] Figure 6 It is along Figure 2 A cross-sectional view of the electronic device taken from line II-II';

[0032] Figure 7 yes Figure 6 An enlarged sectional view of region AA';

[0033] Figure 8 This is a cross-sectional view of an embodiment of an electronic device based on a utility model concept;

[0034] Figure 9 This is a cross-sectional view of an embodiment of an electronic device based on a utility model concept;

[0035] Figure 10 This is a cross-sectional view of an embodiment of an electronic device based on a utility model concept; and

[0036] Figure 11 yes Figure 10 An enlarged sectional view of region BB'. Detailed Implementation

[0037] In this specification, it will also be understood that when a component (or region, layer, part) is referred to as being "on" another component, "connected to" or "integrated into" another component, it may be directly disposed on / directly connected to / directly integrated into said component, or there may be an intervening third component.

[0038] The same reference numerals always refer to the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of components are exaggerated for clarity. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. Terms are used only to distinguish one component from others. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise stated, singular terms may include plural forms.

[0040] In addition, terms such as "below," "under," "above," and "above" are used to explain the relationships between the components shown in the accompanying drawings. The terms can be relative concepts and are described based on the directions indicated in the drawings.

[0041] The meaning of "includes" or "contains" describes a property, a fixed quantity, a step, an operation, an element, a component, or a combination thereof, but does not exclude other properties, fixed quantities, steps, operations, elements, components, or combinations thereof.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant art, and shall not be interpreted in an overly idealized or formalized sense unless explicitly defined.

[0043] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0044] Figure 1 This is a perspective view of an embodiment of an electronic device based on a utility model concept. Figure 2 This is an exploded perspective view of an embodiment of an electronic device based on a utility model concept. Figure 3 This is a block diagram of an embodiment of an electronic device based on a utility model concept. Figure 4 This is a plan view of an embodiment of a display panel adjacent to (beside) a hole, based on a utility model concept. Figure 5It is along Figure 2 A cross-sectional view of the electronic device taken by line I-I'.

[0045] Reference Figure 1 and Figure 2 The electronic device 1000 may include a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The electronic device 1000 may display an image IM on the display surface FS on the third direction DR3. The display surface FS on which the image IM is displayed may correspond to the front surface of the electronic device 1000. The display surface FS may include a light-transmitting region TA and a border region BZA surrounding at least a portion of the light-transmitting region TA.

[0046] Electronic device 1000 can be a display device that provides an image (moving image or still image) IM to a user via a display surface FS. Electronic device 1000 can also be an input device for sensing external input TC. Figure 1 In the embodiment of the image IM, a clock and icons are shown. The display surface FS of the electronic device 1000 can be connected to the front surface FS-1 of the window 300 (see reference). Figure 2 Therefore, the light transmission area TA of the electronic device 1000 can be defined to correspond to the light transmission area TA-1 of the window 300, and the frame area BZA of the electronic device 1000 can be defined to correspond to the frame area BZA-1 of the window 300.

[0047] In this embodiment, the front (or top) or rear (or bottom) surface of each component can be defined based on the direction along which the image IM is displayed. The front and rear surfaces can be opposite each other in the third direction DR3. The normal direction of each of the front and rear surfaces can be parallel to the third direction DR3. The spacing between the front and rear surfaces in the third direction DR3 can correspond to the thickness of the electronic device 1000 in the third direction DR3.

[0048] In an embodiment of the inventive concept, the electronic device 1000 can sense external inputs (e.g., user input) TC applied from the outside. External inputs TC include various types of external inputs such as a part of the user's body, light, heat, pressure, etc. In this embodiment, the user input TC is shown as the user's hand applied to the front surface FS of the electronic device 1000.

[0049] However, this is only one embodiment. In the embodiments, as described above, for example, the external input TC can be provided in various shapes. The electronic device 1000 can sense the external input TC applied to the side or rear surface of the electronic device 1000 according to the structure of the electronic device 1000, but is not limited to the exemplary embodiments.

[0050] The electronic device 1000 in the embodiment may include an aperture region A1 superimposed on the light transmission region TA. The aperture region A1 may be defined as the area where the electronic module 400, which will be described later, is disposed. The module aperture MH of the display module 100 (see reference...) Figure 2 It can be limited to the hole region A1.

[0051] The electronic device 1000 can receive external signals desired by the electronic module 400 through the aperture region A1, or it can provide signals output from the electronic module 400 to the outside. In an embodiment of the inventive concept, the aperture region A1 can be disposed inside the light transmission region TA, thereby reducing the surface area of ​​the border region BZA.

[0052] Reference Figure 2 The electronic device 1000 may include a display module 100, a housing 200, a window 300, and an electronic module 400. The window 300 and the housing 200 may be combined to define the appearance of the electronic device 1000. The electronic device 1000 in the embodiments may also include a cover organic layer IJP disposed on the display module 100 (see reference). Figure 5 ) and the anti-reflective layer ARL (see reference) Figure 5 An explanation will be provided later.

[0053] Window 300 may include an insulating panel. In embodiments, for example, window 300 may include glass, plastic, or any combination thereof, or may be composed of glass, plastic, or any combination thereof. As described above, the front surface FS-1 of window 300 may define the display surface FS of electronic device 1000. Window 300 may include a light-transmitting region TA-1 and a frame region BZA-1 adjacent to (adjacent to) the light-transmitting region TA-1. The light-transmitting region TA-1 may be an optically transparent region. In embodiments, the light-transmitting region TA-1 may be a region having, for example, a visible light transmittance of about 90% or greater. The frame region BZA-1 may be a region having a relatively small transmittance than the light-transmitting region TA-1. The frame region BZA-1 may define the shape of the light-transmitting region TA-1.

[0054] The border area BZA-1 may have a predetermined color. The border area BZA-1 may be defined by a border layer that is separately disposed from the transparent substrate that defines the light transmission area TA-1, or it may be defined by an ink layer that is inserted into the transparent substrate and applied to the transparent substrate.

[0055] The display module 100 may include an electronic panel EP and a driving circuit IC. The electronic panel EP can display an image IM and detect user input TC. The front surface IS of the electronic panel EP includes an active area AA and a peripheral area NAA.

[0056] In this embodiment, the effective area AA can be an area where the image IM is displayed and where the external input TC is also sensed. The effective area AA can be an area in which multiple pixels PX are set.

[0057] The effective area AA may be superimposed on at least a portion of the light-transmitting area TA. In an embodiment, for example, the light-transmitting area TA may be superimposed on the entire surface or at least a portion of the effective area AA. Thus, a user can visually identify an image IM or provide external input TC through the light-transmitting area TA. However, this is only one embodiment. In an embodiment, for example, the area of ​​the effective area AA on which the image IM is displayed and the area of ​​the effective area AA on which the external input TC is sensed may be separated from each other, but is not limited to the exemplary embodiment.

[0058] The outer region NAA can be the area covered by the border region BZA. The outer region NAA is adjacent to the active region AA. The outer region NAA can surround the active region AA. The outer region NAA can be an area on which the image IM is not displayed. The driving circuitry or driving lines used to drive the active region AA can be set in the outer region NAA.

[0059] In one embodiment, a portion of the peripheral region NAA of the electronic panel EP can be bent. In another embodiment, the electronic panel EP may include, for example, a flat portion FN and a bent portion BN. The flat portion FN can be assembled substantially parallel to the plane defined by the first direction DR1 and the second direction DR2. The effective region AA can be disposed within the flat portion FN.

[0060] The curved portion BN can extend from the flat portion FN and bend along a virtual bending axis. The curved portion BN can be assembled by bending it to face the rear surface of the flat portion FN. When assembling the curved portion BN, the flat portion FN can overlap the curved portion BN on a plane, thus reducing the bezel area BZA of the electronic device 1000. As shown in the embodiment, the curved portion BN can be omitted in the electronic panel EP.

[0061] The driving circuit IC can be disposed (e.g., mounted) on the bend BN. In this embodiment, the driving circuit IC can be shown in the form of a chip, but is not limited thereto. In this embodiment, the driving circuit IC can be disposed on a separate circuit board and electrically connected to the electronic panel EP, for example, via a flexible film.

[0062] The driving circuit IC can be electrically connected to the active area AA to transmit electrical signals to the active area AA. In an embodiment, the driving circuit IC may include data driving circuitry and may, for example, provide data signals to a pixel PX disposed in the active area AA. In an alternative embodiment, the driving circuit IC may include touch driving circuitry and may be electrically connected to, for example, an input sensor disposed in the active area AA. This is only one embodiment, and the driving circuit IC may include various circuits other than those described above or may be designed to provide various electrical signals to the active area AA, but is not limited to any embodiment.

[0063] The electronic device 1000 in the embodiment may further include a main circuit board electrically connected to the electronic panel EP and the drive circuit IC. The main circuit board may include various drive circuits for driving the electronic panel EP and connectors for supplying power. The main circuit board may be a rigid printed circuit board (“PCB”), but is not limited thereto, and may also be a flexible circuit board, but is not limited to any embodiment.

[0064] The electronic module 400 can be disposed below the display module 100. The electronic module 400 can be stacked with the module aperture MH defined in the electronic panel EP, and can receive external input transmitted through the module aperture MH or output signals through the module aperture MH.

[0065] Figure 2 A single module hole MH with a circular shape is shown in an embodiment, but it is not limited thereto. The number of module holes MH can be limited to correspond to the number of electronic modules 400 disposed below the electronic panel EP, and the module hole MH can have a polygonal shape or an elliptical shape, but is not limited to any embodiment.

[0066] In an embodiment of the utility model concept, the aperture region A1 with relatively high transmittance can be disposed within the effective region AA; therefore, the electronic module 400 can be configured to overlap with the effective region AA. This prevents an increase in the surface area of ​​the border region BZA.

[0067] The housing 200 can be integrated with the window 300 to provide a predetermined interior space and define the appearance of the electronic device 1000. Components of the electronic device 1000, such as the display module 100 and the electronic module 400, can be accommodated within the interior space.

[0068] The housing 200 may comprise a material with relatively high rigidity. In embodiments, for example, the housing 200 may comprise glass, plastic, or metal, or may comprise multiple frames and / or panels comprising a combination of glass, plastic, and metal, or composed of a combination of glass, plastic, and metal. The housing 200 can stably protect the components of the electronic device 1000 housed within its internal space from external impacts.

[0069] Reference Figure 3 The electronic device 1000 may include a display module 100, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 100, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0070] As an example, Figure 3 The display panel DP and input sensor ISL are shown among the components of the display module 100. The display panel DP may be a component that generates an image IM. The image IM generated by the display panel DP can be displayed on the display surface FS through the light transmission area TA so that it is visible to an external user. The input sensor ISL can sense external input TC applied from the outside. As described above, the input sensor ISL can sense external input TC provided to the window 300.

[0071] The power module PM can supply the power required for the overall operation of the electronic device 1000. The power module PM may include a general-purpose battery module.

[0072] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for driving the electronic device 1000. The first electronic module EM1 may be directly disposed (e.g., mounted) on a motherboard electrically connected to the electronic panel EP, or it may be disposed (e.g., mounted) on a separate board and electrically connected to the motherboard via a connector (not shown).

[0073] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Parts of the module may not be mounted (e.g., installed) on the motherboard, but may be electrically connected to the motherboard via a flexible circuit board.

[0074] The control module CM can control the overall operation of the electronic device 1000. The control module CM can be a microprocessor. In an embodiment, the control module CM can, for example, activate or deactivate the display module 100. The control module CM can control other modules such as the image input module IIM or the audio input module AIM based on touch signals received from the electronic panel EP.

[0075] The wireless communication module™ can communicate via Bluetooth. ® Alternatively, it can transmit / receive wireless signals to or from another terminal via a Wi-Fi line. The wireless communication module TM can transmit / receive audio signals over a common communication line. The wireless communication module TM includes a transmitter TM1 that modulates and transmits the signal to be transmitted and a receiver TM2 that demodulates the received signal.

[0076] The Image Input Module (IIM) processes image signals to convert them into image data that can be displayed on the Electronic Panel (EP). The Audio Input Module (AIM) receives external audio signals via a microphone during recording or voice recognition mode to convert the received audio signals into electroacoustic data.

[0077] The external interface IF serves as an interface for connecting to external chargers, wired / wireless data ports, and card slots (e.g., memory cards and subscriber identity module / user identity module (“SIM / UIM”) cards).

[0078] The second electronic module EM2 may include an audio output module AOM, a light-emitting module LM, a light-receiving module LRM, and a camera module CMM. These components can be directly mounted (e.g., installed) on a motherboard, mounted (e.g., installed) on a separate board and electrically connected to an electronic panel EP via a connector (not shown), or electrically connected to the first electronic module EM1.

[0079] The audio output module AOM converts audio data received from the wireless communication module TM or stored in the memory MM to output the converted audio data to the outside.

[0080] A light-emitting module (LM) generates and outputs light. The LM can output infrared light. The LM may include a light-emitting diode (“LED”). A light-receiving module (LRM) can sense infrared light. The LRM can be activated when infrared light of a predetermined level or higher is sensed. The LRM may include a complementary metal-oxide-semiconductor (“CMOS”) sensor. The infrared light generated in the LM can be output and then reflected by an external object (e.g., a user's finger or face), and the reflected infrared light can be incident on the LRM. A camera module (CMM) captures an external image.

[0081] The electronic module 400 in an embodiment of the utility model concept may include at least one of the components of the second electronic module EM2. In embodiments, the electronic module 400 may include at least one of, for example, a camera, a speaker, an optical detection sensor, and a thermal detection sensor. The electronic module 400 may sense external objects received through the aperture region A1, or provide sound signals such as speech to the outside through the aperture region A1. Furthermore, the electronic module 400 may include multiple components, but is not limited to the exemplary embodiments. Although not shown, the electronic module 400 may be attached to the electronic panel EP using a separate adhesive.

[0082] Figure 4 The display panel DP (reference) is shown. Figure 3The effective area AA in the module hole MH is the portion XX' that is adjacent to (adjacent to) MH.

[0083] Reference Figure 4 Most of the pixels PX in the display panel DP can be set in pixel region A2, and some of the pixels PX can be set in pixel region A2 along the boundary between hole region A1 and pixel region A2 and separated from hole region A1.

[0084] The module aperture MH can be confined within the effective area AA. Therefore, at least some of the pixels PX can be configured to be adjacent to (adjacent to) the module aperture MH and separated from each other, with the module aperture MH located between them.

[0085] At least one dam pattern DMP can be disposed in the hole area A1 of the display panel DP. Electronic device 1000 in the embodiment (see reference) Figure 2 The dam pattern DMP can block moisture and / or oxygen from being introduced into the pixel PX through the module aperture MH. Additionally, during the process of forming the module aperture MH, etchant can be prevented from being introduced into the display panel DP through the module aperture MH. Therefore, a display panel DP with improved quality can be achieved. A detailed description of the dam pattern DMP will be provided later.

[0086] The dam pattern DMP can be set in the hole region A1 and surround at least a portion of the module hole MH. In a plane, the dam pattern DMP can have a closed line shape surrounding the module hole MH.

[0087] In one embodiment, the filler may be disposed inside the module hole MH. The filler may include a polymer resin. When the filler is disposed inside the module hole MH, it can provide a flat surface on the component disposed on the module hole MH.

[0088] A portion of each of the signal lines SGL1 and SGL2 connected to pixel PX can be disposed in the aperture region A1. Signal lines SGL1 and SGL2 can be connected to pixel PX via aperture region A1, with pixels PX separated from each other and module aperture MH located between them. For ease of explanation, Figure 4 Two signal lines, SGL1 and SGL2, are shown among the multiple signal lines connected to pixel PX.

[0089] The first signal line SGL1 may extend along the first direction DR1. The first signal line SGL1 may be connected to pixels PX in the same row arranged along the first direction DR1. In an embodiment, the first signal line SGL1 may correspond to, for example, one of the scan lines connected to the pixel PX.

[0090] A portion of pixel PX connected to the first signal line SGL1 can be positioned on the left side of the module aperture MH, and the remaining (other) portion of pixel PX can be positioned on the right side of the module aperture MH. Therefore, even if a portion of pixel PX relative to the module aperture MH is omitted, pixels PX in the same row of the first signal line SGL1 can be connected via substantially the same scan signal on / off.

[0091] The second signal line SGL2 may extend along the second direction DR2. The second signal line SGL2 may be connected to a pixel PX in the same column arranged along the second direction DR2. In an embodiment, the second signal line SGL2 may correspond to, for example, one of the data lines connected to the pixel PX.

[0092] A portion of pixel PX connected to the second signal line SGL2 can be positioned above the module aperture MH, and the remaining (other) portion of pixel PX can be positioned below the module aperture MH. Therefore, even if the portion of pixel PX relative to the module aperture MH is omitted, pixels PX in the same row connected to the second signal line SGL2 can receive data signals through the same line.

[0093] At least one of the first signal line SGL1 and the second signal line SGL2 can be broken at the point where the first signal line SGL1 and the second signal line SGL2 intersect within the hole region A1. Therefore, a connection pattern can also be provided, which is set in a layer different from the layer of the broken signal line to connect the broken portion. However, the connection relationship between pixels PX that are separated from each other and in which the module hole MH is located is not limited to this.

[0094] Figure 5 It is along Figure 2 A sectional view taken by line I-I'. Figure 5 In the middle, it can be omitted. Figure 1 The housing 200 described in the text. Figure 5 It shows the relationship with Figure 2 The cross-section of the electronic device 1000 corresponding to pixel PX described in the text.

[0095] Reference Figure 5 The electronic device 1000 in the embodiment may include a display module 100, an organic cover layer IJP, an anti-reflective layer ARL, and so on. Figure 2 The housing 200 and window 300 are described in the diagram. The display module 100 may include a display panel DP and an input sensor ISL.

[0096] Figure 2 The pixel PX described herein may include a light-emitting element (LD) and a pixel driving circuit. The pixel driving circuit may include multiple transistors and capacitors. Figure 5 It shows that it includes Figure 2 The two transistors T1 and T2 in pixel PX described herein are used as examples. In an embodiment, transistors T1 and T2 are included in pixel PX (refer to...). Figure 2 The transistors in the pixel driving circuit can be oxide semiconductors. In embodiments, each of the transistors may include, for example, a semiconductor layer comprising a metal oxide. However, the construction of the pixel driving circuit is not limited to this. Some of the transistors included in the pixel driving circuit may include silicon transistors, while others may include oxide transistors.

[0097] The display module 100 in this embodiment may include a display panel DP and an input sensor ISL. The input sensor ISL may be directly disposed on the display panel DP. The cover organic layer IJP, the anti-reflective layer ARL, and the window 300 may be disposed on the display module 100.

[0098] The display panel DP may include a substrate layer 110, a circuit element layer 120, a display element layer 130, and an encapsulation layer 140.

[0099] The display panel DP may also include functional layers such as an anti-reflective layer and a refractive index adjustment layer. The circuit element layer 120 may include at least a plurality of insulating layers and circuit elements. In the following, the insulating layer may include organic layers and / or inorganic layers.

[0100] An insulating layer, a semiconductor layer, and a conductive layer can be formed on the substrate layer 110 by coating, deposition, or other methods. Subsequently, the insulating layer, semiconductor layer, and conductive layer can be selectively patterned using photolithography. In this way, semiconductor patterns, conductive patterns, signal lines, etc., can be formed.

[0101] The substrate layer 110 may be a substrate layer on which the circuit element layer 120 is disposed, or other components thereof. The substrate layer 110 may have a structure in which layers comprising or composed of organic materials and layers comprising or composed of inorganic materials are alternately stacked. In an embodiment, the substrate layer 110 may include, for example, a first organic layer PI1, a first inorganic layer BA1, a second organic layer PI2, and a second inorganic layer BA2 sequentially stacked.

[0102] The first organic layer PI1 may be disposed at the bottommost side. The first organic layer PI1 may include an organic material. In embodiments, the first organic layer PI1 may include at least one of, for example, polyimide (“PI”), polyethylene naphthalate (“PEN”), polyethylene terephthalate (“PET”), polyarylate, polycarbonate (“PC”), polyetherimide (“PEI”), and polyethersulfone (“PES”).

[0103] The first inorganic layer BA1 may be disposed on the first organic layer PI1. The first inorganic layer BA1 may include an inorganic material. In an embodiment, the first inorganic layer BA1 may include at least one of, for example, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, silicon nitride, zirconium oxide, hafnium oxide, and amorphous silicon.

[0104] The second organic layer PI2 can be disposed on the first inorganic layer BA1. The second organic layer PI2 can include organic materials. The organic materials included in the second organic layer PI2 can be the same as the organic materials included in the first organic layer PI1.

[0105] The second inorganic layer BA2 can be disposed on the first organic layer PI1. The second inorganic layer BA2 may include inorganic materials. The inorganic materials included in the second inorganic layer BA2 may be the same as the inorganic materials included in the first inorganic layer BA1. The second inorganic layer BA2 may correspond to the barrier layer.

[0106] However, this embodiment is not limited to this, and the substrate layer 110 may be a single layer. Here, the substrate layer 110 may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide resin layer, and its material is not particularly limited. In addition, the substrate layer 110 may include glass, metal, or organic / inorganic composite materials.

[0107] According to this embodiment, a light-blocking pattern BMI can also be provided, which is disposed within the second inorganic layer BA2. The light-blocking pattern BMI can be superimposed on a first semiconductor pattern included in the first transistor T1. Alternatively, the light-blocking pattern BMI can be superimposed on a second semiconductor pattern included in the second transistor T2. The light-blocking pattern BMI can include a metal. In this embodiment, the light-blocking pattern BMI can include, for example, molybdenum (Mo).

[0108] The first insulating layer 10 may be disposed on the second inorganic layer BA2 of the substrate layer 110. The first insulating layer 10 may correspond to the buffer layer. The first insulating layer 10 may include a silicon oxynitride layer, a silicon oxide layer, and / or a silicon nitride layer. In addition, the silicon oxynitride layer may have a single-layer or multi-layer structure, but is not limited to any embodiment.

[0109] The first semiconductor pattern of the first transistor T1 can be disposed on the first insulating layer 10. Figure 5 Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern can also be set in pixel PX (see reference). Figure 4 In other regions of the first semiconductor pattern. Depending on whether the first semiconductor pattern is doped, the first semiconductor pattern can have different electrical properties. The first semiconductor pattern can include doped regions and undoped regions. The doped regions can be doped with N-type dopant or P-type dopant. A P-type transistor includes a doped region in which P-type dopant is doped.

[0110] The source S1, active region AT1, and drain D1 of the first transistor T1 can be formed by a first semiconductor pattern. The source S1 and drain D1 of the first transistor T1 can be separated from each other, and the active region AT1 is located between them.

[0111] The connection signal line SCL can be disposed on the first insulating layer 10. The connection signal line SCL can be connected to the pixel PX (see reference). Figure 4 Any one of the multiple transistors in ).

[0112] The second insulating layer 20 may cover the first semiconductor pattern and the connection signal line SCL and may be disposed on the first insulating layer 10. The second insulating layer 20 may include an inorganic layer and / or an organic layer and has a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be an inorganic layer.

[0113] The gate GE1 of the first transistor T1 can be disposed on the second insulating layer 20. The gate GE1 can be part of a metal pattern. The gate GE1 of the first transistor T1 can be stacked with the active region AT1 of the first transistor T1. In the process of doping the first semiconductor pattern, the gate GE1 of the first transistor T1 can be used as a mask.

[0114] A third insulating layer 30 covering the gate GE1 may be disposed on the second insulating layer 20. The third insulating layer 30 may include an inorganic layer and / or an organic layer and have a single-layer or multi-layer structure. In this embodiment, the third insulating layer 30 may be an inorganic layer.

[0115] The upper electrode UE can be disposed on the third insulating layer 30. The upper electrode UE can be stacked with the gate GE1. The upper electrode UE can be part of a metal pattern or a doped semiconductor pattern. A portion of the gate GE1 and the upper electrode UE stacked with said portion of the gate GE1 can define a capacitor included in the pixel PX. In embodiments of the inventive concept, the upper electrode UE can be omitted.

[0116] A fourth first insulating layer 40-1 covering the upper electrode UE can be disposed on the third insulating layer 30. In this embodiment, the fourth insulating layer 40 may include at least one silicon oxide layer and at least one silicon nitride layer alternately stacked.

[0117] The second semiconductor pattern of the second transistor T2 can be disposed on the third insulating layer 30. The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor.

[0118] In embodiments, for example, oxide semiconductors may include metal oxides (such as oxides of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti)) or metals (such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), and combinations thereof). Oxide semiconductors may include indium tin oxide (“ITO”), indium gallium zinc oxide (“IGZO”), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc indium oxide (“ZIO”), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (“IZTO”), zinc tin oxide (“ZTO”), etc.

[0119] The source S2, active region AT2, and drain D2 of the second transistor T2 can be formed from a second semiconductor pattern. Each of the source S2 and drain D2 may include metal reduced from a metal-oxide-semiconductor. Each of the source S2 and drain D2 may have a predetermined thickness from the top surface of the second semiconductor pattern and may include a metal layer containing the reduced metal.

[0120] A fourth second insulating layer 40-2 covering the second semiconductor pattern can be disposed on the third insulating layer 30. In this embodiment, the fourth second insulating layer 40-2 can be a single layer of silicon oxide. In the description, the fourth first insulating layer 40-1 and the fourth second insulating layer 40-2 can be collectively referred to as the fourth insulating layer 40.

[0121] The gate GE2 of the second transistor T2 can be disposed on the fourth insulating layer 40. The gate GE2 can be part of a metal pattern. The gate GE2 of the second transistor T2 can be stacked with the active region AT2 of the second transistor T2.

[0122] A fifth insulating layer 50 covering the gate GE2 may be disposed on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 may include at least one silicon oxide layer and at least one silicon nitride layer alternately stacked.

[0123] At least one insulating layer may also be disposed on the fifth insulating layer 50. As in this embodiment, a sixth insulating layer 60 and a seventh insulating layer 70 may be disposed on the fifth insulating layer 50. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer and may have a single-layer or multi-layer structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be a single-layer polyimide resin layer.

[0124] However, this embodiment is not limited thereto. In the embodiment, each of the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of, for example, acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins.

[0125] The first connection electrode CNE1 can be disposed on the fifth insulating layer 50. The first connection electrode CNE1 can be connected to the connection signal line SCL through a first contact hole passing through the second insulating layer 20 to the fifth insulating layer 50.

[0126] The second connecting electrode CNE2 can be disposed on the sixth insulating layer 60. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through a second contact hole passing through the sixth insulating layer 60.

[0127] A light-emitting element (LD) may be disposed on a seventh insulating layer 70. A first electrode AE ​​of the light-emitting element LD may be disposed on the seventh insulating layer 70. A pixel defining layer (PDL) is disposed on the seventh insulating layer 70. The pixel defining layer (PDL) may define a display opening that exposes at least a portion of the first electrode AE. In this embodiment, the pixel defining layer (PDL) may include a light-absorbing material. In this embodiment, the pixel defining layer (PDL) may be, for example, black.

[0128] A spacer SPC can be disposed on the pixel defining layer PDL. The spacer SPC prevents the pixel defining layer PDL, which has a black component, from being externally visible, and a groove for securing a support member of a mask in the process of forming a light-emitting pattern EL through a deposition process can be defined in the spacer SPC. The groove can be defined by penetrating at least a portion of the spacer SPC. The spacer SPC can be an organic layer comprising polyimide. The spacer SPC in the embodiments can be transparent. A spacer opening exposing a portion of the first electrode AE ​​and overlapping with a display opening can be defined in the spacer SPC. The emission region LA can be defined to correspond to the spacer opening.

[0129] The light-emitting pattern EL can be disposed inside the spacer opening and on the first electrode AE. In an embodiment of the inventive concept, a hole control layer can be disposed between the first electrode AE ​​and the light-emitting pattern EL. The hole control layer may include a hole transport layer and may also include a hole injection layer. An electron control layer can be disposed between the light-emitting pattern EL and the second electrode CE. The electron control layer includes an electron transport layer and may also include an electron injection layer.

[0130] The second electrode CE can be disposed on the light-emitting pattern EL. An electronic control layer can be disposed between the light-emitting pattern EL and the second electrode CE. The electronic control layer may include an electron transport layer and an electron injection layer. The second electrode CE can be disposed on the light-emitting pattern EL. The electronic control layer, the hole control layer, and the second electrode CE can be jointly disposed on multiple pixels PX (see reference). Figure 4 )superior.

[0131] Encapsulation layer 140 may cover the light-emitting element (LD). Encapsulation layer 140 may include a first encapsulation inorganic layer 141, an encapsulation organic layer 142, and a second encapsulation inorganic layer 143, sequentially stacked. However, the layers constituting encapsulation layer 140 are not limited to these. Each of encapsulation inorganic layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Each of encapsulation inorganic layers 141 and 143 may have a multilayer structure. Encapsulation organic layer 142 may include, but is not limited to, an acrylic organic layer.

[0132] The input sensor ISL may include at least one conductive layer (or at least one sensor conductive layer) containing a conductive pattern and at least one sensing insulating layer (or at least one sensor insulating layer).

[0133] In this embodiment, the input sensor ISL may include a first sensing insulating layer 210, a first conductive pattern TML1, a second sensing insulating layer 220, a second conductive pattern TML2, a third sensing insulating layer 230, and a fourth sensing insulating layer 240. As an example, Figure 5 A first conductive pattern TML1 included in a first conductive layer and a second conductive pattern TML2 included in a second conductive layer are shown.

[0134] The first sensing insulating layer 210 can be directly disposed on the display panel DP. That is, the first sensing insulating layer 210 can contact the second encapsulation inorganic layer 143. The first sensing insulating layer 210 can be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0135] A first conductive pattern TML1 may be disposed on a first sensing insulating layer 210. A second conductive pattern TML2 may be disposed on a second sensing insulating layer 220. Each of the first conductive pattern TML1 and the second conductive pattern TML2 may have a single-layer structure or a multilayer structure sequentially stacked. The second conductive pattern TML2 may include conductive lines defining a mesh electrode. The conductive lines of the second conductive pattern TML2 and the first conductive pattern TML1 may or may not be connected to each other through contact holes passing through the second sensing insulating layer 220. The connection relationship between the conductive lines of the first conductive pattern TML1 and the second conductive pattern TML2 may be determined according to the type of sensor forming the input sensor ISL.

[0136] The first conductive pattern TML1 and the second conductive pattern TML2 may include a metal layer or a transparent conductive layer, each of which has a monolayer structure. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or any alloy thereof. The transparent conductive layer may include materials such as ITO, IZO, or zinc oxide (ZnO). x Transparent conductive oxides such as poly(3,4-ethylenedioxythiophene) (“PEDOT”), metal nanowires, graphene, etc., can also be used.

[0137] The first conductive patterns TML1 and TML2, having a multilayer structure, may include metal layers. The metal layers may have a three-layer structure of titanium / aluminum / titanium. The multilayer conductive layers may include at least one metal layer and at least one transparent conductive layer.

[0138] The second sensing insulating layer 220 may cover the first conductive pattern TML1 and may be disposed on the first sensing insulating layer 210. The second conductive pattern TML2 may be disposed on the second sensing insulating layer 220. The third sensing insulating layer 230 may cover the second conductive pattern TML2 and may be disposed on the second sensing insulating layer 220. Each of the second sensing insulating layer 220 and the third sensing insulating layer 230 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0139] A fourth sensing insulating layer 240 may be disposed on the third sensing insulating layer 230. The fourth sensing insulating layer 240 may compensate for height differences that occur during the process of forming the component disposed below the fourth sensing insulating layer 240. Therefore, the fourth sensing insulating layer 240 may include an organic material.

[0140] An organic cover layer IJP can be disposed on the input sensor ISL. The organic cover layer IJP can compensate for the height difference generated during the process of forming the display panel DP and the input sensor ISL. Therefore, a flat surface can be provided to the component disposed on the display panel DP. The organic cover layer IJP can include organic materials. The organic cover layer IJP can be formed on the fourth sensing insulating layer 240 by an inkjet process.

[0141] The display module 100 in this embodiment may further include an anti-reflective layer ARL. The anti-reflective layer ARL may be disposed between the cover organic layer IJP and the window 300. The anti-reflective layer ARL can reduce the reflection of light incident from the outside of the electronic device 1000. That is, the anti-reflective layer ARL can reduce the external light reflectivity of the electronic device 1000. The anti-reflective layer ARL in this embodiment may include a polarizing layer, a phaser, a destructive interference structure, or multiple color filters.

[0142] The first adhesive layer AD1 may be disposed between the antireflective layer ARL and the cover organic layer IJP to bond the antireflective layer ARL to the cover organic layer IJP. The first adhesive layer AD1 may include at least one of optically clear adhesive, optically clear adhesive resin and pressure-sensitive adhesive (PSA).

[0143] Window 300 may be disposed on the anti-reflective layer ARL. Second adhesive layer AD2 may be disposed between the anti-reflective layer ARL and window 300 to bond the anti-reflective layer ARL to window 300. Second adhesive layer AD2 may comprise the same material as the first adhesive layer AD1.

[0144] Figure 6 It is along Figure 2 A cross-sectional view of the electronic device taken from line II-II'. Figure 7 yes Figure 6 An enlarged sectional view of region AA'. Figure 6 A cross-sectional view is shown of the hole region A1 in the effective area AA and the pixel region A2 adjacent to (adjacent to) the hole region A1.

[0145] The electronic device 1000 in this embodiment may have a display panel DP, an input sensor ISL, and a module aperture MH stacked with the aperture region A1, with an organic cover layer IJP passing through the module aperture MH. The module aperture MH may be stacked with the electronic module 400. Specifically, the module aperture MH may be stacked with the camera module CMM of the electronic module 400 (see reference). Figure 3 (Stacked)

[0146] Figure 5 At least one of the first adhesive layer AD1, the anti-reflective layer ARL, the second adhesive layer AD2, and the window 300 described herein may cover the module hole MH to prevent the side surfaces defining the module hole MH of each of the display panel DP, the input sensor ISL, and the cover organic layer IJP from being exposed to the outside. In an embodiment, a resin layer disposed inside the module hole MH may also be provided.

[0147] The effective area AA of the display panel DP may include an aperture region A1 and a pixel region A2. In this specification, the aperture region A1 and the pixel region A2 may be defined in the substrate layer 110. The aperture region A1 may be defined as an area superimposed on the electronic module 400, and the pixel region A2 may surround at least a portion of the aperture region A1 within the effective area AA. The pixel region A2 may be provided with... Figure 2 The region of pixel PX described in the text.

[0148] The display panel DP may include a first dam pattern DMP1 to a fifth dam pattern DMP5 disposed in the hole region A1. The first dam pattern DMP1 to the fifth dam pattern DMP5 may be arranged sequentially in the direction from the pixel region A2 toward the module hole MH. On the plane, each of the first dam pattern DMP1 to the fifth dam pattern DMP5 may have a closed line shape surrounding the module hole HM.

[0149] like Figure 6 As shown, each of the first dam pattern DMP1 to the fifth dam pattern DMP5 may include a first insulating pattern 60-P, a second insulating pattern 70-P, a first pattern SD1, and a second pattern SD2. The first pattern SD1 and the second pattern SD2 may be in contact with each other.

[0150] Each of the first insulating pattern 60-P and the second insulating pattern 70-P may include an organic material. The first insulating pattern 60-P may be made from... Figure 5 The patterned portion of the sixth insulating layer 60 described herein, and the second insulating pattern 70-P may be derived from... Figure 5 The patterned portion of the seventh insulating layer 70 described herein. Therefore, the first insulating pattern 60-P can be disposed on the fifth insulating layer 50.

[0151] The first pattern SD1 can be with Figure 5 The first connecting electrode CNE1 described herein is formed using the same process and may include the same material as the first connecting electrode CNE1. The second pattern SD2 may be... Figure 5 The second connecting electrode CNE2 described herein is formed by the same process and may include the same material as the second connecting electrode CNE2. Each of the first pattern SD1 and the second pattern SD2 may include a first layer, a second layer, and a third layer that are sequentially stacked, each of the first and third layers may include titanium, and the second layer may include aluminum.

[0152] In an embodiment of the utility model concept, a second pattern SD2 included in each of the first dam patterns DMP1 to the fifth dam patterns DMP5 may protrude from the side surface of the first insulating pattern 60-P and the side surface of the second insulating pattern 70-P to define a tip TIP. At least two tips in adjacent (adjacent) dam patterns included in the first dam patterns DMP1 to the fifth dam patterns DMP5 may face each other.

[0153] According to this embodiment, the first dam pattern DMP1 to the fifth dam pattern DMP5 can be covered by the first encapsulation inorganic layer 141. Therefore, the second pattern SD2 of the defined tip TIP of each of the first dam pattern DMP1 to the fifth dam pattern DMP5 can also be covered by the first encapsulation inorganic layer 141.

[0154] The first dam pattern DMP1 may include two first patterns SD1 disposed on the first insulating pattern 60-P and spaced apart from each other, and a second pattern SD2 that contacts the first pattern SD1 respectively. The second pattern SD2 may protrude from the side surfaces of the first insulating pattern 60-P and the second insulating pattern 70-P to define two tip portions TIP.

[0155] In an embodiment, a sub-dam pattern DMP0 may also be provided adjacent to the boundary between pixel region A2 and hole region A1 and located at the end of pixel region A2. The sub-dam pattern DMP0 may include a first pattern SD1 located at the end of the sixth insulating layer 60 and a second pattern SD2 contacting the first pattern SD1. The second pattern SD2 may be covered by the seventh insulating layer 70. The second pattern SD2 of the sub-dam pattern DMP0 may protrude between the sixth insulating layer 60 and the seventh insulating layer 70 to define a tip TIP.

[0156] In this embodiment, one of the tip TIPs of the sub-dam pattern DMP0 and the tip TIP of the first dam pattern DMP1 can face each other.

[0157] The tip of the second dam pattern DMP2 can protrude to the left in the cross section, and the remaining (other) tip of the first dam pattern DMP1 and the tip of the second dam pattern DMP2 can face each other.

[0158] The tip of the third dam pattern DMP3 can protrude to the left in the cross-section.

[0159] like Figure 7 As shown, the fourth dam pattern DMP4 may include two second patterns SD2-L and SD2-R disposed on the first pattern SD1 and spaced apart from each other. Pattern SD2-L (2-1) may protrude to the left side of the fourth dam pattern DMP4 in the cross-section, and pattern SD2-R (2-2) may protrude to the right side of the fourth dam pattern DMP4 in the cross-section. Therefore, two tip portions may be defined within the fourth dam pattern DMP4. The tip portion defined by pattern SD2-1 (2-1) may protrude toward the third dam pattern DMP3. The tip portion defined by pattern SD2-R (2-2) may protrude toward the fifth dam pattern DMP5.

[0160] The tip of the fifth dam pattern DMP5 can protrude in the direction of the module hole MH.

[0161] However, Figure 6The shape and number of the first dam pattern DMP1 to the fifth dam pattern DMP5 shown are not limited to this, and the protruding direction of the tip TIP included in each of the first dam pattern DMP1 to the fifth dam pattern DMP5 may also not be limited to this.

[0162] According to this embodiment, each of the first dam pattern DMP1 to the fourth dam pattern DMP4 may further include a first dummy pattern G1 and a second dummy pattern G2. The first dummy pattern G1 may be disposed on the second insulating layer 20 and covered by the third insulating layer 30. The second dummy pattern G2 may be superimposed on the first dummy pattern G1, may be disposed on the third insulating layer 30, and may be covered by the fourth insulating layer 40. The first dummy pattern G1 may be superimposed on the second dam pattern 20 and covered by the third insulating layer 30. Figure 5 The gate GE1 of the first transistor T1 described herein is formed using the same process and may include the same material as the gate GE1. The second dummy pattern G2 may be consistent with... Figure 5 The gate GE2 of the second transistor T2 described herein is formed using the same process and may include the same material as the gate GE2. Since the first dam pattern DMP1 to the fourth dam pattern DMP4 include a first dummy pattern G1 and a second dummy pattern G2, the height of each of the dam patterns can be adjusted.

[0163] The fifth dam pattern DMP5 can also include a dummy pattern BP. The dummy pattern BP can be set... Figure 5 The second inorganic layer BA2 of the substrate layer 110 described herein. The first pattern SD1 of the fifth dam pattern DMP5 can be superimposed on the dummy pattern BP through a contact hole that passes through a portion of the second inorganic layer BA2 that overlaps with the dummy pattern BP, the first insulating layer 10 to the fifth insulating layer 50, and the first insulating pattern 60-P.

[0164] The input sensor ISL in an embodiment of the utility model concept may include an organic patterned layer YOC. The organic patterned layer YOC may be stacked with the hole region A1 and may be disposed between the first sensing insulating layer 210 and the second sensing insulating layer 220. The organic patterned layer YOC may compensate for height differences generated during the manufacturing process of the first dam pattern DMP1 to the fifth dam pattern DMP5.

[0165] According to this embodiment, the organic patterned layer YOC can be disposed from a groove defined between the first dam pattern DMP1 and the second dam pattern DMP2 to the fourth dam pattern DMP4. According to this embodiment, the boundary of the organic patterned layer YOC within the hole region A1 can be defined by the fourth dam pattern DMP4.

[0166] As in the utility model concept, an electronic device 1000 that defines a module aperture MH in an effective region AA provides moisture and / or oxygen introduced from the module aperture MH to the light-emitting element LD via it along an organic material disposed in the aperture region A1 (see reference). Figure 5 The path in ) . In an embodiment of the utility model concept, the boundary of the organic patterned layer YOC can be defined by the fourth dam pattern DMP4, such as Figure 7 As shown, the top surface DU of the fourth dam pattern DMP4 can be exposed from the organic pattern layer YOC. Therefore, the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 can contact each other on the top surface DU of the fourth dam pattern DMP4 (i.e., on the top surface DU of the fourth dam pattern DMP4, the first sensing insulating layer 210 can directly contact the second encapsulation inorganic layer 143, the second sensing insulating layer 220 can directly contact the first sensing insulating layer 210, and the third sensing insulating layer 230 can directly contact the second sensing insulating layer 220), each of the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 comprising inorganic material. Additionally, the first encapsulation inorganic layer 141 can contact the second encapsulation inorganic layer 143 on the top surface DU of the fourth dam pattern DMP4.

[0167] In this specification, the area in which the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220 and the third sensing insulating layer 230 contact each other can be defined as the “bonding area CA” on any of the top surfaces.

[0168] According to this embodiment, moisture and / or oxygen introduced from the module aperture MH are introduced into the light-emitting element LD (see reference). Figure 5 The path in the junction area CA can be blocked. Therefore, it is possible to configure an LD (light-emitting element) with improved lifespan and reliability. Figure 5 ) electronic device 1000.

[0169] Figure 8 This is a cross-sectional view of an embodiment of an electronic device based on a utility model concept. Figure 9 This is a cross-sectional view of an embodiment of an electronic device based on a utility model concept. Figure 10 This is a cross-sectional view of an embodiment of an electronic device based on a utility model concept. Figure 11 yes Figure 10 An enlarged sectional view of area BB'. Same / similar reference numerals are used with... Figures 1 to 7 Components that are the same as or similar to those described in the previous section are excluded, and duplicate descriptions are omitted.

[0170] Figures 8 to 10The electronic devices 1000-1, 1000-2, and 1000-3 described herein only show those included in the display module 100 (see reference 1000-1). Figure 2 The display panel DP and input sensor ISL in the display module 100 (see reference) will be omitted. Figure 2 ) on the component.

[0171] Reference Figure 8 The electronic device 1000-1 in the embodiment may include a display panel DP and an input sensor ISL. The display panel DP may include a substrate layer 110, a circuit element layer 120, a display element layer 130, and an encapsulation layer 140. The display panel DP may include a first dam pattern DMP1 to a fifth dam pattern DMP5 disposed in the hole region A1. The first dam pattern DMP1 to the fifth dam pattern DMP5 may be arranged sequentially in a direction from the pixel region A2 toward the module hole MH. On a plane, each of the first dam pattern DMP1 to the fifth dam pattern DMP5 may have a closed line shape surrounding the module hole HM.

[0172] The input sensor ISL may include a first sensing insulating layer 210, a first conductive pattern TML1, a second sensing insulating layer 220, a second conductive pattern TML2, a third sensing insulating layer 230, and a fourth sensing insulating layer 240.

[0173] The input sensor ISL in this embodiment may include an organic patterned layer YOC-1. The organic patterned layer YOC-1 may be stacked with the hole region A1 and disposed between the first sensing insulating layer 210 and the second sensing insulating layer 220. The organic patterned layer YOC-1 may compensate for the height difference generated in the process of manufacturing the first dam pattern DMP1 to the fifth dam pattern DMP5.

[0174] According to this embodiment, the organic patterned layer YOC-1 can be disposed from the groove defined between the first dam pattern DMP1 and the second dam pattern DMP2 to the fifth dam pattern DMP5. According to this embodiment, the boundary of the organic patterned layer YOC-1 within the hole region A1 can be defined by the fifth dam pattern DMP5.

[0175] The organic patterned layer YOC-1 may include a first pattern Y-1 disposed from a first dam pattern DMP1 to a fourth dam pattern DMP4, and a second pattern Y-2 disposed between the fourth dam pattern DMP4 and the fifth dam pattern DMP5. The first pattern Y-1 and the second pattern Y-2 may be portions that are broken off by the fourth dam pattern DMP4 during the process of forming the organic patterned layer YOC-1 by applying organic materials.

[0176] The top surface of the fourth dam pattern DMP4 can be exposed between the first pattern Y-1 and the second pattern Y-2, and the top surface of the fifth dam pattern DMP5 can be exposed from the second pattern Y-2. According to this embodiment, the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 can contact each other on the top surface of the fourth dam pattern DMP4. Additionally, the first encapsulation inorganic layer 141 and the second encapsulation inorganic layer 143 can contact each other on the top surface of the fourth dam pattern DMP4. Therefore, the first bonding region CA1 can be defined on the top surface of the fourth dam pattern DMP4.

[0177] Furthermore, the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 can contact each other on the top surface of the fifth dam pattern DMP5. Additionally, the first encapsulation inorganic layer 141 and the second encapsulation inorganic layer 143 can contact each other on the top surface of the fifth dam pattern DMP5. Therefore, the second bonding region CA2 can be defined on the top surface of the fifth dam pattern DMP5.

[0178] According to this embodiment, even when the organic pattern layer YOC-1, which includes organic materials, is disposed between the fourth dam pattern DMP4 and the fifth dam pattern DMP5, moisture and / or oxygen can be easily blocked from being introduced into the pixel PX through the module aperture MH via the first bonding region CA1 and the second bonding region CA2 (see reference). Figure 4 The path of ).

[0179] Reference Figure 9 The electronic device 1000-2 in the embodiment may include a display panel DP and an input sensor ISL. The display panel DP may include a substrate layer 110, a circuit element layer 120, a display element layer 130, and an encapsulation layer 140. The display panel DP may include a first dam pattern DMP1 to a fifth dam pattern DMP5 disposed in the hole region A1. The first dam pattern DMP1 to the fifth dam pattern DMP5 may be arranged sequentially in a direction from the pixel region A2 toward the module hole MH. On a plane, each of the first dam pattern DMP1 to the fifth dam pattern DMP5 may have a closed line shape surrounding the module hole HM.

[0180] The input sensor ISL may include a first sensing insulating layer 210, a first conductive pattern TML1, a second sensing insulating layer 220, a second conductive pattern TML2, a third sensing insulating layer 230, and a fourth sensing insulating layer 240.

[0181] The input sensor ISL in this embodiment may include an organic patterned layer YOC-2. The organic patterned layer YOC-2 may be stacked with the hole region A1 and may be disposed between the first sensing insulating layer 210 and the second sensing insulating layer 220. The organic patterned layer YOC-2 may compensate for the height differences generated during the manufacturing process of the first dam pattern DMP1 to the fifth dam pattern DMP5.

[0182] According to this embodiment, the organic patterned layer YOC-2 can be disposed from the groove defined between the first dam pattern DMP1 and the second dam pattern DMP2 to the fourth dam pattern DMP4. According to this embodiment, the boundary of the organic patterned layer YOC-2 within the hole region A1 can be defined by the fourth dam pattern DMP4.

[0183] The organic patterned layer YOC-2 may include a first pattern Y-1 disposed from a first dam pattern DMP1 to a second dam pattern DMP2, a second pattern Y-2 disposed between the second dam pattern DMP2 and a third dam pattern DMP3, and a third pattern Y-3 disposed between the third dam pattern DMP3 and a fourth dam pattern DMP4. The first pattern Y-1 to the third pattern Y-3 may be portions that are broken by the second dam pattern DMP2 to the fourth dam pattern DMP4 during the process of forming the organic patterned layer YOC-2 by applying organic materials.

[0184] The top surface of the second dam pattern DMP2 can be exposed between the first pattern Y-1 and the second pattern Y-2, the top surface of the third dam pattern DMP3 can be exposed between the second pattern Y-2 and the third pattern Y-3, and the top surface of the fourth dam pattern DMP4 can be exposed from the third pattern Y-3.

[0185] According to this embodiment, the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 can contact each other on the top surface of each of the second dam patterns DMP2 to the fourth dam patterns DMP4. Additionally, the first encapsulation inorganic layer 141 and the second encapsulation inorganic layer 143 can contact each other on the top surfaces of the second dam patterns DMP2 to the fourth dam patterns DMP4. Therefore, the first bonding region CA1 can be defined on the top surface of the second dam pattern DMP2, the second bonding region CA2 can be defined on the top surface of the third dam pattern DMP3, and the third bonding region CA3 can be defined on the top surface of the fourth dam pattern DMP4.

[0186] According to this embodiment, an organic patterned layer YOC-2, comprising organic material, can be disposed in each groove region defined between the second dam pattern DMP2 and the fourth dam pattern DMP4 to form the first bonding region to the third bonding region CA1, CA2, and CA3. Therefore, moisture and / or oxygen can be easily blocked from being introduced into the pixel PX through the module aperture MH (see reference). Figure 4 The path of ).

[0187] Reference Figure 10 and Figure 11 The electronic device 1000-3 in the embodiment may include a display panel DP and an input sensor ISL. The display panel DP may include a substrate layer 110, a circuit element layer 120, a display element layer 130, and an encapsulation layer 140. The display panel DP may include a first dam pattern DMP1 to a fifth dam pattern DMP5 disposed in the hole region A1. The first dam pattern DMP1 to the fifth dam pattern DMP5 may be arranged sequentially in a direction from the pixel region A2 toward the module hole MH. On a plane, each of the first dam pattern DMP1 to the fifth dam pattern DMP5 may have a closed line shape surrounding the module hole HM.

[0188] The input sensor ISL may include a first sensing insulating layer 210, a first conductive pattern TML1, a second sensing insulating layer 220, a second conductive pattern TML2, a third sensing insulating layer 230, and a fourth sensing insulating layer 240.

[0189] The input sensor ISL in this embodiment may include an organic patterned layer YOC-3. The organic patterned layer YOC-3 may be stacked with the hole region A1 and may be disposed between the first sensing insulating layer 210 and the second sensing insulating layer 220. The organic patterned layer YOC-3 may compensate for the height differences generated during the manufacturing process of the first dam pattern DMP1 to the fifth dam pattern DMP5.

[0190] According to this embodiment, the organic patterned layer YOC-3 can be disposed from the groove defined between the first dam pattern DMP1 and the second dam pattern DMP2 to the fifth dam pattern DMP5. According to this embodiment, the boundary of the organic patterned layer YOC-3 within the hole region A1 can be defined by the fifth dam pattern DMP5.

[0191] The organic pattern layer YOC-3 may include a first pattern Y-1 set from the first dam pattern DMP1 to the fourth dam pattern DMP4 and a second pattern Y-2 set between the fourth dam pattern DMP4 and the fifth dam pattern DMP5.

[0192] The top surface of the fourth dam pattern DMP4 can be exposed between the first pattern Y-1 and the second pattern Y-2, and the top surface of the fifth dam pattern DMP5 can be exposed from the second pattern Y-2.

[0193] like Figure 11As shown, the fourth dam pattern DMP4 in the embodiment may include a first additional pattern PDL-P1 disposed on the second insulating pattern 70-P and a second additional pattern SPC-P disposed on the first additional pattern PDL-P1. Each of the first additional pattern PDL-P1 and the second additional pattern SPC-P may include an organic material. The fourth dam pattern DMP4 may include the first additional pattern PDL-P1 and the second additional pattern SPC-P to increase the thickness within the aperture region A1. The first additional pattern PDL-P1 may be combined with... Figure 5 The pixel-defining layer (PDL) described herein is formed using the same process and may include the same material as the pixel-defining layer (PDL). The second additional pattern (SPC-P) may be... Figure 5 The spacer SPC described herein is formed by the same process and may include the same material as the spacer SPC.

[0194] The fifth dam pattern DMP5 may also include a third additional pattern PDL-P2 disposed on the second insulating pattern 70-P. The third additional pattern PDL-P2 may include an organic material. The fifth dam pattern DMP5 may include the third additional pattern PDL-P2 to increase the thickness within the aperture region A1. The third additional pattern PDL-P2 may be combined with... Figure 5 The pixel-defining layer (PDL) described herein is formed using the same process and may include the same material as the pixel-defining layer (PDL).

[0195] According to this embodiment, the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 can contact each other on the top surface of the fourth dam pattern DMP4. Additionally, the first encapsulation inorganic layer 141 and the second encapsulation inorganic layer 143 can contact each other on the top surface of the fourth dam pattern DMP4. Therefore, the first bonding region CA1 can be defined on the top surface of the fourth dam pattern DMP4.

[0196] Furthermore, the second encapsulation inorganic layer 143, the first sensing insulating layer 210, the second sensing insulating layer 220, and the third sensing insulating layer 230 can contact each other on the top surface of the fifth dam pattern DMP5. Additionally, the first encapsulation inorganic layer 141 and the second encapsulation inorganic layer 143 can contact each other on the top surface of the fifth dam pattern DMP5. Therefore, the second bonding region CA2 can be defined on the top surface of the fifth dam pattern DMP5.

[0197] According to this embodiment, even when the organic pattern layer YOC-3, which includes organic materials, is disposed between the fourth dam pattern DMP4 and the fifth dam pattern DMP5, moisture and / or oxygen can be easily blocked from being introduced into the pixel PX through the module aperture MH via the first bonding region CA1 and the second bonding region CA2 (see reference). Figure 4 The path of ).

[0198] According to embodiments of the inventive concept, since an insulating layer comprising inorganic material is stacked on a dam around the module aperture defined in the effective area, the path of oxygen and / or moisture through the module aperture into the light-emitting element can be easily blocked. Therefore, an electronic device with improved reliability can be provided.

[0199] It will be apparent to those skilled in the art that various modifications and variations can be made to the inventive concept. Therefore, this disclosure is intended to cover modifications and variations of the present invention, provided that they fall within the scope of the appended claims and their equivalents.

[0200] Therefore, the actual scope of protection of a utility model concept should be determined by the technical scope of the appended claims.

Claims

1. An electronic device, characterized by comprising: The electronic device includes: a display panel including: a base layer including an active area including a hole area and a pixel area surrounding the hole area; a light emitting element disposed in the pixel area; an encapsulation layer covering the light emitting element and including a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer; and a dam pattern disposed in the hole area; an input sensor disposed on the encapsulation layer and including: a first sensing insulating layer; a first conductive pattern; a second sensing insulating layer; a second conductive pattern; a third sensing insulating layer; and an organic pattern layer overlapping the hole area, disposed on the first sensing insulating layer, and covered by the second sensing insulating layer; a cap organic layer disposed on the input sensor; and a window disposed on the cap organic layer, wherein a module hole is defined, the module hole passing through the display panel, the input sensor, and the cap organic layer and overlapping the hole area, each of the dam patterns surrounds the module hole, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are in contact with each other on at least one top surface of the dam pattern. 2.The electronic device of claim 1, wherein, The dam pattern includes a first dam pattern, a second dam pattern, a third dam pattern, a fourth dam pattern, and a fifth dam pattern, which are spaced apart from each other in a direction from the pixel area toward the module hole, and each of the first dam pattern to the fifth dam pattern includes: a first insulating pattern; a first pattern disposed on the first insulating pattern; a second pattern contacting the first pattern; and a second insulating pattern covering the second pattern, and the second pattern protrudes between a side surface of the first insulating pattern and a side surface of the second insulating pattern and defines a tip portion. 3.The electronic device of claim 2, wherein, a boundary of the organic pattern layer is defined by the fourth dam pattern within the hole area, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are in contact with each other on the fourth dam pattern. 4.The electronic device of claim 2, wherein, The display panel includes: a first insulating layer disposed on the base layer; a first semiconductor pattern disposed on the first insulating layer; a second insulating layer covering the first semiconductor pattern and disposed on the first insulating layer; a first gate overlapping the first semiconductor pattern and disposed on the second insulating layer; a third insulating layer covering the first gate and disposed on the second insulating layer; a second semiconductor pattern disposed on the third insulating layer; a fourth insulating layer covering the second semiconductor pattern and disposed on the third insulating layer; a second gate overlapping the second semiconductor pattern and disposed on the fourth insulating layer; a fifth insulating layer covering the second gate and disposed on the fourth insulating layer; a first connection electrode disposed on the fifth insulating layer and connected to the first semiconductor pattern through a first contact hole passing through the second insulating layer to the fifth insulating layer; a sixth insulating layer covering the first connection electrode and disposed on the fifth insulating layer; A second connecting electrode is disposed on the sixth insulating layer and connected to the first connecting electrode through a second contact hole that passes through the sixth insulating layer; and A seventh insulating layer covers the second connecting electrode and is disposed on the sixth insulating layer. In this embodiment, one of the light-emitting elements is connected to the second connection electrode through a third contact hole, which passes through the seventh insulating layer. 5.The electronic device of claim 4, wherein, The matrix layer comprises a first organic layer, a first inorganic layer disposed on the first organic layer, a second organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the second organic layer, which are sequentially stacked. Each of the first organic layer and the second organic layer is composed of polyimide, and each of the first inorganic layer and the second inorganic layer is composed of inorganic material. 6.The electronic device of claim 5, wherein, The electronic device further includes a light-blocking pattern superimposed on the first semiconductor pattern and disposed within the second inorganic layer. 7.The electronic device of claim 4, wherein, Each of the first to fifth insulating layers is composed of inorganic materials, and Each of the sixth and seventh insulating layers is composed of organic materials. 8.The electronic device of claim 7, wherein, The first insulating pattern is composed of the same material as the sixth insulating layer, and the second insulating pattern is composed of the same material as the seventh insulating layer. The first pattern is composed of the same material as the first connecting electrode, and the second pattern is composed of the same material as the second connecting electrode. 9.The electronic device of claim 4, wherein, Each of the first to fourth dam patterns further includes a first dummy pattern superimposed on the first pattern and disposed on the second insulating layer, and a second dummy pattern superimposed on the first dummy pattern and disposed on the third insulating layer. 10.The electronic device of claim 5, wherein, The fifth dam pattern also includes a dummy pattern set within the second inorganic layer, and The first pattern of the fifth dam pattern is connected to the dummy pattern through a contact hole, which passes through the second inorganic layer, the first insulating layer to the fifth insulating layer and the first insulating pattern. 11.The electronic device of claim 2, wherein, The organic pattern layer is disposed in the region between the first dam pattern and the second dam pattern, the region between the second dam pattern and the third dam pattern, and the region between the third dam pattern and the fourth dam pattern. 12.The electronic device of claim 11, wherein, The second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are in contact with each other on the top surfaces of the second dam pattern, the third dam pattern, and the fourth dam pattern. 13.The electronic device of claim 2, wherein, The fourth dam pattern also includes: A first additional pattern is disposed on the second insulating pattern; and The second additional pattern is set on top of the first additional pattern. The fifth dam pattern also includes a third additional pattern disposed on the second insulating pattern, and Each of the first to the third additional patterns is composed of organic materials. 14.The electronic device of claim 13, wherein, A portion of the organic pattern layer is disposed between the fourth dam pattern and the fifth dam pattern, and The second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are in contact with each other on a top surface of the fourth bank pattern and a top surface of the fifth bank pattern. 15.The electronic device of claim 2, wherein, The first encapsulation inorganic layer covers the first bank pattern to the fifth bank pattern. 16.The electronic device of claim 2, wherein, At least two of the tip portions included in the first bank pattern to the fifth bank pattern, respectively, face each other. 17.The electronic device of claim 1, wherein, The first encapsulation inorganic layer and the second encapsulation inorganic layer are in contact with each other on the at least one top surface of the bank pattern, and the second encapsulation inorganic layer, the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer are in contact with each other on the at least one top surface. 18.The electronic device of claim 1, wherein, Each of the first sensing insulating layer, the second sensing insulating layer, and the third sensing insulating layer consists of an inorganic material. 19.The electronic device of claim 1, wherein, The electronic device further includes a fourth sensing insulating layer disposed between the cap organic layer and the third sensing insulating layer and consisting of an organic material. 20.The electronic device of claim 1, wherein, The electronic device further includes a camera module superposed with the module hole. The electronic device further includes a fourth sensing insulating layer disposed between the cap organic layer and the third sensing insulating layer and consisting of an organic material.

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