Power supply monitoring circuit, micro-processing chip and encoder

Abstract

The utility model provides a power supply monitoring circuit and an encoder, and the power supply monitoring circuit comprises a comparison circuit input end which is connected with a to-be-monitored power supply and a first reference power supply, and a comparison circuit output end which is connected with a first input end of a self-locking circuit; the comparison circuit is used for comparing the to-be-monitored power supply voltage with the first reference power supply and outputting a comparison result; the self-locking circuit outputs a state signal of the to-be-monitored power supply according to the comparison result output by the comparison circuit and received by the first input end, if the state signal represents that the to-be-monitored power supply is abnormal, the self-locking circuit enters a self-locking state, and the output end of the self-locking circuit continuously outputs an alarm signal. According to the embodiment of the invention, the condition of large power supply fluctuation can be locked in time, and repeated alarm is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power supply, in particular to a power supply monitoring circuit, a micro-processing chip and an encoder. BACKGROUND

[0002] Various precision instruments, especially encoders, need to work in stable environmental conditions, and therefore have high requirements for the stability of power supply.

[0003] The prior art filters the input power supply, but it is difficult to completely eliminate large power supply ripple. If the power supply is not monitored, the power supply ripple may cause the output precision of the precision instrument to decrease or even damage the instrument. CONTENT OF THE UTILITY MODEL

[0004] The utility model aims at overcoming the defects of the prior art, and provides a power supply monitoring circuit, a micro-processing chip and an encoder, which monitor the power supply and solve the problem of precision decrease caused by power supply ripple.

[0005] In a first aspect, the utility model discloses a power supply monitoring circuit, which comprises a comparison circuit and a self-locking circuit; the input ends of the comparison circuit are connected with a to-be-monitored power supply and a first reference power supply respectively; the output end of the comparison circuit is connected with the first input end of the self-locking circuit; the self-locking circuit comprises a comparator, a transistor and a resistor; the first input end of the comparator is connected with the output end of the comparison circuit; the second input end of the comparator is connected with a second reference power supply and serves as the second input end of the self-locking circuit; the output end of the comparator is connected with the control end of the transistor; the resistor and the transistor are connected in series between a power supply and the ground; the connecting point between the resistor and the transistor serves as the output end of the self-locking circuit; and the output end of the self-locking circuit is also connected to the first input end of the comparator; the comparison circuit is used for comparing the to-be-monitored power supply voltage with the first reference power supply and outputting a comparison result; the self-locking circuit outputs a state signal of the to-be-monitored power supply according to the comparison result output by the comparison circuit and received by the first input end; if the state signal represents that the to-be-monitored power supply is abnormal, the self-locking circuit enters a self-locking state, and the output end of the self-locking circuit continuously outputs an alarm signal.

[0006] In one of the embodiments, the comparison circuit comprises an overvoltage comparison circuit and an undervoltage comparison circuit; the self-locking circuit comprises a first self-locking circuit and a second self-locking circuit; the input end of the first self-locking circuit is connected with the output end of the overvoltage comparison circuit; the input end of the second self-locking circuit is connected with the output end of the undervoltage comparison circuit; the input end of the overvoltage comparison circuit is connected with a to-be-monitored power supply and a third reference power supply respectively, and the output end outputs the comparison result of the to-be-monitored power supply voltage and the third reference power supply; the first self-locking circuit outputs a first state signal of the to-be-monitored power supply according to the comparison result output by the overvoltage comparison circuit; if the first state signal represents overvoltage of the to-be-monitored power supply, the first self-locking circuit enters a self-locking state, and the output end of the first self-locking circuit continuously outputs an alarm signal.

[0007] The input end of the undervoltage comparison circuit is connected with the to-be-monitored power supply and a fourth reference power supply respectively, and the output end outputs the comparison result of the to-be-monitored power supply voltage and the fourth reference power supply; the second self-locking circuit outputs a second state signal of the to-be-monitored power supply according to the comparison result output by the undervoltage comparison circuit; if the second state signal represents undervoltage of the to-be-monitored power supply, the second self-locking circuit enters a self-locking state, and the output end of the second self-locking circuit continuously outputs an alarm signal.

[0008] In the embodiment, overvoltage and undervoltage of the power supply can be monitored simultaneously, so as to prevent abnormal monitoring of the power supply and improve the accuracy of monitoring of the power supply.

[0009] In one of the embodiments, the overvoltage comparison circuit comprises a first comparator, a first input terminal of the first comparator being connected to the power supply to be monitored, a second input terminal being connected to a third reference power supply, and an output terminal serving as an output terminal of the overvoltage comparison circuit; the undervoltage comparison circuit comprises a second comparator, a first input terminal of the second comparator being connected to the power supply to be monitored, a second input terminal being connected to a fourth reference power supply, and an output terminal serving as an output terminal of the undervoltage comparison circuit; the first self-locking circuit comprises a third comparator, a first transistor, and a first resistor, a first input terminal of the third comparator being connected to the output terminal of the overvoltage comparison circuit, a second input terminal being connected to a fifth reference power supply, and an output terminal being connected to a control terminal of the first transistor, the first resistor being connected in series with the first transistor between a power supply and ground, a connection point between the first resistor and the first transistor serving as an output terminal of the first self-locking circuit, and the output terminal of the first self-locking circuit being further connected to the first input terminal of the third comparator; the second self-locking circuit comprises a fourth comparator, a second transistor, and a second resistor, a first input terminal of the fourth comparator being connected to the output terminal of the undervoltage comparison circuit, a second input terminal being connected to a sixth reference power supply, and an output terminal being connected to a control terminal of the second transistor, the second resistor being connected in series with the second transistor between the power supply and the ground, a connection point between the second resistor and the second transistor serving as an output terminal of the second self-locking circuit, and the output terminal of the second self-locking circuit being further connected to the first input terminal of the fourth comparator.

[0010] In the embodiment, the first comparator and the second comparator are respectively used for comparing the power supply voltage to be monitored with the third reference power supply voltage and comparing the power supply voltage to be monitored with the fourth reference power supply voltage; the third comparator and the fourth comparator are respectively used for controlling the first transistor and the second transistor according to the comparison results output by the overvoltage comparison circuit and the undervoltage comparison circuit.

[0011] The power supply monitoring circuit further comprises a judging circuit; the comparison circuit comprises an overvoltage comparison circuit and an undervoltage comparison circuit; input ends of the overvoltage comparison circuit are connected with the power supply to be monitored and a third reference power supply respectively, and an output end outputs a comparison result of the power supply to be monitored and the third reference power supply; input ends of the undervoltage comparison circuit are connected with the power supply to be monitored and a fourth reference power supply respectively, and an output end outputs a comparison result of the power supply to be monitored and the fourth reference power supply; the judging circuit comprises an OR gate, a third transistor and a third resistor, a first input end of the OR gate is connected with an output end of the overvoltage comparison circuit, used for receiving the comparison result of the power supply to be monitored and the third reference power supply, a second input end of the OR gate is connected with an output end of the undervoltage comparison circuit, used for receiving the comparison result of the power supply to be monitored and the fourth reference power supply, an output end is connected with a control end of the third transistor, the third resistor and the third transistor are connected in series between a power supply and a ground, and a connection point between the third resistor and the third transistor serves as an output end of the judging circuit; the output end of the judging circuit is connected with a first input end of the self-locking circuit; the judging circuit is used for outputting a judging result representing an abnormality of the power supply to be monitored to the first input end of the self-locking circuit according to the comparison result representing overvoltage of the power supply to be monitored output by the overvoltage comparison circuit and / or according to the comparison result representing undervoltage of the power supply to be monitored output by the undervoltage comparison circuit.

[0012] In the embodiment, the judging circuit is connected between the comparison circuit and the self-locking circuit, used for avoiding the comparison result output by the comparison circuit from affecting the self-locking state of the self-locking circuit; the judging circuit further performs logical operation on the comparison results of the overvoltage comparison circuit and the undervoltage comparison circuit through the OR gate, so as to realize overvoltage and undervoltage monitoring of the power supply to be monitored through only one self-locking circuit.

[0013] In one of the embodiments, the power supply monitoring circuit further comprises a first judging circuit and a second judging circuit; the first judging circuit comprises a fourth transistor and a fourth resistor, a control end of the fourth transistor serves as an input end of the first judging circuit and is connected with an output end of the overvoltage comparison circuit, the fourth resistor and the fourth transistor are connected in series between a power supply and a ground, and a connection point between the fourth transistor and the fourth resistor serves as an output end of the first judging circuit and is connected with an input end of the first self-locking circuit; the second judging circuit comprises a fifth transistor and a fifth resistor, a control end of the fifth transistor serves as an input end of the second judging circuit and is connected with an output end of the undervoltage comparison circuit, the fifth resistor and the fifth transistor are connected in series between the power supply and the ground, and a connection point between the fifth transistor and the fifth resistor serves as an output end of the second judging circuit and is connected with an input end of the second self-locking circuit.

[0014] In one of the embodiments, the power supply monitoring circuit further comprises a first sampling circuit and a second sampling circuit; the input end of the first sampling circuit is connected with the power supply to be monitored, the output end is connected with the first input end of the overvoltage comparison circuit, and the first sampling voltage is provided; the input end of the second sampling circuit is connected with the power supply to be monitored, and the output end is connected with the second input end of the undervoltage comparison circuit, and the second sampling voltage is provided.

[0015] In the embodiment, the first sampling circuit and the second sampling circuit can provide the sampling voltage with a proper range and related to the voltage of the power supply to be monitored to the overvoltage comparison circuit and the undervoltage comparison circuit; the first sampling voltage provided by the first sampling circuit is different from the second sampling voltage provided by the second sampling circuit, and the third reference power supply voltage and the fourth reference power supply voltage received by the overvoltage comparison circuit and the undervoltage comparison circuit can be the same, so that the power supply is reduced and the circuit structure is simplified.

[0016] In one of the embodiments, the self-locking circuit further comprises an unlocking port; the unlocking port is connected with the output end of the comparator and the control end of the transistor at the same time; the unlocking port of the self-locking circuit is used for receiving an unlocking signal; the unlocking signal is used for releasing the self-locking state of the self-locking circuit when the self-locking circuit enters the self-locking state, the alarm signal is continuously output from the output end of the self-locking circuit, and the self-locking circuit outputs the normal signal.

[0017] In the embodiment, the user can release the self-locking state of the self-locking circuit through the unlocking port of the self-locking circuit, so that the user can release the self-locking state and make the self-locking circuit output the normal signal after replacing the power supply or determining that the power supply is restored to normal.

[0018] In one of the embodiments, the power supply monitoring circuit further comprises a processing circuit; the input end of the processing circuit is connected with the output end of the self-locking circuit, and is used for receiving the state signal output from the self-locking circuit; and the output end of the processing circuit is connected with the unlocking port of the self-locking circuit, and is used for providing the unlocking signal.

[0019] In the embodiment, the user can conveniently obtain the state signal representing the state of the power supply to be monitored through the microprocessor, and can conveniently release the self-locking state of the self-locking circuit and the alarm signal.

[0020] In a second aspect, the utility model discloses a kind of microprocessing chips, including above-mentioned power supply monitoring circuit and pin interface, and the output end of the self-locking circuit of power supply monitoring circuit is connected to the pin interface.

[0021] In a third aspect, the utility model discloses a kind of encoders, including any one of the above-mentioned power supply monitoring circuit.

[0022] The embodiment of the present application discloses a power supply monitoring circuit and an encoder, the power supply monitoring circuit continuously outputs an alarm signal to remind to replace the power supply or check the problem according to the power supply sampling result, if the ripple amplitude exceeds a certain range, and can avoid the problem of reduced accuracy of the encoder due to unstable power supply. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings herein are incorporated into the description and form a part of the description, show the embodiments consistent with the present application, and together with the description, serve to explain the principles of the present application, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Figure 1 A possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0025] Figure 2 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0026] Figure 3 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0027] Figure 4 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0028] Figure 5 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0029] Figure 6 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0030] Figure 7 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0031] Figure 8 Another possible circuit diagram of the power supply monitoring circuit provided by the embodiment of the present application;

[0032] Figure 9 A possible schematic diagram of the microprocessor provided by the embodiment of the present application;

[0033] Figure 10 A possible schematic diagram of the encoder provided by the embodiment of the present application. DETAILED DESCRIPTION

[0034] The illustrative embodiments will be described with reference to the accompanying drawings, of which like elements are referred to by like reference numerals. The following detailed description is presented in terms of a number of examples, which are not intended to limit the scope of the application. Rather, the following detailed description is intended to describe a number of aspects of the application, which are described in terms of a number of examples.

[0035] It should be noted that the described embodiments are merely a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0036] In the description of the present application, the terms "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified.

[0037] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0038] It should be understood that the term "and / or" used herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0039] As Figure 1The power supply monitoring circuit comprises a comparison circuit 1 and a self-locking circuit 2, the comparison circuit 1 is connected with the self-locking circuit 2, the input ends of the comparison circuit 1 are connected with a power to be monitored and a first reference power respectively, the self-locking circuit 2 comprises a comparator U0, a transistor Q0 and a resistor R0, the first input end of the comparator U0 is connected with the comparison circuit 1 as the input end of the self-locking circuit 2, the second input end of the comparator U0 is connected with a second reference power, and the output end of the comparator U0 is connected with the control end of the transistor Q0, the transistor Q0 and the resistor R0 are connected in series between a power supply and the ground, the first end of the resistor R0 is connected with the power supply, the second end of the resistor R0 is connected with the first end of the transistor Q0, the second end of the transistor Q0 is connected with the ground, the connecting point between the transistor Q0 and the resistor R0 is the output end of the self-locking circuit 2, and the output end of the self-locking circuit 2 is further connected to the first input end of the comparator U0.

[0040] In the embodiment, the first input end of the comparator U0 is an inverting input end, and the second input end is a non-inverting input end, if the state of the power to be monitored is normal, the first input end of the comparator U0 receives a high-level signal, thus the comparator U0 outputs a low-level signal, if the state of the power to be monitored is abnormal, the first input end of the comparator U0 receives a low-level signal, thus the comparator U0 outputs a high-level signal, the transistor Q0 is an NPN transistor, the control end of the transistor Q0 is a base, the first end is a collector, and the second end is an emitter, in the case that the state of the power to be monitored is normal, the transistor Q0 is cut off according to the low-level signal output by the comparator U0, the output end of the self-locking circuit 2 outputs a high-level signal, and the inverting input end of the comparator U0 connected with the output end of the self-locking circuit 2 receives the high-level signal, in the case that the state of the power to be monitored is abnormal, the transistor Q0 is turned on according to the high-level signal output by the comparator U0, the output end of the self-locking circuit 2 outputs a low-level signal, and the inverting input end of the comparator U0 connected with the output end of the self-locking circuit 2 receives the low-level signal, the self-locking circuit 2 enters a self-locking state, in the embodiment, the high-level signal output by the output end of the self-locking circuit 2 is a normal state signal, and the low-level signal is an alarm state signal.

[0041] The self-locking circuit 2 further comprises an unlocking port connected with the control end of the transistor Q0 and the output end of the comparator U0, when the state of the power to be monitored is restored to normal or the power is replaced, the unlocking port inputs an unlocking signal, which is a low-level signal in the embodiment.

[0042] According to the circuit connection in the self-locking circuit 2, the power supply monitoring circuit can continuously output the alarm signal representing the abnormality of the to-be-monitored power supply voltage when the abnormality of the to-be-monitored power supply voltage occurs, until the normal signal representing the normality of the to-be-monitored power supply voltage is outputted after the unlocking port inputs the unlocking signal and the state of the to-be-monitored power supply returns to normal. The power supply monitoring circuit continuously outputs the alarm signal representing the abnormality of the to-be-monitored power supply voltage after the abnormality of the to-be-monitored power supply voltage occurs, which can timely find the abnormal state of the to-be-monitored power supply voltage and can also avoid frequent error reporting due to power supply fluctuation. In the embodiment, the connection relationship of the comparator U0, the transistor Q0 and the resistor R0 in the self-locking circuit 2 makes the transistor Q0 abnormal short circuit also make the self-locking circuit 2 enter the self-locking state and continuously output the alarm signal, which facilitates the user to troubleshoot the fault, and the unlocking port is located at the output port of the comparator U0, avoiding the influence of the unlocking signal of the unlocking port on the comparison result representing the state of the to-be-monitored power supply outputted by the comparison circuit 1.

[0043] As shown in another power supply monitoring circuit, Figure 2 the comparison circuit 1 includes an overvoltage comparison circuit 101 and an undervoltage comparison circuit 102, and the self-locking circuit 2 includes a first self-locking circuit 201 and a second self-locking circuit 202. The overvoltage comparison circuit 101 includes a first comparator U1, the first input end of the first comparator U1 is connected with the to-be-monitored power supply, the second input end is connected with the third reference power supply, and the output end is used as the output end of the overvoltage comparison circuit 101. The undervoltage comparison circuit 102 includes a second comparator U2, the first input end of the second comparator U2 is connected with the to-be-monitored power supply, the second input end is connected with the fourth reference power supply, and the output end is used as the output end of the undervoltage comparison circuit 102. The first self-locking circuit 201 includes a third comparator U3, a first transistor Q1 and a first resistor R1, the first input end of the third comparator U3 is connected with the output end of the overvoltage comparison circuit 101, the second input end is connected with the fifth reference power supply, the output end is connected with the control end of the first transistor Q1, the first resistor R1 and the first transistor Q1 are connected in series between the power supply and the ground, the connection point between the first resistor R1 and the first transistor Q1 is used as the output end of the first self-locking circuit 201, and the output end of the first self-locking circuit 201 is also connected to the first input end of the third comparator U3. The second self-locking circuit 202 includes a fourth comparator U4, a second transistor Q2 and a second resistor R2, the first input end of the fourth comparator U4 is connected with the output end of the undervoltage comparison circuit 102, the second input end is connected with the sixth reference power supply, the output end is connected with the control end of the second transistor Q2, the second resistor R2 and the second transistor Q2 are connected in series between the power supply and the ground, the connection point between the second resistor R2 and the second transistor Q2 is used as the output end of the second self-locking circuit 202, and the output end of the second self-locking circuit 202 is also connected to the first input end of the fourth comparator U4.

[0044] In the embodiment, the input end of the first self-locking circuit 201 is connected with the output end of the overvoltage comparison circuit 101, and the input end of the second self-locking circuit 202 is connected with the output end of the undervoltage comparison circuit 102; the overvoltage comparison circuit 101 is used for receiving the to-be-monitored power voltage and the third reference power voltage for comparison and outputting a comparison result, and the first self-locking circuit 201 outputs the first state signal of the to-be-monitored power according to the comparison result output by the overvoltage comparison circuit 101; the undervoltage comparison circuit 102 is used for receiving the to-be-monitored power voltage and the fourth reference power voltage for comparison and outputting a comparison result, and the second self-locking circuit 202 outputs the second state signal of the to-be-monitored power according to the comparison result output by the undervoltage comparison circuit 102.

[0045] In the embodiment, when the overvoltage abnormality occurs in the to-be-monitored power supply, the overvoltage comparison circuit 101 outputs a low-level signal to represent the comparison result that the voltage of the to-be-monitored power supply is higher than the third reference power supply, the first input terminal of the third comparator U3 is the inverting input terminal and receives the low-level signal output by the overvoltage comparison circuit 101, the second input terminal is the non-inverting input terminal and receives the voltage of the fifth reference power supply, and the output terminal outputs a high-level signal. The first transistor Q1 is an NPN transistor, the control terminal is the base and receives the high-level signal output by the third comparator U3, the first transistor Q1 is turned on, the first terminal of the first resistor R1 is connected to the power supply, the second terminal is connected to the collector of the first transistor Q1, the emitter of the first transistor Q1 is connected to the ground, the connection point of the first resistor R1 and the first transistor Q1 serves as the output terminal of the first self-locking circuit 201 and outputs a first state signal representing the overvoltage of the to-be-monitored power supply as a low-level signal, and the output terminal of the first self-locking circuit 201 is also connected to the first input terminal of the third comparator U3, the first input terminal of the third comparator U3 continuously receives the low-level signal, and the first self-locking circuit 201 enters the self-locking state. When the undervoltage abnormality occurs in the to-be-monitored power supply, the undervoltage comparison circuit 102 outputs a low-level signal to represent the comparison result that the voltage of the to-be-monitored power supply is lower than the fourth reference power supply, the first input terminal of the fourth comparator U4 is the inverting input terminal and receives the low-level signal output by the undervoltage comparison circuit 102, the second input terminal is the non-inverting input terminal and receives the voltage of the sixth reference power supply, and the output terminal outputs a high-level signal. The second transistor Q2 is an NPN transistor, the control terminal is the base and receives the high-level signal output by the fourth comparator, the second transistor Q2 is turned on, the first terminal of the second resistor R2 is connected to the power supply, the second terminal is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is connected to the ground, the connection point of the second resistor R2 and the second transistor Q2 serves as the output terminal of the second self-locking circuit 202 and outputs a second state signal representing the undervoltage of the to-be-monitored power supply as a low-level signal, and the output terminal of the second self-locking circuit 202 is also connected to the first input terminal of the fourth comparator U4, the first input terminal of the fourth comparator U4 continuously receives the low-level signal, and the second self-locking circuit 202 enters the self-locking state.

[0046] In the application, the power supply can be the to-be-monitored power supply to reduce the power supply demand and simplify the circuit, or can be an independent other power supply to avoid the influence of possible changes of the to-be-monitored power supply on the function of the power supply monitoring circuit.

[0047] As Figure 3As shown, the comparison circuit 1 comprises an overvoltage comparison circuit 101 and an undervoltage comparison circuit 102, and the power supply monitoring circuit further comprises a judgment circuit 3, which comprises an OR gate, a third transistor Q3 and a third resistor R3. The first input end of the OR gate is connected to the output end of the overvoltage comparison circuit 101 for receiving the comparison result of the to-be-monitored power supply voltage and the third reference power supply voltage, the second input end of the OR gate is connected to the output end of the undervoltage comparison circuit 102 for receiving the comparison result of the to-be-monitored power supply voltage and the fourth reference power supply voltage, and the output end of the OR gate is connected to the control end of the third transistor Q3. The third resistor R3 is connected in series with the third transistor Q3 between the power supply and the ground, and the connection point between the third resistor R3 and the third transistor Q3 serves as the output end of the judgment circuit 3. The output end of the judgment circuit 3 is connected to the first input end of the self-locking circuit 2.

[0048] In this embodiment, when the to-be-monitored power supply has an overvoltage abnormality, the overvoltage comparison circuit 101 outputs a high-level signal to indicate the comparison result that the to-be-monitored power supply voltage exceeds the third reference power supply voltage. When the to-be-monitored power supply has an undervoltage abnormality, the undervoltage comparison circuit 102 outputs a high-level signal to indicate the comparison result that the to-be-monitored power supply voltage is lower than the fourth reference power supply voltage. The OR gate receives the comparison results of the overvoltage comparison circuit 101 and the undervoltage comparison circuit 102 respectively and performs logical operation. When the to-be-monitored power supply has an overvoltage abnormality or an undervoltage abnormality, the OR gate outputs a high-level signal. When the to-be-monitored power supply voltage is normal, the OR gate outputs a low-level signal. The third transistor Q3 is an NPN transistor. The first end of the third resistor R3 is connected to the power supply, the second end of the third resistor R3 is connected to the collector of the third transistor Q3, the emitter of the third transistor Q3 is connected to the ground, the base of the third transistor Q3 is connected to the output end of the OR gate, and the connection point between the third resistor R3 and the third transistor Q3 serves as the output end of the judgment circuit 3 for outputting a judgment signal. When the to-be-monitored power supply has an overvoltage abnormality or an undervoltage abnormality, the third transistor Q3 receives a high-level signal and is turned on. The judgment circuit 3 outputs a low-level judgment result representing the abnormality of the to-be-monitored power supply voltage to the self-locking circuit 2.

[0049] In this embodiment, when the to-be-monitored power supply has an overvoltage abnormality or an undervoltage abnormality, the self-locking circuit 2 enters a self-locking state, the output end outputs a low-level state signal representing the abnormality of the to-be-monitored power supply voltage, and provides a low-level signal to the first input end of the comparator U0. When the to-be-monitored power supply returns to normal, the third transistor Q3 is closed according to the low-level signal received by the base, and the transistor Q0 still remains in the turned-on state, so that the first input end of the comparator U0 still receives a low-level signal.

[0050] Obviously, the embodiment can monitor overvoltage and undervoltage of the power supply to be monitored at the same time, and can alarm and self-lock overvoltage and undervoltage abnormalities, so as to realize overvoltage and undervoltage monitoring of the power supply to be monitored by only one self-locking circuit 2; the judgment circuit 3 is connected between the comparison circuit 1 and the self-locking circuit 2, and is used for avoiding the influence of the comparison result output by the comparison circuit 1 on the self-locking state of the self-locking circuit 2; it can be easily thought that other combinations of logic devices and high and low level representations of the power supply to be monitored will not exceed the protection scope of the utility model.

[0051] As shown in Figure 4 the difference between Figure 3 lies in that the judgment circuit 3 comprises a first judgment circuit 301 and a second judgment circuit 302, and the self-locking circuit 2 comprises a first self-locking circuit 201 and a second self-locking circuit 202; the first judgment circuit 301 is connected between the overvoltage comparison circuit 101 and the first self-locking circuit 201, the first judgment circuit 301 comprises a fourth transistor Q4 and a fourth resistor R4, the control end of the fourth transistor Q4 is connected with the output end of the overvoltage comparison circuit 101 as the input end of the first judgment circuit 301, the fourth resistor R4 and the fourth transistor Q4 are connected in series between the power supply and the ground, the connection point between the fourth resistor R4 and the fourth transistor Q4 is connected with the output end of the first judgment circuit 301, and the output end of the first judgment circuit 301 is connected with the first input end of the first self-locking circuit 201; the second judgment circuit 302 is connected between the undervoltage comparison circuit 102 and the second self-locking circuit 202, the second judgment circuit 302 comprises a fifth transistor Q5 and a fifth resistor R5, the control end of the fifth transistor Q5 is connected with the output end of the undervoltage comparison circuit 102 as the input end of the second judgment circuit 302, the fifth resistor R5 and the fifth transistor Q5 are connected in series between the power supply and the ground, the connection point between the fourth resistor R5 and the fifth transistor Q5 is connected with the output end of the second judgment circuit 302, and the output end of the second judgment circuit 302 is connected with the first input end of the second self-locking circuit 202.

[0052] In the embodiment, the fourth transistor Q4 is an NPN transistor, the control end is a base, the first end of the fourth resistor R4 is connected with the power supply, the second end is connected with the collector of the fourth transistor Q4, and the emitter of the fourth transistor Q4 is connected with the ground; when the overvoltage abnormality of the to-be-monitored power supply occurs, the fourth transistor Q4 is turned on according to the high-level comparison result output by the overvoltage comparison circuit 101, which represents the overvoltage abnormality of the to-be-monitored power supply, and provides the low-level first judgment result to the first self-locking circuit 201; the fifth transistor Q5 is an NPN transistor, the control end is a base, the first end of the fifth resistor R5 is connected with the power supply, the second end is connected with the collector of the fourth transistor Q4, and the emitter of the fifth transistor Q5 is connected with the ground; when the undervoltage abnormality of the to-be-monitored power supply occurs, the fifth transistor Q5 is turned on according to the high-level comparison result output by the undervoltage comparison circuit 102, which represents the undervoltage abnormality of the to-be-monitored power supply, and provides the low-level second judgment result to the second self-locking circuit 202.

[0053] As shown in Figure 5 , the power supply monitoring circuit further comprises a sampling circuit 4 connected between the to-be-monitored power supply and the comparison circuit 1, used for sampling the voltage of the to-be-monitored power supply; the sampling circuit 4 specifically comprises a sixth resistor R6 and a seventh resistor R7, as shown in Figure 6 , the first end of the sixth resistor R6 is connected with the to-be-monitored power supply, the second end is connected with the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected with the ground, and the connection point between the sixth resistor R6 and the seventh resistor R7 is connected with the first input end of the overvoltage comparison circuit 101 and the first input end of the undervoltage comparison circuit 102 as the output end of the sampling circuit 4.

[0054] In the embodiment, the overvoltage comparison circuit 101 and the undervoltage comparison circuit 102 use the same sampling voltage of the to-be-monitored power supply to compare with different third reference power supply voltage and fourth reference power supply voltage respectively.

[0055] In the embodiment, the sampling circuit 4 obtains the sampling voltage in the appropriate range by sampling the voltage of the to-be-monitored power supply; the overvoltage comparison circuit 101 and the undervoltage comparison circuit 102 receive different third reference power supply voltage and fourth reference power supply voltage to compare with the same sampling voltage to determine whether the to-be-monitored power supply is in the overvoltage or undervoltage abnormal state, so that only one sampling circuit 4 can be provided to provide the sampling voltage for the overvoltage comparison circuit 101 and the undervoltage comparison circuit 102, thereby simplifying the circuit structure.

[0056] As shown in Figure 7 , the sampling circuit 4 comprises a first sampling circuit 401 and a second sampling circuit 402, and the power supply monitoring circuit further comprises a reference power supply providing circuit 5.

[0057] In the embodiment, the first sampling circuit 401 comprises an eighth resistor R8 and a ninth resistor R9, the first end of the eighth resistor R8 is connected with the power supply to be monitored, the second end is connected with the first end of the ninth resistor R9, the second end of the ninth resistor R9 is connected with the ground, the connecting point between the eighth resistor R8 and the ninth resistor R9 is the output end of the first sampling circuit 401, and the output end of the first sampling circuit 401 is connected with the first input end of the overvoltage comparison circuit 101, for providing the first sampling voltage; the second sampling circuit 402 comprises a tenth resistor R10 and an eleventh resistor R11, the first end of the tenth resistor R10 is connected with the power supply to be monitored, the second end is connected with the first end of the eleventh resistor R11, the second end of the eleventh resistor R11 is connected with the ground, the connecting point between the tenth resistor R10 and the eleventh resistor R11 is the output end of the second sampling circuit 402, and the output end of the second sampling circuit 402 is connected with the first input end of the undervoltage comparison circuit 102, for providing the second sampling voltage; the reference power supply providing circuit 5 comprises a twelfth resistor R12 and a voltage stabilizing diode D0, the first end of the twelfth resistor R12 is connected with the power supply, the second end is connected with the negative electrode of the voltage stabilizing diode D0, the positive electrode of the voltage stabilizing diode D0 is connected with the ground, the connecting point between the twelfth resistor R12 and the voltage stabilizing diode D0 is the output end of the reference power supply providing circuit 5, and the output end of the reference power supply providing circuit 5 is connected with the second input end of the first comparator U1, the second input end of the second comparator U2, the second input end of the third comparator U3 and the second input end of the fourth comparator U4 respectively, that is, the third reference power supply, the fourth reference power supply, the fifth reference power supply and the sixth reference power supply are the same, and the overvoltage comparison circuit 101 and the undervoltage comparison circuit 102 compare the different first sampling voltage and the second sampling voltage according to the same third reference power supply and the fourth reference power supply respectively.

[0058] In the embodiment, the reference power supply voltage required by the power supply monitoring circuit is provided by a reference power supply providing circuit 5, so that the number of power supplies is reduced and the circuit structure is simplified.

[0059] As shown in Figure 8 the power supply monitoring circuit further comprises a processing circuit, the input end of the processing circuit is connected with the output end of the self-locking circuit 2, for receiving the state signal output by the self-locking circuit 2; and the output end of the processing circuit is connected with the unlocking port of the self-locking circuit 2, for providing an unlocking signal.

[0060] In the embodiment, the processing circuit receives the state signal output by the self-locking circuit 2, and provides an unlocking signal to the unlocking port of the self-locking circuit 2 after the abnormality of the power supply to be monitored is eliminated or the power supply to be monitored is replaced, so that the self-locking state and the alarm signal of the self-locking circuit 2 are released. The user can conveniently obtain the state signal representing the state of the power supply to be monitored through the processing circuit, and can conveniently release the self-locking state and the alarm signal of the self-locking circuit 2.

[0061] As Figure 9 shown, the application provides a micro-processing chip, comprising a power monitoring circuit and at least one pin interface, the output end of the self-locking circuit 2 of the power monitoring circuit is connected to the first pin interface.

[0062] In the embodiment, the unlocking port of the self-locking circuit can also be connected to the second pin interface.

[0063] In the embodiment, the power monitoring circuit is integrated in the micro-processing chip, the user can conveniently obtain the state signal representing the state of the power to be monitored through the first pin interface of the micro-processing chip, and can also input the unlocking signal through the second pin interface of the micro-processing chip to conveniently release the self-locking state of the self-locking circuit 2 and the alarm signal.

[0064] The micro-processing chip can be MCU, DSP, MPU, micro CPU, etc. which can process digital signals, analog signals, or micro central control chips, system-on-chip chips, etc. which can perform signal control functions, instruction processing and operation functions, etc. and there is no limitation.

[0065] As Figure 10 shown, the application provides an encoder comprising the power monitoring circuit in any of the above embodiments.

[0066] In the embodiments of the application, "at least one" means one or more, and "multiple" means two or more. The association relationship of "and / or" describing the associated objects means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. Wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" and similar expressions mean any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c can be single or multiple.

[0067] Those of ordinary skill in the art can realize that the units and algorithm steps described in the embodiments disclosed herein can be realized by electronic hardware, computer software and a combination of electronic hardware and computer software. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0068] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the system, device and unit described above can refer to the corresponding processes in the foregoing method embodiments, and will not be described here.

[0069] In several embodiments provided in the present application, any function, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0070] The above description is merely specific embodiments of the present application, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. The protection scope of the present application should be subject to the protection scope of the claims.

[0071] Other embodiments of the present application will be apparent to those skilled in the art upon consideration of the specification and practice of the present application. The present application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice in the art to which the application pertains. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the application are indicated by the following claims.

[0072] It should be understood that the present application is not limited to the precise construction that has been described and illustrated herein and that various modifications and changes can be made therein without departing from the scope thereof. The scope of the application is indicated by the appended claims.

Claims

1. A power monitoring circuit, characterized in that, include: Comparator circuits and self-locking circuits; The input terminals of the comparator circuit are connected to the power supply to be monitored and the first reference power supply, respectively, and the output terminal of the comparator circuit is connected to the first input terminal of the self-locking circuit. The self-locking circuit includes a comparator, a transistor, and a resistor. The first input terminal of the comparator is connected to the output terminal of the comparator circuit. The second input terminal of the comparator serves as the second input terminal of the self-locking circuit and is connected to a second reference power supply. The output terminal of the comparator is connected to the control terminal of the transistor. The resistor and the transistor are connected in series between the power supply and ground. The connection point between the resistor and the transistor serves as the output terminal of the self-locking circuit, and the output terminal of the self-locking circuit is also connected to the first input terminal of the comparator. The comparison circuit is used to compare the voltage of the power supply to be monitored with the first reference power supply and output the comparison result; The self-locking circuit outputs a status signal of the power supply to be monitored based on the comparison result received from the comparison circuit at the first input terminal. If the status signal indicates that the power supply to be monitored is abnormal, the self-locking circuit enters a self-locking state, and the output terminal of the self-locking circuit continuously outputs an alarm signal.

2. The power monitoring circuit according to claim 1, characterized in that, The comparison circuit includes an overvoltage comparison circuit and an undervoltage comparison circuit; the self-locking circuit includes a first self-locking circuit and a second self-locking circuit. The input terminal of the first self-locking circuit is connected to the output terminal of the overpressure comparator circuit; The input terminal of the second self-locking circuit is connected to the output terminal of the undervoltage comparator circuit; The input terminal of the overpressure comparison circuit is connected to the power supply to be monitored and the third reference power supply respectively, and the output terminal outputs the comparison result between the power supply to be monitored and the third reference power supply. The first self-locking circuit outputs the first status signal of the power supply to be monitored based on the comparison result output by the overpressure comparison circuit. If the first status signal indicates that the power supply to be monitored is overpressured, the first self-locking circuit enters the self-locking state, and the output terminal of the first self-locking circuit continuously outputs an alarm signal. The input terminal of the undervoltage comparison circuit is connected to the power supply to be monitored and the fourth reference power supply respectively, and the output terminal outputs the comparison result of the power supply to be monitored and the fourth reference power supply. The second self-locking circuit outputs the second status signal of the power supply to be monitored based on the comparison result output by the undervoltage comparison circuit. If the second status signal indicates that the power supply to be monitored is undervoltage, the second self-locking circuit enters the self-locking state, and the output terminal of the second self-locking circuit continuously outputs an alarm signal.

3. The power monitoring circuit according to claim 2, characterized in that, The overpressure comparison circuit includes a first comparator, the first input terminal of the first comparator is connected to the power supply to be monitored, the second input terminal is connected to the third reference power supply, and the output terminal is used as the output terminal of the overpressure comparison circuit. The undervoltage comparison circuit includes a second comparator. The first input terminal of the second comparator is connected to the power supply to be monitored, the second input terminal is connected to the fourth reference power supply, and the output terminal serves as the output terminal of the undervoltage comparison circuit. The first self-locking circuit includes a third comparator, a first transistor, and a first resistor. The first input terminal of the third comparator is connected to the output terminal of the overvoltage comparator circuit, the second input terminal is connected to the fifth reference power supply, and the output terminal is connected to the control terminal of the first transistor. The first resistor and the first transistor are connected in series between the power supply and ground. The connection point between the first resistor and the first transistor serves as the output terminal of the first self-locking circuit, and the output terminal of the first self-locking circuit is also connected to the first input terminal of the third comparator. The second self-locking circuit includes a fourth comparator, a second transistor, and a second resistor. The first input terminal of the fourth comparator is connected to the output terminal of the undervoltage comparator circuit, the second input terminal is connected to the sixth reference power supply, and the output terminal is connected to the control terminal of the second transistor. The second resistor and the second transistor are connected in series between the power supply and ground. The connection point between the second resistor and the second transistor serves as the output terminal of the second self-locking circuit, and the output terminal of the second self-locking circuit is also connected to the first input terminal of the fourth comparator.

4. The power monitoring circuit according to claim 1, characterized in that, The power monitoring circuit further includes a judgment circuit; the comparison circuit includes an overvoltage comparison circuit and an undervoltage comparison circuit. The input terminal of the overpressure comparison circuit is connected to the power supply to be monitored and the third reference power supply respectively, and the output terminal outputs the comparison result between the power supply to be monitored and the third reference power supply. The input terminal of the undervoltage comparator circuit is connected to the power supply to be monitored and the fourth reference power supply respectively, and the output terminal outputs the comparison result between the power supply to be monitored and the fourth reference power supply. The judgment circuit includes an OR gate, a third transistor, and a third resistor. The first input terminal of the OR gate is connected to the output terminal of the overvoltage comparator circuit and is used to receive the comparison result between the power supply to be monitored and the third reference power supply. The second input terminal is connected to the output terminal of the undervoltage comparator circuit and is used to receive the comparison result between the power supply to be monitored and the fourth reference power supply. The output terminal is connected to the control terminal of the third transistor. The third resistor and the third transistor are connected in series between the power supply and ground. The connection point between the third resistor and the third transistor serves as the output terminal of the judgment circuit. The output terminal of the judgment circuit is connected to the first input terminal of the self-locking circuit; The judgment circuit is used to output a judgment result indicating an abnormality of the power supply to be monitored to the first input terminal of the self-locking circuit based on the comparison result indicating overvoltage of the power supply to be monitored output by the overvoltage comparison circuit and / or the comparison result indicating undervoltage of the power supply to be monitored output by the undervoltage comparison circuit.

5. The power monitoring circuit according to claim 2, characterized in that, The power monitoring circuit further includes a first judgment circuit and a second judgment circuit; The first judgment circuit includes a fourth transistor and a fourth resistor. The control terminal of the fourth transistor is connected to the output terminal of the overvoltage comparison circuit as the input terminal of the first judgment circuit. The fourth resistor and the fourth transistor are connected in series between the power supply and ground. The connection point of the fourth transistor and the fourth resistor is connected to the input terminal of the first self-locking circuit as the output terminal of the first judgment circuit. The second judgment circuit includes a fifth transistor and a fifth resistor. The control terminal of the fifth transistor is connected to the output terminal of the undervoltage comparator circuit as the input terminal of the second judgment circuit. The fifth resistor and the fifth transistor are connected in series between the power supply and ground. The connection point of the fifth transistor and the fifth resistor is connected to the input terminal of the second self-locking circuit as the output terminal of the second judgment circuit.

6. The power monitoring circuit according to claim 3, characterized in that, The power monitoring circuit also includes a first sampling circuit and a second sampling circuit; The input terminal of the first sampling circuit is connected to the power supply to be monitored, and the output terminal is connected to the first input terminal of the overvoltage comparison circuit, which is used to provide the first sampling voltage. The input terminal of the second sampling circuit is connected to the power supply to be monitored, and the output terminal is connected to the second input terminal of the undervoltage comparator circuit to provide a second sampling voltage.

7. The power monitoring circuit according to claim 1, characterized in that, The self-locking circuit also includes an unlocking port; the unlocking port is connected to both the output of the comparator and the control terminal of the transistor. The unlocking port of the self-locking circuit is used to receive an unlocking signal. The unlocking signal is used to release the self-locking state of the self-locking circuit when the self-locking circuit enters the self-locking state and the output terminal of the self-locking circuit continuously outputs an alarm signal, and the output terminal of the self-locking circuit outputs a normal signal.

8. The power monitoring circuit according to claim 7, characterized in that, The power monitoring circuit also includes a processing circuit. The input terminal of the processing circuit is connected to the output terminal of the self-locking circuit to receive the status signal output by the self-locking circuit; the output terminal of the processing circuit is connected to the unlocking port of the self-locking circuit to provide an unlocking signal.

9. A microprocessor chip, characterized in that, It includes the power monitoring circuit and pin interface as described in any one of claims 1-7, wherein the output terminal of the self-locking circuit of the power monitoring circuit is connected to the pin interface.

10. An encoder, characterized in that, Includes the power monitoring circuit as described in any one of claims 1-8.

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