Reference circuit, tag chip, electronic tag and commodity

Abstract

The utility model provides a reference circuit, a tag chip, an electronic tag and a commodity. The reference circuit comprises an MOS tube M4, a triode Q4, a triode Q5, an operational amplifier C1, a resistor R4 and a resistor network. The grid electrode of the MOS tube M4 is connected with the output end of the operational amplifier, the source electrode / drain electrode of the MOS tube M4 is connected with a voltage VDD, the drain electrode / source electrode of the MOS tube M4 is connected with the resistor R4, and a first branch circuit where the triode Q4 is located, a second branch circuit where the triode Q5 is located and the resistor network are connected in parallel between the resistor R4 and the voltage VSS; the first branch circuit and the second branch circuit are respectively connected with two input ends of the operational amplifier, base electrodes and collector electrodes of the triode Q4 and the triode Q5 are connected with voltage VSS, and reference voltage VREF is output through a resistance network. The whole circuit is more compact, and is suitable for being used in applications with higher requirements on area and power consumption.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a reference circuit, tag chip, electronic tag, and commodity that improves the temperature coefficient and optimizes the area of ​​the bandgap. Background Technology

[0002] In recent years, with the deepening application of passive radio frequency identification (RFID) technology, the requirements for the identification distance of tags have become increasingly higher. The reference voltage of the tag chip is generated by the bandgap. As the original reference voltage of the entire electronic tag, the accuracy of the bandgap affects the performance of the overall chip circuit. Improving the circuit performance of the bandgap is an important focus.

[0003] Figure 1 This is an existing bandgap circuit (reference circuit) that uses two BJT (Block Joint Transistor) paths, which are then differentially amplified by an operational amplifier to obtain the PTAT (temperature-dependent current). This PTAT current is then mirrored onto a resistor via a current mirror to generate the PTAT voltage. Since the base-emitter voltage VBE of the BJT is the CTAT (temperature-dependent voltage), the positive and negative proportional voltages are superimposed to achieve a zero-temperature coefficient reference voltage output. Its drawbacks include the need for a transistor Q3 and a corresponding current mirror, resulting in higher cost. It also suffers from a large overall BJT area and a limited temperature coefficient adjustment range, leading to a lower output reference voltage. Where VBE is the base-emitter voltage, exhibiting CTAT characteristics, and K is the Boltzmann constant (approximately 1.38 × 10⁻⁶). -23 J / K), T is the absolute temperature (unit: K), and q is the electron charge (approximately 1.6 × 10⁻⁶). - 19 C), from Figure 2 The temperature drift of this existing bandgap circuit is 6.76mV. Utility Model Content

[0004] In view of the deficiencies in the prior art, the purpose of this utility model is to provide a reference circuit, a tag chip, an electronic tag, and a product.

[0005] A reference circuit according to the present invention includes: MOSFET M4, transistor Q4, transistor Q5, operational amplifier C1, resistor R4, and resistor network;

[0006] The gate of the MOS transistor M4 is connected to the output terminal of the operational amplifier. The source / drain of the MOS transistor M4 is connected to the voltage VDD. The drain / source of the MOS transistor M4 is connected to the resistor R4. The first branch where the transistor Q4 is located, the second branch where the transistor Q5 is located, and the resistor network are connected in parallel between the resistor R4 and the voltage VSS.

[0007] The first and second branches are respectively connected to the two input terminals of the operational amplifier C1. The emitter of the transistor Q5 is connected to the negative input terminal of the operational amplifier. The base and collector of the transistors Q4 and Q5 are connected to the voltage VSS, and the reference voltage VREF is output through the resistor network.

[0008] Furthermore, the area ratio of the transistor Q4 to the transistor Q5 is 4:1 to 16:1;

[0009] And / or, the emitter unit size of transistor Q4 and transistor Q5 is 5μm×5μm.

[0010] Furthermore, the area ratio of transistor Q4 to transistor Q5 is 8:1;

[0011] And / or, the emitter unit size of transistor Q4 and transistor Q5 is 2μm×2μm.

[0012] Furthermore, the MOS transistor M4 is a PMOS transistor, the source of the PMOS transistor is connected to the voltage VDD, and the drain is connected to the resistor R4;

[0013] Alternatively, the MOS transistor M4 may be an NMOS transistor, with the drain voltage VDD and the source resistor R4.

[0014] Furthermore, the first branch includes a resistor R8, a resistor R7, and a transistor Q4 connected in series, wherein the resistor R8 is connected to the resistor R4, and the resistor R7 is connected to the emitter of the transistor Q4;

[0015] When the MOS transistor M4 is a PMOS transistor, the positive input terminal of the operational amplifier is connected between the resistor R8 and the resistor R7; when the MOS transistor M4 is an NMOS transistor, the negative input terminal of the operational amplifier is connected between the resistor R8 and the resistor R7.

[0016] Furthermore, the second branch includes a resistor R9 and a transistor Q5 connected in series, wherein the resistor R9 is connected to the resistor R4;

[0017] When the MOS transistor M4 is a PMOS transistor, the negative input terminal of the operational amplifier is connected between the resistor R9 and the emitter of the transistor Q5; when the MOS transistor M4 is an NMOS transistor, the positive input terminal of the operational amplifier is connected between the resistor R9 and the emitter of the transistor Q5.

[0018] Furthermore, the resistor network includes resistors R5 and R6 connected in series. Resistor R5 is connected to resistor R4, and resistor R6 is connected to voltage VSS. The resistors R5 and R6 serve as the output terminal to output the reference voltage VREF.

[0019] A tag chip according to the present invention includes the aforementioned reference circuit.

[0020] An electronic tag according to the present invention includes the aforementioned tag chip.

[0021] According to the present invention, a product includes a product body and an electronic tag, wherein the electronic tag is attached to the product body or the packaging of the product body.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] This invention uses a MOSFET M4 to form a stable bias current source. Compared to the original structure (see...), Figure 1 This invention omits transistor Q3 and its corresponding current mirror, retaining only two transistors Q1 and Q2. The base-emitter voltage difference ΔV_BE is generated using their area ratio, and this voltage difference is proportional to temperature. This voltage difference is superimposed on the V_BE of transistor Q5, which has a negative temperature coefficient, and directly outputs a temperature-compensated reference voltage V_REF through a resistor network formed by resistors R5 and R6. This structure eliminates the need for a current mirror to replicate the current, simplifying the circuit structure, reducing the layout area, and facilitating integrated implementation.

[0024] In this invention, the area ratio of transistors Q1 to Q2 is increased compared to the original structure. Despite the increased ratio, the overall BJT area is reduced by decreasing the size of the emitter unit. Simultaneously, this adjustment not only enhances the magnitude of ΔV_BE but also widens the temperature coefficient adjustment range, making it suitable for applications with high requirements for area and power consumption. Attached Figure Description

[0025] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a schematic diagram of the existing bandgap circuit structure.

[0027] Figure 2 This is a schematic diagram of the performance of an existing bandgap circuit;

[0028] Figure 3 A schematic diagram of the circuit structure of this utility model when M4 is a PMOS transistor;

[0029] Figure 4 A schematic diagram illustrating the performance of this invention when M4 is a PMOS transistor;

[0030] In the diagram: 1-Resistor network, 2-First branch, 3-Second branch. Detailed Implementation

[0031] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0032] Example 1

[0033] like Figure 3 As shown, the reference circuit provided by this utility model includes: MOS transistor M4, transistor Q4, transistor Q5, operational amplifier C1, resistor R4, and resistor network 1.

[0034] In this embodiment, MOSFET M4 is a PMOS transistor. The gate of the PMOS transistor is connected to the output terminal of the operational amplifier, the source of the PMOS transistor is connected to voltage VDD, and the drain of the PMOS transistor is connected to resistor R4. The first branch 2 containing transistor Q4, the second branch 3 containing transistor Q5, and the resistor network are connected in parallel between resistor R4 and voltage VSS. The first branch 2 is connected to the positive input terminal of the operational amplifier, the emitter of transistor Q5 is connected to the negative input terminal of the operational amplifier, and the base and collector of transistors Q4 and Q5 are connected to voltage VSS. The reference voltage VREF is output through the resistor network.

[0035] In this embodiment, the area ratio of transistors Q4 and Q5 is between 4:1 and 16:1. This range originates from the general design range in BGR (bandgap reference) where the ΔVbe value is adjusted by the area ratio. 4 to 16 is a commonly used ratio range. Specifically, the area ratio is 8:1, but this invention is not limited to this. The transistors use a PNP structure with a smaller emitter unit size. The emitter unit sizes of transistors Q4 and Q5 are less than 5μm × 5μm. Specifically, the emitter unit size is 2μm × 2μm. The parallel multiple of transistor Q4 is M = 8, therefore the total emitter area of ​​Q4 is 32μm. 2 The parallel multiplication factor M of transistor Q5 is 1, therefore the total emitter area of ​​Q5 is 4μm. 2 However, this utility model is not limited thereto. This embodiment increases the proportion of BJTs in the PTAT branch circuit, and from -40℃ to 85℃, the bandgap temperature drift is only 1.1mV. (See...) Figure 4 ,according to TC is the temperature coefficient, representing the relative rate of change of the reference voltage with temperature, usually expressed in ppm / ℃. ΔV is the voltage difference between the output voltage and temperature. normal The reference voltage is the normal value, ΔT represents the temperature variation range, and the temperature drift is only 10.9, while the original structure has a temperature drift of 67. This invention optimizes the resistance ratio, saving 2000um^2 compared to the original structure, and effectively improves the temperature stability of the reference voltage.

[0036] In this embodiment, the first branch includes resistors R8 and R7 connected in series with transistor Q4. Resistor R8 is connected to resistor R4, the positive input terminal of the operational amplifier is connected between resistors R8 and R7, and resistor R7 is connected to the emitter of transistor Q4. The second branch includes resistor R9 connected in series with transistor Q5. Resistor R9 is connected to resistor R4, and the negative input terminal of the operational amplifier is connected between resistor R9 and the emitter of transistor Q5. The resistor network includes resistors R5 and R6 connected in series. Resistor R5 is connected to resistor R4, and resistor R6 is connected to voltage VSS. The area between resistors R5 and R6 serves as the output terminal, providing a reference voltage VREF. The first branch acts as a differential voltage differential, and the second branch acts as a reference voltage differential. Together, they construct a temperature-proportional voltage difference ΔV_BE, which is then converted into a PTAT current through resistor R7. A temperature compensation term is superimposed on the V_BE of Q5, and the resistor network formed by resistors R5 and R6 ultimately outputs a stable reference voltage VREF.

[0037] In the initial state, the two input terminals of operational amplifier C1 are respectively connected to transistor Q4 (emitter voltage Vpat) and transistor Q5 (emitter voltage Vcat). Due to the different areas of transistor Q4 and transistor Q5, a fixed base-emitter voltage difference ΔV_BE will be generated under the same current.

[0038] When operational amplifier C1 detects that Vpat≠Vcat, it will adjust its output voltage, control the conduction degree of the connected PMOS transistor, and adjust the current flowing through Q4 and Q5.

[0039] If Vpat>Vcat, the output voltage of operational amplifier C1 increases, making the PMOS transistor less conductive and the current decreases, resulting in both Vpat and Vcat decreasing, but Vpat decreases more significantly, and the difference between the two decreases.

[0040] If Vpat<Vcat, the output voltage of operational amplifier C1 decreases, making the PMOS transistor more conductive and the current increases, both Vpat and Vcat increase, Vpat increases more significantly, and the difference also decreases.

[0041] After closed-loop regulation, Vpat and Vcat tend to be consistent, forming a stable ΔV_BE, ensuring the stable output of the reference voltage VREF.

[0042] This stable current generates a voltage drop through the series-connected resistors R5 and R6, and the reference voltage VREF is output at the voltage division point. Since ΔV_BE is a positive temperature coefficient (PTAT) and the V_BE of Q5 is a negative temperature coefficient (CTAT), the two are superimposed to achieve temperature drift compensation and generate a stable reference voltage with a near-zero temperature coefficient.

[0043] The output of the present utility model is obtained by voltage division of resistors R5 and R6:

[0044]

[0045] Embodiment 2

[0046] A reference circuit provided by the present utility model includes: MOS transistor M4, transistor Q4, transistor Q5, operational amplifier C1, resistor R4, and resistor network 1.

[0047] In this embodiment, MOS transistor M4 is an NMOS transistor.

[0048] Among them, the gate of the NMOS transistor is connected to the output terminal of the operational amplifier, the drain of the NMOS transistor is connected to the voltage VDD, the source of the NMOS transistor is connected to the resistor R4, the first branch 2 where the triode Q4 is located, the second branch 3 where the triode Q5 is located, and the resistor network are connected in parallel between the resistor R4 and the voltage VSS. The first branch 2 is connected to the negative input terminal of the operational amplifier, the emitter of the triode Q5 is connected to the positive input terminal of the operational amplifier, the bases and collectors of the triodes Q4 and Q5 are connected to the voltage VSS, and the reference voltage VREF is output through the resistor network.

[0049] In this embodiment, the first branch 2 includes the resistor R8, the resistor R7, and the triode Q4 connected in series in sequence. The resistor R8 is connected to the resistor R4, the negative input terminal of the operational amplifier C1 is connected between the resistor R8 and the resistor R7, and the resistor R7 is connected to the emitter of the triode Q4. The second branch 3 includes the resistor R9 and the triode Q5 connected in series in sequence. The resistor R9 is connected to the resistor R4, and the positive input terminal of the operational amplifier C1 is connected between the resistor R9 and the emitter of the triode Q5. The resistor network includes the resistor R5 and the resistor R6 connected in series. The resistor R5 is connected to the resistor R4, the resistor R6 is connected to the voltage VSS, and the reference voltage VREF is output between the resistor R5 and the resistor R6. The first branch 2 is used as a differential construction branch, and the second branch 3 is used as a reference branch. The two are jointly used to construct a ΔV_BE voltage difference proportional to the temperature, and a PTAT current is obtained through the resistor R7. A temperature compensation term is superimposed on the basis of the V_BE of Q5, and finally a stable reference voltage VREF is output through the resistor network formed by the resistor R5 and R6.

[0050] In the initial state, the two input terminals of the operational amplifier C1 are respectively connected to the first branch 2 where the triode Q4 is located and the triode Q5 (emitter voltage Vcat). Due to the different areas of the triodes Q4 and Q5, a fixed base-emitter voltage difference ΔV_BE will be generated under the same current.

[0051] When the operational amplifier C1 detects that Vpat≠Vcat, it will adjust its output voltage, control the conduction degree of the connected NMOS transistor, and adjust the current flowing through Q4 and Q5.

[0052] If Vpat>Vcat, the output voltage of the operational amplifier C1 increases, making the NMOS transistor less conductive and the current decreases, resulting in both Vpat and Vcat decreasing, but Vpat decreases more significantly, and the difference between the two decreases.

[0053] If Vpat<Vcat, the output voltage of the operational amplifier C1 decreases, making the NMOS transistor more conductive and the current increases, Vpat and Vcat both increase, Vpat increases more significantly, and the difference also decreases.

[0054] After closed-loop regulation, Vpat and Vcat tend to be consistent, forming a stable ΔV_BE, which ensures a stable output of the reference voltage VREF.

[0055] This stabilizing current generates a voltage drop through the series resistors R5 and R6, and the voltage divider outputs a reference voltage VREF. Since ΔV_BE has a positive temperature coefficient (PTAT) and Q5's V_BE has a negative temperature coefficient (CTAT), their superposition achieves temperature drift compensation, generating a stable reference voltage with a near-zero temperature coefficient.

[0056] The output of this invention is obtained by voltage division using resistors R5 and R6:

[0057]

[0058] Example 3

[0059] The reference circuit of Embodiment 1 or Embodiment 2 described above can be applied to a tag chip, which can be used in an electronic tag. The electronic tag can be connected to the product itself or its packaging to obtain and identify relevant product information or for anti-counterfeiting identification.

[0060] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0061] The specific embodiments of this utility model have been described above. It should be understood that this utility model is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the substantive content of this utility model. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A reference circuit, characterized in that, include: MOSFET M4, transistor Q4, transistor Q5, operational amplifier C1, resistor R4 and resistor network (1); The gate of the MOS transistor M4 is connected to the output terminal of the operational amplifier. The source / drain of the MOS transistor M4 is connected to the voltage VDD. The drain / source of the MOS transistor M4 is connected to the resistor R4. The first branch (2) where the transistor Q4 is located, the second branch (3) where the transistor Q5 is located, and the resistor network (1) are connected in parallel between the resistor R4 and the voltage VSS. The first branch (2) and the second branch (3) are respectively connected to the two input terminals of the operational amplifier C1. The base and collector of the transistors Q4 and Q5 are connected to the voltage VSS, and the reference voltage VREF is output through the resistor network (1).

2. The reference circuit according to claim 1, characterized in that, The area ratio of transistor Q4 to transistor Q5 is 4:1 to 16:1; And / or, the emitter unit size of transistor Q4 and transistor Q5 is 5μm×5μm.

3. The reference circuit according to claim 2, characterized in that, The area ratio of transistor Q4 to transistor Q5 is 8:1; And / or, the emitter unit size of transistor Q4 and transistor Q5 is 2μm×2μm.

4. The reference circuit according to claim 1, characterized in that, The MOS transistor M4 is a PMOS transistor, and the source of the PMOS transistor is connected to the voltage VDD, and the drain is connected to the resistor R4. Alternatively, the MOS transistor M4 may be an NMOS transistor, with the drain voltage VDD and the source resistor R4.

5. The reference circuit according to claim 1, characterized in that, The first branch (2) includes a resistor R8, a resistor R7 and a transistor Q4 connected in series. The resistor R8 is connected to the resistor R4 and the resistor R7 is connected to the emitter of the transistor Q4. When the MOS transistor M4 is a PMOS transistor, the positive input terminal of the operational amplifier is connected between the resistor R8 and the resistor R7; when the MOS transistor M4 is an NMOS transistor, the negative input terminal of the operational amplifier is connected between the resistor R8 and the resistor R7.

6. The reference circuit according to claim 1, characterized in that, The second branch (3) includes a resistor R9 and a transistor Q5 connected in series, wherein the resistor R9 is connected to the resistor R4; When the MOS transistor M4 is a PMOS transistor, the negative input terminal of the operational amplifier is connected between the resistor R9 and the emitter of the transistor Q5; when the MOS transistor M4 is an NMOS transistor, the positive input terminal of the operational amplifier is connected between the resistor R9 and the emitter of the transistor Q5.

7. The reference circuit according to claim 1, characterized in that, The resistor network (1) includes resistors R5 and R6 connected in series. Resistor R5 is connected to resistor R4, and resistor R6 is connected to voltage VSS. Resistor R5 and resistor R6 serve as the output terminal to output reference voltage VREF.

8. A tag chip, characterized in that, Includes the reference circuit as described in any one of claims 1-7.

9. An electronic tag, characterized in that, Includes the tag chip as described in claim 8.

10. A commodity, characterized in that, It includes the product body and the electronic tag as described in claim 9, the electronic tag being attached to the product body or the packaging of the product body.

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