Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device, the array substrate comprises a touch control area and a binding area arranged on one side of the touch control area, the binding area comprises a fan-out area, the fan-out area comprises at least one touch control fan-out line and at least one data fan-out line which are arranged on a substrate, and the touch control fan-out line and the data fan-out line are arranged on the substrate. The orthographic projection of the at least one touch fan-out line on the substrate is not overlapped with the orthographic projection of the adjacent at least one data fan-out line on the substrate; and display abnormities such as screen splitting of the display device are avoided.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) have seen rapid development due to their small size, low power consumption, and lack of radiation. An LCD device consists of a thin film transistor array (TFT) substrate and a color filter (CF) substrate. Liquid crystal (LC) molecules are disposed between the TFT substrate and the color filter substrate. A grayscale display is achieved by controlling a second electrode and a first electrode to create an electric field that drives the liquid crystal deflection. Utility Model Content

[0003] This utility model provides an array substrate and a display device to avoid display abnormalities such as screen splitting.

[0004] This utility model provides an array substrate, including a touch area and a bonding area disposed on one side of the touch area. The bonding area includes a fan-out area, which includes at least one touch fan-out line and at least one data fan-out line disposed on the substrate. The orthographic projection of the at least one touch fan-out line on the substrate does not overlap with the orthographic projection of the adjacent at least one data fan-out line on the substrate.

[0005] In an exemplary embodiment, the at least one touch fan-out line and the at least one data fan-out line are arranged alternately.

[0006] In an exemplary embodiment, the at least one touch fan-out line and the adjacent at least one data fan-out line are located in different film layers.

[0007] In an exemplary embodiment, the at least one touch fan-out line is located on the side of the at least one data fan-out line away from the substrate.

[0008] In an exemplary embodiment, the touch area includes a touch structure layer disposed on the substrate and at least two touch signal lines. The touch structure layer includes at least one touch electrode. The polarities of the at least two touch signal lines are opposite. One end of each of the at least two touch signal lines is connected to the same touch electrode, and the other end of each of the at least two touch signal lines is connected to a corresponding touch fan-out line.

[0009] In an exemplary embodiment, the at least two touch signal lines include a first touch signal line and a second touch signal line. The first touch signal line and the second touch signal line have opposite polarities. One end of the first touch signal line and the second touch signal line are respectively connected to the same touch electrode, and the other end of the first touch signal line and the second touch signal line are respectively connected to the corresponding touch fan-out line.

[0010] In an exemplary embodiment, the touch area includes at least one touch signal line disposed on the substrate, the at least one touch signal line being correspondingly connected to the at least one touch fan-out line, and the at least one touch signal line and the connected touch fan-out line being located in the same film layer.

[0011] In an exemplary embodiment, the touch area includes at least one data signal line disposed on the substrate, the at least one data signal line being connected to at least one data fan-out line, and the at least one data signal line and the connected data fan-out line being located in different film layers.

[0012] In an exemplary embodiment, the at least one data fan-out line is located on the side of the connected data signal line near the substrate.

[0013] In an exemplary embodiment, the bonding area further includes a driver chip area, which is disposed on the side of the fan-out area away from the touch area. The driver chip area includes at least one driver chip, and the at least one touch fan-out line and the at least one data fan-out line are connected to the at least one driver chip.

[0014] In an exemplary embodiment, the touch area includes a circuit unit disposed on the substrate, the circuit unit including at least one thin-film transistor, the at least one thin-film transistor being an oxide thin-film transistor.

[0015] This utility model embodiment also provides a display device, including an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate is the aforementioned array substrate.

[0016] In this embodiment of the present disclosure, the array substrate avoids the overlap of the orthographic projections of the touch fan-out lines and the adjacent data fan-out lines on the substrate, effectively improving the abnormal pulling of the data fan-out lines, avoiding display abnormalities such as screen splitting on the display device, and ensuring the display effect.

[0017] In this embodiment, the array substrate has the touch fan-out line and the adjacent data fan-out line located on different film layers, which reduces the parasitic capacitance between the touch fan-out line and the adjacent data fan-out line, effectively improves the abnormal pulling of the data fan-out line, avoids display abnormalities such as screen splitting in the display device, and ensures the display effect.

[0018] In this embodiment of the present disclosure, the array substrate uses the opposite polarities of the first touch signal line and the second touch signal line to reduce the parasitic capacitance difference between the touch fan-out lines and the data fan-out lines located on opposite sides of the center line of the driver chip, thereby avoiding display abnormalities such as screen splitting in the display device and ensuring the display effect.

[0019] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solution of this utility model and do not constitute a limitation on the technical solution of this utility model.

[0021] Figure 1 This is a schematic diagram of the structure of a related display device;

[0022] Figure 2 This is a schematic diagram of the structure of another related display device;

[0023] Figure 3 This is a schematic diagram of the fan-out area of ​​the relevant display device;

[0024] Figure 4 This is a schematic diagram of one side of the fan-out area of ​​the relevant display device;

[0025] Figure 5 This is a schematic diagram of the other side of the fan-out area of ​​the relevant display device;

[0026] Figure 6 This is a schematic diagram of the planar structure of the array substrate according to an embodiment of the present disclosure;

[0027] Figure 7 This is a schematic diagram of the planar structure of the fan-out region of the array substrate according to an embodiment of the present disclosure;

[0028] Figure 8 This is a schematic diagram of the routing of touch fan-out lines and data fan-out lines on one side of the fan-out area of ​​the array substrate according to an embodiment of this disclosure;

[0029] Figure 9 This is a schematic diagram of the routing of touch fan-out lines and data fan-out lines on the other side of the fan-out area of ​​the array substrate in an embodiment of this disclosure.

[0030] Figure 10 This is a schematic diagram of the planar structure of the touch structure layer in the array substrate of this embodiment. Detailed Implementation

[0031] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in at least two different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited solely to the content described in the following embodiments. Without conflict, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0032] In the accompanying drawings, the size of one or at least two constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or at least two components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0033] The ordinal numbers “first,” “second,” “third,” etc., used in this specification are for the purpose of avoiding confusion among constituent elements, not for limiting quantity. “At least two” in this disclosure refers to two or more quantities.

[0034] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0035] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0036] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0037] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0038] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0039] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0040] In this disclosure, "about" or "approximately" means without strictly defining the limits, allowing for the possibility of errors in the process and measurement.

[0041] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0042] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0043] Figure 1 This is a schematic diagram of the structure of a related display device; Figure 2 This is a schematic diagram of another related display device. With the increase in resolution and refresh rate of liquid crystal displays (LCDs), the requirements for in-cell touch functionality are gradually increasing. Low-Temperature Polysilicon (LTPS) display devices generally use multiplexing circuits (MUX) to reduce the number of data signal lines, thereby reducing costs. Because the electron migration speed difference between oxide semiconductor (OPS) and LPS display devices is greater than 500%, OPS display devices cannot use multiplexing circuits (MUX) to reduce the number of data signal lines. Taking WQHD (WideQuad High Definition) of 2520*1680 as an example, an OPS display device using a single-gate in-cell touch structure requires five 10' driver chips. Figure 1 As shown. To reduce the number of driver chips 10', oxide semiconductor display devices can adopt a triple-gate in-cell touch structure, reducing the number of data signal lines from 2520*3 to 2520*1, and the number of driver chips 10' from 5 to 2, effectively reducing costs, such as... Figure 2 As shown. However, display devices using a Triple Gate In-Cell Touch structure exhibit a split-screen phenomenon, for example, a 6-screen split, during flicker testing.

[0044] Figure 3 This is a schematic diagram of the fan-out area of ​​a related display device. The inventors of this application have discovered that the split-screen phenomenon occurs because: (The text abruptly ends here, likely due to an incomplete sentence or missing information.) Figure 3 As shown, in the fan-out area 210' of the bonding area of ​​the display device, both the touch fan-out line 20' and the data fan-out line 30' converge towards the driver chip 10' and are connected to the driver chip 10', causing at least a portion of the orthographic projection of the touch fan-out line 20' onto the substrate to overlap with the orthographic projection of the data fan-out line 30' onto the substrate. Due to the different output signals of the data fan-out lines 30' located on opposite sides of the driver chip 10', and the different overlapping areas of the orthographic projections of the touch fan-out line 20' and the data fan-out line 30' onto the substrate, the data fan-out lines 30' located on opposite sides of the driver chip 10' experience different pulling forces, resulting in a split-screen phenomenon in the display.

[0045] Figure 4 This is a schematic diagram of one side of the fan-out area of ​​the relevant display device; Figure 5 This is a schematic diagram of the other side of the fan-out area of ​​the relevant display device. Among them, Figure 4 The diagram illustrates the routing of the data fan-out lines and touch fan-out lines located on one side of the driver chip. Figure 5 The diagram illustrates the routing of the data fan-out lines and touch fan-out lines located on the other side of the driver chip. For example... Figure 4 and Figure 5 As shown, one end of the touch fan-out line 20' is connected to the touch signal line 21' of the touch area, and the other end of the touch fan-out line 20' is connected to the driver chip. One end of the data fan-out line 30' is connected to the data signal line 31' of the touch area, and the other end of the data fan-out line 30' is connected to the driver chip. On the side opposite to the first direction X of the driver chip (e.g., the left side), at least a portion of the orthographic projection of the touch fan-out line 20' onto the substrate overlaps with the orthographic projection of the adjacent data fan-out line 30' onto the substrate, and the adjacent data fan-out line 30' is positive. The two form a first parasitic capacitance, such as... Figure 4 As shown. On one side (e.g., the right side) of the driver chip in the first direction X, at least a portion of the orthogonal projection of the touch fan-out line 20' onto the substrate overlaps with the orthogonal projection of the adjacent data fan-out line 30' onto the substrate, and the adjacent data fan-out line 30' is the negative terminal. The two form a second parasitic capacitance, as shown. Figure 5 As shown. Due to the different parasitic capacitances generated by the touch fan-out lines 20' on both sides of the first direction X of the driver chip and the adjacent data fan-out lines 30', that is, the first parasitic capacitance and the second parasitic capacitance are different, and the polarity of the data fan-out lines 30' is opposite, the data fan-out lines 30' on both sides of the first direction X of the driver chip are pulled abnormally, causing the display screen to split.

[0046] This utility model provides an array substrate, including a touch area and a bonding area disposed on one side of the touch area. The bonding area includes a fan-out area, which includes at least one touch fan-out line and at least one data fan-out line disposed on the substrate. The orthographic projection of the at least one touch fan-out line on the substrate does not overlap with the orthographic projection of the adjacent at least one data fan-out line on the substrate.

[0047] In an exemplary embodiment, the at least one touch fan-out line and the at least one data fan-out line are arranged alternately.

[0048] In an exemplary embodiment, the at least one touch fan-out line and the adjacent at least one data fan-out line are located in different film layers.

[0049] In an exemplary embodiment, the at least one touch fan-out line is located on the side of the at least one data fan-out line away from the substrate.

[0050] In an exemplary embodiment, the touch area includes a touch structure layer disposed on the substrate and at least two touch signal lines. The touch structure layer includes at least one touch electrode. The polarities of the at least two touch signal lines are opposite. One end of each of the at least two touch signal lines is connected to the same touch electrode, and the other end of each of the at least two touch signal lines is connected to a corresponding touch fan-out line.

[0051] The following examples illustrate the solution of this embodiment.

[0052] Figure 6 This is a schematic diagram of the planar structure of the array substrate according to an embodiment of the present disclosure. In an exemplary embodiment, such as... Figure 6 As shown, on a plane parallel to the array substrate, the array substrate may include: a touch area 100, a bonding area 200 located on one side of the touch area 100, and a border area 300 located on the other sides of the touch area 100. The bonding area 200 may be connected to the border area 300. For example, the bonding area 200 may be the lower border of the array substrate, and the border area 300 may include the remaining border areas of the array substrate other than the lower border.

[0053] In an exemplary embodiment, the touch area 100 may be a flat area, including at least two circuit units 50 arranged in an array and a touch structure layer. The circuit unit 50 may include at least one thin-film transistor, a pixel electrode, and a common electrode disposed on a substrate. The thin-film transistor may include an active layer, a gate, and source / drain electrodes disposed on the substrate. The touch structure layer may include at least one touch electrode disposed on the substrate. The touch structure layer may be based on the working principle of self-capacitance (or voltage) detection, using a single conductive layer to form at least one touch electrode. The driving chip realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0054] In an exemplary embodiment, the thin-film transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor or an oxide thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide semiconductor. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current.

[0055] In an exemplary embodiment, the touch structure layer can be an in-cell touch structure, such as a triple gate in-cell touch structure, thereby reducing the number of driver chips in the array substrate.

[0056] In an exemplary embodiment, the touch area 100 may further include at least one gate signal line 60, at least one data signal line 31, and at least one touch signal line 21. The at least one gate signal line 60 may extend along a first direction X, and the at least one data signal line 31 and the at least one touch signal line 21 may extend along a second direction Y. The orthographic projections of the at least one gate signal line 60 and the at least one data signal line 31 onto the substrate may intersect to form a circuit unit area. A circuit unit 50 may be disposed within a circuit unit area. The at least one data signal line 31 may be electrically connected to the at least one circuit unit 50 and may be configured to provide a data signal to the at least one circuit unit 50. The at least one gate signal line 60 may be electrically connected to the at least one circuit unit 50 and may be configured to provide a gate drive signal to the at least one circuit unit 50. A touch electrode may cover the at least one circuit unit area, and the at least one touch signal line 21 may be electrically connected to the at least one touch electrode and may be configured to provide a touch signal.

[0057] In an exemplary embodiment, the first direction X may be the extension direction of the gate signal line 60 in the touch area 100 (e.g., row direction), and the second direction Y may be the extension direction of the data signal line 31 in the touch area 100 (e.g., column direction). The first direction X and the second direction Y may intersect each other, for example, they may be perpendicular to each other.

[0058] In an exemplary embodiment, the touch area 100 can be a rectangle or a rounded rectangle. However, this embodiment is not limited to this. For example, the touch area can be a circle or other shapes.

[0059] In an exemplary embodiment, the bonding region 200 may include a fan-out region 210, a driver chip region 220, and a bonding pin region 230 arranged sequentially along a direction away from the touch region 100. The fan-out region 210 may be connected to the bezel region 300 and is located on one side of the touch region 100 in the second direction Y. The fan-out region 210 includes touch fan-out lines and data fan-out lines disposed on the substrate. The driver chip region 220 is connected to the fan-out region 210 on one side of the second direction Y and to the bonding pin region 230 on the other side of the second direction Y. The driver chip region 220 includes at least one driver chip 10 disposed on the substrate. For example, the driver chip region 220 may include two driver chips 10 spaced apart along the first direction X. Both driver chips 10 may be Touch and Display Driver Integration (TDDI) chips, and the driver chips are configured to connect to the touch fan-out lines and data fan-out lines. The bonding pin area 230 is connected to the driver chip area 220 on one side of the second direction Y. The bonding pin area 230 includes at least two pins disposed on the substrate. The bonding pin area 230 is configured to bond with the flexible printed circuit board 400 (FPC). One end of the flexible printed circuit board 400 is connected to the bonding pin area 230 in the second direction Y, and the other end of the flexible printed circuit board 400 is connected to the external circuit board 500 in the second direction Y.

[0060] Figure 7 This is a schematic diagram of the planar structure of the fan-out region of the array substrate according to an embodiment of this disclosure. Figure 7 The diagram illustrates the routing of the touch fan-out lines and data fan-out lines in the fan-out area. In an exemplary embodiment, such as... Figure 7 As shown, on a plane parallel to the array substrate, the touch area includes at least one touch signal line 21 and at least one data signal line 31. Both the touch signal line 21 and the data signal line 31 extend along the second direction Y, and can be alternately arranged along the first direction X, meaning that a touch signal line 21 can be positioned between two adjacent data signal lines 31. The at least two touch signal lines 21 can be located on opposite sides of the centerline O of a driver chip 10 along the second direction Y in the first direction X, and the at least two data signal lines 31 can also be located on opposite sides of the centerline O of a driver chip 10 along the second direction Y in the first direction X. The at least one touch signal line 21 and the at least one data signal line 31 can extend from the left side of the centerline O of the driver chip 10 towards the fan-out area 210, and can also extend from the right side of the centerline O of the driver chip 10 towards the fan-out area 210.

[0061] In an exemplary embodiment, at least one touch signal line 21 and at least one data signal line 31 can be located in the same film layer on a plane perpendicular to the array substrate, and can be fabricated using the same conductive material and the same manufacturing process, thereby simplifying the process and reducing costs. For example, at least one touch signal line 21 and at least one data signal line 31 can both be located in the source / drain conductive layer. In some embodiments, at least one touch signal line and at least one data signal line can be located in different film layers, which will not be elaborated further in this disclosure.

[0062] In an exemplary embodiment, on a plane parallel to the array substrate, the fan-out region 210 is connected to the touch area on one side of the second direction Y, and the fan-out region 210 is connected to the driver chip area on the other side of the second direction Y. The fan-out region 210 includes at least one touch fan-out line 20 and at least one data fan-out line 30 disposed on the substrate. One end of the touch fan-out line 20 is connected to the corresponding touch signal line 21, and the other end of the touch fan-out line 20 extends toward the driver chip 10 and is connected to the driver chip 10; one end of the data fan-out line 30 is connected to the corresponding data signal line 31, and the other end of the data fan-out line 30 extends toward the driver chip 10 and is connected to the driver chip 10.

[0063] In an exemplary embodiment, at least two touch fan-out lines 20 may be located on opposite sides of the center line O of a driver chip 10 along the second direction Y in the first direction X, and at least two data fan-out lines 30 may be located on opposite sides of the center line O of a driver chip 10 along the second direction Y in the first direction X. At least one touch fan-out line 20 and at least one data fan-out line 30 may extend from the left side of the center line O of the driver chip 10 toward the driver chip 10 and connect to the driver chip 10; a portion of the touch fan-out lines 20 and a portion of the data fan-out lines 30 may extend from the right side of the center line O of the driver chip 10 toward the fan-out area 210 and connect to the driver chip 10.

[0064] Figure 8 This is a schematic diagram of the routing of touch fan-out lines and data fan-out lines on one side of the fan-out area of ​​the array substrate according to an embodiment of this disclosure; Figure 9 This is a schematic diagram showing the routing of the touch fan-out lines and data fan-out lines on the other side of the fan-out area of ​​the array substrate according to an embodiment of this disclosure. Figure 8 The diagram illustrates the routing of the touch fan-out line and the data fan-out line located to the left of the center line O of the driver chip. Figure 9 The diagram illustrates the routing of the touch fan-out line and the data fan-out line located to the right of the center line O of the driver chip. In an exemplary embodiment, such as... Figure 8 and Figure 9As shown, the orthographic projection of at least one touch fan-out line 20 on the substrate does not overlap with the orthographic projection of the adjacent at least one data fan-out line 30 on the substrate.

[0065] In this embodiment, the array substrate avoids overlap between the orthographic projections of the touch fan-out line 20 and the adjacent data fan-out line 30 on the substrate, effectively improving the abnormal pulling of the data fan-out line 30, preventing display abnormalities such as screen splitting in the display device, and ensuring the display effect.

[0066] In an exemplary embodiment, at least one touch fan-out line 20 and at least one data fan-out line 30 are arranged alternately, that is, a touch fan-out line 20 can be set between two adjacent data fan-out lines 30, and the orthographic projection of the touch fan-out line 20 on the substrate does not overlap with the orthographic projection of the two adjacent data fan-out lines 30 on the substrate.

[0067] In an exemplary embodiment, on a plane perpendicular to the array substrate, at least one touch fan-out line 20 and two adjacent data fan-out lines 30 may be located in different film layers. For example, the touch fan-out line 20 may be located on the side of the two adjacent data fan-out lines 30 away from the substrate, and at least one touch fan-out line 20 may be located in the source / drain conductive layer, while the two adjacent data fan-out lines 30 may be located in the gate conductive layer. In some embodiments, at least one touch fan-out line may be located on the side of the two adjacent data fan-out lines closer to the substrate, which will not be elaborated further in this disclosure.

[0068] In this embodiment, the array substrate has the touch fan-out line 20 and the two adjacent data fan-out lines 30 located on different film layers, which reduces the parasitic capacitance of the touch fan-out line 20 and the two adjacent data fan-out lines 30, effectively improves the abnormal pulling of the data fan-out line 30, avoids display abnormalities such as screen splitting in the display device, and ensures the display effect.

[0069] In an exemplary embodiment, at least one touch fan-out line 20 may be located in the same film layer as the connected touch signal line 21, and be fabricated using the same conductive material and the same manufacturing process, thereby simplifying the process and reducing costs. For example, at least one touch fan-out line 20 and the connected touch signal line 21 may both be located in the source / drain conductive layer. In some embodiments, at least one touch signal line may be located in a different film layer from the connected touch signal line, which will not be elaborated further in this disclosure.

[0070] In an exemplary embodiment, at least one data fan-out line 30 may be located in a different film layer from the connected data signal line 31. For example, at least one data fan-out line 30 may be located on the side of the connected data signal line 31 closer to the substrate, at least one data fan-out line 30 may be located in the gate conductive layer, and the connected data signal line 31 may be located in the source / drain conductive layer. At least one data fan-out line 30 may be connected to a connection electrode 32 through a via, and the connection electrode 32 may be connected to the data signal line 31. The connection electrode 32 and the data signal line 31 may be located in the same film layer and integrated together.

[0071] Figure 10 This is a schematic diagram of the planar structure of the touch structure layer in the array substrate according to an embodiment of this disclosure. In an exemplary embodiment, such as... Figure 10 As shown, the touch structure layer 40 of the array substrate in this embodiment may include at least one touch electrode 41, which may be arranged in an array, and one touch electrode 41 may cover at least one circuit unit. At least one touch signal line 21 includes a first touch signal line 21-1 and a second touch signal line 21-2, which are respectively connected to the same touch electrode 41, so that one touch electrode 41 is connected to the driver chip through the first touch signal line 21-1 and the second touch signal line 21-2 respectively.

[0072] In an exemplary embodiment, the first touch signal line 21-1 and the second touch signal line 21-2 have opposite polarities. For example, the first touch signal line 21-1 can be a positive electrode and the second touch signal line 21-2 can be a negative electrode; or, the first touch signal line 21-1 can be a negative electrode and the second touch signal line 21-2 can be a positive electrode.

[0073] In this embodiment of the present disclosure, the array substrate uses the opposite polarities of the first touch signal line 21-1 and the second touch signal line 21-2 to reduce the parasitic capacitance difference between the touch fan-out line 20 and the data fan-out line 30 located on opposite sides of the center line O of the driver chip 10, thereby avoiding display abnormalities such as screen splitting in the display device and ensuring the display effect.

[0074] In some embodiments, a touch electrode may also be connected to a number of other touch signal lines. For example, a touch electrode may be connected to 3, 4, 5 or other numbers of touch signal lines, and at least two touch signal lines may have opposite polarities. This disclosure will not elaborate further.

[0075] In an exemplary embodiment, this disclosure also provides a display device, which may include: an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the color filter substrate. The array substrate may be the array substrate of the foregoing embodiments, the color filter substrate may include a black matrix and a filter layer, and the liquid crystal layer may include at least two liquid crystal molecules having dielectric anisotropy. In response to an electric field applied between the array substrate and the color filter substrate, the at least two liquid crystal molecules may rotate in a predetermined direction between the array substrate and the color filter substrate, thereby allowing or blocking the transmission of light.

[0076] In exemplary embodiments, the display device of this disclosure may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame or navigator, or it may be a product or component with touch and display functions.

[0077] Although the embodiments disclosed in this utility model are as described above, the content described is only for the purpose of facilitating understanding of this utility model and is not intended to limit this utility model. Any person skilled in the art to which this utility model pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this utility model, but the patent protection scope of this utility model shall still be defined by the appended claims.

Claims

1. An array substrate, characterized by, It includes a touch area and a binding area disposed on one side of the touch area. The binding area includes a fan-out area, which includes at least one touch fan-out line and at least one data fan-out line disposed on the substrate. The orthographic projection of the at least one touch fan-out line on the substrate does not overlap with the orthographic projection of the adjacent at least one data fan-out line on the substrate.

2. The array substrate of claim 1, wherein, The at least one touch fan-out line and the at least one data fan-out line are arranged alternately.

3. The array substrate of claim 1, wherein, The at least one touch fan-out line and the adjacent at least one data fan-out line are located in different film layers.

4. The array substrate of claim 3, wherein, The at least one touch fan-out line is located on the side of the adjacent at least one data fan-out line away from the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein, The touch area includes a touch structure layer disposed on the substrate and at least two touch signal lines. The touch structure layer includes at least one touch electrode. The polarities of the at least two touch signal lines are opposite. One end of each of the at least two touch signal lines is connected to the same touch electrode, and the other end of each of the at least two touch signal lines is connected to a corresponding touch fan-out line.

6. The array substrate of claim 5, wherein, The at least two touch signal lines include a first touch signal line and a second touch signal line. The first touch signal line and the second touch signal line have opposite polarities. One end of the first touch signal line and the second touch signal line are respectively connected to the same touch electrode, and the other end of the first touch signal line and the second touch signal line are respectively connected to the corresponding touch fan-out line.

7. The array substrate according to any one of claims 1 to 4, wherein, The touch area includes at least one touch signal line disposed on the substrate, the at least one touch signal line being connected to at least one touch fan-out line, and the at least one touch signal line and the connected touch fan-out line being located in the same film layer.

8. The array substrate according to any one of claims 1 to 4, wherein, The touch area includes at least one data signal line disposed on the substrate, the at least one data signal line being connected to at least one data fan-out line, and the at least one data signal line and the connected data fan-out line being located in different film layers.

9. The array substrate of claim 8, wherein, The at least one data fan-out line is located on the side of the connected data signal line closer to the substrate.

10. The array substrate according to any one of claims 1 to 4, wherein, The bonding area also includes a driver chip area, which is located on the side of the fan-out area away from the touch area. The driver chip area includes at least one driver chip, and the at least one touch fan-out line and the at least one data fan-out line are connected to the at least one driver chip.

11. The array substrate according to any one of claims 1 to 4, wherein, The touch area includes a circuit unit disposed on the substrate, the circuit unit including at least one thin-film transistor, the at least one thin-film transistor being an oxide thin-film transistor.

12. A display device, characterized by comprising: It includes an array substrate and a color filter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 11.

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