Fast detection display panel

Abstract

The embodiment of the utility model belongs to the technical field of display panels. The utility model also relates to a fast detection display panel, which comprises a display panel main body and a GOA circuit arranged on the display panel main body, the display panel main body is provided with an FPC binding pad, a signal line main body is connected between the FPC binding pad and the GOA circuit, and the FPC binding pad is connected with a main screen FPC. According to the invention, the signal line main body is directly connected to the FPC binding pad, and the main screen FPC is connected with the test board during detection, so that the screen is lightened, compared with the prior art, a fast detection Pad is removed, the problem of insufficient wiring space of the signal line main body caused by large occupied area of the fast detection Pad is effectively eliminated, the layout of the signal line is optimized, and the detection efficiency is improved. And the routing distance and the line width are reduced, so that the risk of short circuit of the signal line is reduced.

Description

Technical Field

[0001] This utility model relates to the field of display panel technology, and more specifically, to a fast detection display panel. Background Technology

[0002] In the display panel industry, the actual drawing and testing of array circuits is a key step in product quality and cost control. However, traditional rapid testing methods have encountered significant challenges in this process.

[0003] Specifically, when drawing array circuits, the fast-detection pads, used as test connection points, often occupy a large area (e.g., Figure 4 As shown, Figure 4 The feature marked at point B ("Quick Test Pad") directly restricts the space for signal line routing, forcing a reduction in trace spacing and line width. These issues create hidden dangers in subsequent screen manufacturing, significantly increasing the risk of short circuits and threatening production efficiency and yield. Therefore, we have made improvements and proposed a quick test display panel. Utility Model Content

[0004] The technical problem to be solved by this utility model embodiment is that when drawing array circuits, the fast detection pad, as a test connection point, often occupies a large area, resulting in limited space for signal line routing.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A fast-test display panel includes: a display panel body and a GOA circuit disposed on the display panel body. The display panel body has FPC bonding pads, and signal line bodies are connected between the FPC bonding pads and the GOA circuit. The FPC bonding pads are also connected to a main screen FPC. This application directly connects the signal line bodies to the FPC bonding pads. During testing, the main screen FPC connects to the test board, thereby illuminating the screen. Compared with existing technologies, this application eliminates the fast-test pad, effectively eliminating the problem of insufficient space for signal line routing caused by the large area occupied by the fast-test pad. This helps optimize the signal line layout, reduce the spacing and width of the traces, and thus reduce the risk of short circuits in the signal lines.

[0007] As an improvement of this utility model, the main body of the display panel has a display area and a non-display area, and the GOA circuit is located in the non-display area.

[0008] As an improvement of this utility model, the main screen FPC is connected to the test motherboard during testing, and the GOA circuit is connected to the test motherboard through the signal line body, the FPC bonding pad, and the main screen FPC.

[0009] As an improvement of this utility model, the main screen FPC is thermally pressed to connect the FPC bonding pads.

[0010] As an improvement of this utility model, the signal line body includes multiple parallel metal traces, and all the multiple metal traces are connected between the GOA circuit and the signal line body.

[0011] As an improvement of this utility model, the display panel body includes an upper polarizer, an upper substrate glass, a lower substrate glass, and a lower polarizer stacked from top to bottom.

[0012] As an improvement of this utility model, the FPC bonding pads are disposed on the lower substrate glass.

[0013] As an improvement of this utility model, the surface of the FPC bonding pad is provided with a gold plating layer.

[0014] As an improvement of this utility model, the main screen FPC is provided with a component area, and the main screen FPC is also provided with a protective film, which covers the component area.

[0015] As an improvement of this utility model, the protective film is a polyimide film.

[0016] Compared with the prior art, the embodiments of this utility model have the following main advantages:

[0017] To address the issue that in existing array circuit design, the fast test pad, used as a test connection point, often occupies a large area, resulting in limited space for signal line routing, this application directly connects the main body of the signal line to the FPC bonding pad. During testing, the main screen FPC is connected to the test board to illuminate the screen. Compared to existing technologies, this application eliminates the fast test pad, effectively eliminating the problem of insufficient space for signal line routing caused by the large area occupied by the fast test pad. This helps optimize the layout of the signal lines, reduce the spacing and width of the traces, and thus reduce the risk of short circuits in the signal lines. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the rapid test display panel provided in this application;

[0019] Figure 2 A partial structural schematic diagram of the rapid detection display panel provided in this application;

[0020] Figure 3 A schematic diagram of the rapid test display panel provided in this application during testing;

[0021] Figure 4 This is a schematic diagram of the structure of an existing rapid test display panel.

[0022] The image shows:

[0023] 1. Display panel body; 2. FPC bonding pads; 3. GOA circuit; 4. Signal line body; 5. Main screen FPC. Detailed Implementation

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The reference herein to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] As described in the background section, when drawing array circuits, the fast-detection pad, used as a test connection point, often occupies a large area (e.g., Figure 4 As shown, Figure 4 The feature marked at point B (Quick Test Pad) directly leads to limited space for signal line routing, which forces the spacing between lines to be reduced and the line width to be reduced as a result. These problems create hidden dangers in the subsequent screen manufacturing process, significantly increasing the risk of short circuits in signal lines and threatening production efficiency and yield.

[0026] To solve this technical problem, this utility model provides a fast detection display panel.

[0027] For details, please refer to Figures 1-2 The quick test display panel specifically includes:

[0028] The main body 1 of the display panel and the GOA circuit 3 set on the main body 1 of the display panel are provided with FPC bonding pads 2. The FPC bonding pads 2 and the GOA circuit 3 are connected by a signal line body 4, and the FPC bonding pads 2 are connected to the main screen FPC 5.

[0029] The fast test display panel provided by this utility model directly connects the signal line body 4 to the FPC bonding pad 2. During testing, the main screen FPC5 is connected to the test board to light up the screen. Compared with the prior art, this application eliminates the fast test pad, effectively eliminating the problem of insufficient routing space for the signal line body 4 caused by the large area occupied by the fast test pad. This helps to optimize the layout of the signal lines, reduce the spacing and width of the traces, and thus reduce the risk of short circuits in the signal lines.

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0031] It should be noted that, unless otherwise specified, the embodiments and features and technical solutions in the present invention can be combined with each other.

[0032] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0033] Embodiment 1 of the fast detection display panel of this utility model

[0034] Please refer to Figures 1-2 The present invention relates to a fast test display panel, comprising: a display panel body 1 and a GOA circuit 3 disposed on the display panel body 1. An FPC bonding pad 2 is disposed on the display panel body 1, and a signal line body 4 is connected between the FPC bonding pad 2 and the GOA circuit 3. The FPC bonding pad 2 is also connected to a main screen FPC 5. In this application, the signal line body 4 is directly connected to the FPC bonding pad 2. During testing, the main screen FPC 5 is connected to the test board to light up the screen. Compared with the prior art, this application eliminates the fast test pad, effectively eliminating the problem of insufficient trace space for the signal line body 4 due to the large area occupied by the fast test pad. This helps to optimize the layout of the signal line, reduce the trace spacing and line width, thereby reducing the risk of short circuit of the signal line.

[0035] Removing the fast test pad eliminates the problem of insufficient signal line routing space caused by its large footprint. In traditional designs, the fast test pad occupies a large panel space, which restricts the layout of signal lines and forces the spacing and width of the traces to be reduced. This increases the possibility of short circuits caused by mutual interference between signal lines. This design optimizes the layout of the main signal line 4, making the routing more reasonable and reducing the risk of short circuits.

[0036] Furthermore, the main body 1 of the display panel has a display area and a non-display area, with the GOA circuit 3 located in the non-display area, and the display area being... Figure 3As indicated by the label at point C; placing the GOA circuit 3 in the non-display area can make full use of the area on the main body of the display panel that was not previously effectively utilized, thereby improving space utilization.

[0037] Furthermore, during testing, the main screen FPC5 is connected to the test motherboard, and the GOA circuit 3 is connected to the test motherboard via the signal line body 4, the FPC bonding pad 2, and the main screen FPC5. Figure 3 The section marked A is the test motherboard. During testing, the gold fingers of the main screen FPC5 are connected to the interface on the test motherboard for testing. It should be noted that the technology of using the test motherboard to test the display panel is existing technology, and the test motherboard is also an existing structure, so this application will not elaborate further.

[0038] A complete connection path is constructed through the signal line body 4, FPC bonding pad 2, and main screen FPC 5, enabling the test motherboard to reliably communicate with key components such as the GOA circuit 3. During the testing process, the test motherboard can send various test signals to the display panel and obtain feedback information from the display panel, thereby comprehensively testing the various performance aspects of the display panel. This connection method is simple and direct, requiring no complex adapters, reducing the cost of testing equipment and the difficulty of testing operations. At the same time, the stable connection ensures the accuracy of signal transmission, reduces testing errors, and improves the reliability of test results.

[0039] Embodiment 2 of the fast detection display panel of this utility model

[0040] Furthermore, the quick-test display panel of this utility model features a thermo-press connection between the main screen FPC5 and the FPC bonding pad 2. This thermo-press connection allows the main screen FPC5 and the FPC bonding pad 2 to bond together, forming a robust physical connection. This connection method effectively reduces contact resistance, lowers signal loss during transmission, and ensures signal integrity and accuracy. In practical use, the display panel may be subjected to external forces such as vibration and bending. If the connection is not secure, it can easily lead to poor contact, affecting signal transmission and even causing display failure. The thermo-press connection, however, has high connection strength, can resist certain external forces, and ensures connection stability, thereby improving the product's durability and stability and reducing after-sales maintenance costs.

[0041] Furthermore, such as Figures 1-3As shown, the signal line body 4 includes multiple parallel metal traces, all of which connect the GOA circuit 3 and the signal line body 4. These parallel metal traces can transmit multiple signals simultaneously, greatly improving signal transmission efficiency. During the operation of the display panel, the GOA circuit 3 needs to frequently interact with other components, such as control signals and data signals. The design of multiple parallel metal traces allows for the simultaneous transmission of these different types of signals, reducing congestion and delay in signal transmission. This enables the display panel to respond to various operation commands more quickly, improving its response speed and performance. Furthermore, parallel traces enhance signal transmission reliability; even if one trace fails, the others can continue to transmit signals, ensuring the normal operation of the display panel. The metal traces can be made of copper.

[0042] Furthermore, the display panel body 1 includes an upper polarizer, an upper substrate glass, a lower substrate glass, and a lower polarizer stacked sequentially from top to bottom. The upper polarizer and the lower polarizer can precisely control the polarization direction of light, enabling the display panel body 1 to present a clear and vivid image. The upper substrate glass and the lower substrate glass provide stable support and reliable encapsulation for display media such as liquid crystals, ensuring the normal operation of the display media. The reasonable stacking of these components constitutes a complete display structure.

[0043] Furthermore, the FPC bonding pad 2 is disposed on the lower substrate glass. Disposing the FPC bonding pad 2 on the lower substrate glass facilitates direct connection with the main screen FPC 5, etc. In the production process of display panels, wiring is a critical step. Complex wiring not only increases production costs but also easily leads to wiring errors and signal interference. Disposing the FPC bonding pad 2 on the lower substrate glass makes the wiring simpler and clearer, reducing wiring difficulty and cost.

[0044] Furthermore, the surface of the FPC bonding pad 2 is coated with a gold layer. The gold layer has good conductivity and corrosion resistance. The good conductivity can effectively reduce the contact resistance between the FPC bonding pad 2 and the main screen FPC 5, reduce energy loss and signal attenuation during signal transmission, and ensure that the signal can be transmitted accurately and stably. The corrosion resistance can reduce the oxidation and corrosion of the FPC bonding pad 2. Especially in harsh environments such as humidity and high temperature, the gold layer can protect the FPC bonding pad 2, reduce the erosion of the external environment, and extend the service life of the FPC bonding pad 2. In addition, the stable connection and good corrosion resistance also improve the product's resistance to environmental interference, enabling the display panel to work normally in a wider range of environmental conditions, improving the product's applicability and reliability.

[0045] Embodiment 3 of the rapid detection display panel of this utility model

[0046] Furthermore, the fast-test display panel of this utility model has a component area on the main screen FPC5, and a protective film is also provided on the main screen FPC5, covering the component area. In actual use, the components on the main screen FPC5 are easily affected by external environmental factors. The protective film can isolate and block external factors from damaging the components. At the same time, the protective film can also reduce mechanical damage to the components during transportation and assembly, ensuring the integrity and reliability of the components. By protecting the components, the product failure rate is reduced, after-sales maintenance costs are reduced, and the product's market competitiveness is improved.

[0047] Furthermore, such as Figure 1 As shown, the protective film is a polyimide film. The high insulation of the polyimide film can effectively reduce the occurrence of leakage current, thereby reducing component damage and safety accidents caused by leakage current. Its excellent heat resistance allows the protective film to maintain stable performance in high-temperature environments, without deforming or losing its protective function due to temperature rise, ensuring the normal operation of components in high-temperature environments. Its good chemical stability enables it to resist the corrosion of various chemical substances, further improving the service life and protective effect of the protective film. In addition, the polyimide film also has a certain degree of flexibility, which can adapt to bending and folding operations of the main screen FPC5, thus providing strong support for the miniaturization and foldable design of the display panel.

[0048] Obviously, the embodiments described above are only some embodiments of this utility model, not all embodiments. The accompanying drawings show preferred embodiments of this utility model, but do not limit the patent scope of this utility model. This utility model can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this utility model. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this utility model specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the patent protection scope of this utility model.

Claims

1. A quick-detection display panel, characterized in that, include: The display panel body (1) and the GOA circuit (3) set on the display panel body (1) are provided with FPC bonding pads (2). A signal line body (4) is connected between the FPC bonding pads (2) and the GOA circuit (3), and the FPC bonding pads (2) are connected to the main screen FPC (5).

2. The quick inspection display panel according to claim 1, characterized in that, The main body of the display panel (1) has a display area and a non-display area, and the GOA circuit (3) is located in the non-display area.

3. The quick inspection display panel according to claim 1 or 2, characterized in that, The main screen FPC (5) is connected to the test motherboard during testing, and the GOA circuit (3) is connected to the test motherboard through the signal line body (4), the FPC bonding pad (2) and the main screen FPC (5).

4. The quick detection display panel according to claim 3, characterized in that, The main screen FPC (5) is thermally bonded to the FPC bonding pad (2).

5. The fast inspection display panel according to claim 4, characterized in that, The signal line body (4) includes multiple parallel metal traces, and all of the multiple metal traces are connected between the GOA circuit (3) and the signal line body (4).

6. The fast inspection display panel according to claim 5, characterized in that, The main body of the display panel (1) includes an upper polarizer, an upper substrate glass, a lower substrate glass and a lower polarizer stacked from top to bottom.

7. The fast inspection display panel according to claim 6, characterized in that, The FPC bonding pads (2) are disposed on the lower substrate glass.

8. The quick inspection display panel according to claim 7, characterized in that, The FPC bonding pad (2) has a gold plating layer on its surface.

9. The fast inspection display panel according to claim 8, characterized in that, The main screen FPC (5) is provided with a component area, and the main screen FPC (5) is also provided with a protective film, which covers the component area.

10. The fast inspection display panel according to claim 9, characterized in that, The protective film is a polyimide film.

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