Layout structure of four-bit synchronous add-subtract binary counter

By centrally setting up the counting module and optimizing signal routing in the counter layout structure, the challenges of miniaturization and low cost of counter products are solved, resulting in smaller chip size and lower production costs, while improving the stability and flexibility of signal transmission.

CN224152971UActive Publication Date: 2026-04-21BEIJING YANDONG MICROELECTRONICS
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Patent Information

Application Number
CN202521023398.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-05-22
Publication Date
2026-04-21
Estimated Expiration
2035-05-22

AI Technical Summary

Technical Problem

In the existing technology, counter products are insufficient in terms of miniaturization and reduced production costs, making it difficult to simultaneously meet the requirements of electronic systems or devices for miniaturized components and low cost.

Method used

A layout structure for a four-bit synchronous binary up-and-down counter is provided. The counting module is centrally located at the center of the layout structure, and the input/output ports are arranged around the edge to form a divergent layout centered on the counting module. This optimizes signal routing, reduces unnecessary interconnections, and uses CMOS technology.

Benefits of technology

This has enabled smaller chip and package sizes for counter products, while reducing manufacturing costs and improving the stability and flexibility of signal transmission.

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Abstract

The utility model provides a layout structure of a four-bit synchronous add-subtract binary counter, which comprises a first area, a second area and a third area, the second area surrounds the third area, and the first area surrounds the second area. The first area is provided with an input port and an output port; the second area comprises a first functional area, a second functional area and an addition and subtraction control module; and the third area comprises a third functional area and an overflow control module. The first functional area is provided with a multi-stage output driving module which is used for receiving an output signal from the third functional area and transmitting the output signal to the output port after enhancing the driving of the output signal; the second functional area is provided with an input stage module and a setting control module, and is used for receiving an input signal from the input port and transmitting the input signal to the third functional area; the third function area is provided with a counting module, a clock control module and a three-state control module. A counter product adopting the layout structure has a smaller chip size and a smaller packaging size, and the production and manufacturing cost is lower.
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