Layout structure of four-bit synchronous add-subtract binary counter
By centrally setting up the counting module and optimizing signal routing in the counter layout structure, the challenges of miniaturization and low cost of counter products are solved, resulting in smaller chip size and lower production costs, while improving the stability and flexibility of signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BEIJING YANDONG MICROELECTRONICS
- Filing Date
- 2025-05-22
- Publication Date
- 2026-04-21
AI Technical Summary
In the existing technology, counter products are insufficient in terms of miniaturization and reduced production costs, making it difficult to simultaneously meet the requirements of electronic systems or devices for miniaturized components and low cost.
A layout structure for a four-bit synchronous binary up-and-down counter is provided. The counting module is centrally located at the center of the layout structure, and the input/output ports are arranged around the edge to form a divergent layout centered on the counting module. This optimizes signal routing, reduces unnecessary interconnections, and uses CMOS technology.
This has enabled smaller chip and package sizes for counter products, while reducing manufacturing costs and improving the stability and flexibility of signal transmission.
Smart Images
Figure CN224152971U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design technology, specifically to a layout structure of a four-bit synchronous binary counter. Background Technology
[0002] Counters are integrated circuit products used to implement counting logic functions and are diverse in type and application. Counters primarily count the number of pulses to perform various functions such as counting, measurement, frequency division, timing, generating clock pulse sequences, and performing mathematical operations. Their applications are very broad. For example, in the controller of an electronic computer, they count instruction addresses to sequentially fetch the next instruction; in the arithmetic logic unit (ALU), they record the number of additions and subtractions during multiplication and division operations, and so on.
[0003] A counter consists of a basic counting unit and some control gates. The counting unit is composed of a series of flip-flops with information storage functions, including RS flip-flops, T flip-flops, D flip-flops, and JK flip-flops.
[0004] Counters can be classified into synchronous counters and asynchronous counters based on whether the flip-flops in the counters toggle simultaneously. They can also be classified into up counters, down counters, and reversible counters based on whether the digits increment or decrement during counting. Up counters increment with the clock signal, down counters decrement, and reversible counters can both increment and decrement. Furthermore, counters can be classified according to their counting base, such as binary counters and decimal counters.
[0005] As people's demand for the multifunctionality and portability of electronic systems or devices gradually increases, new and higher requirements are constantly being put forward for the miniaturization of electronic components that make up electronic systems or devices. At the same time, the pursuit of product cost-effectiveness is also constantly prompting manufacturers to reduce the production and manufacturing costs of products while ensuring product performance. For example, smaller chip size and smaller packaging form to enhance the flexibility and adaptability of product applications. Utility Model Content
[0006] In order to provide at least a miniaturized, low-cost counter product, embodiments of this application provide a layout structure of a four-bit synchronous addition and subtraction binary counter, the layout structure including a first region, a second region and a third region, the second region surrounding the third region, and the first region surrounding the second region.
[0007] The first area is equipped with multiple input ports and multiple output ports; the second area includes multiple first function areas, multiple second function areas, and an addition / subtraction control module; the third area includes multiple third function areas and an overflow control module.
[0008] The first functional area is equipped with a multi-level output driver module, which is used to receive the output signal from the third functional area, amplify the output signal, and transmit it to the output port; the second functional area is equipped with an input stage module and a set control module, which are used to receive the input signal from the input port and transmit the input signal to the third functional area; the third functional area is equipped with a counting module, a clock control module, and a three-state control module.
[0009] Optionally, the first area is provided with multiple sets of ESD protection structures and multiple sets of output stage MOSFET groups; the ESD protection structures are connected to the input ports; the output stage MOSFET groups surround the output ports.
[0010] Optionally, the first region has a first side and a third side opposite to each other along a first direction, and a second side and a fourth side opposite to each other along a second direction; the first side is provided with a grounding port, and the second side is provided with a power supply port, both of which are connected to the ESD protection structure.
[0011] Optionally, multiple output ports are provided, specifically including a four-bit parallel output port and an overflow output port; the four-bit parallel output port is located on the second side, and the overflow output port is located on the fourth side; multiple first functional areas are connected adjacent to the multiple output ports in a one-to-one correspondence.
[0012] Optionally, at least one input port is positioned between the four parallel output ports, such that the four parallel output ports are divided into two groups.
[0013] Optionally, the first functional area is equipped with a three-level output driver module, with the driving strength of the three-level output driver module increasing progressively.
[0014] Optionally, multiple input ports are provided, specifically including a four-bit parallel input port, a set control port, a clock control port, a tri-state control port, and an increment / decrement control port; the tri-state control port and the increment / decrement control port are located on the second side, and the set control port and the clock control port are located on the fourth side; at least three of the four-bit parallel input ports are respectively located at the three corners of the layout structure; multiple second functional areas are connected adjacent to the four-bit parallel input ports in a one-to-one correspondence.
[0015] Optionally, the addition / subtraction control module is adjacent to the tri-state control port and the addition / subtraction control port.
[0016] Optionally, at least one output port is located between the set control port and the clock control port.
[0017] Optionally, multiple third functional areas are arranged along the first direction, and the overflow control module is located at one end of the third area along the first direction.
[0018] In summary, the layout structure of the four-bit synchronous binary counter provided in this application embodiment centrally positions the counting module at the center of the layout structure and arranges input / output ports (PADs) around the edge of the layout structure, forming a divergent layout centered on the counting module. This optimizes signal routing and achieves the best performance-to-area ratio, resulting in counter products using this layout structure having smaller chip size and smaller package size, and lower manufacturing costs. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.
[0020] Figure 1 This is a schematic diagram of the layout structure of a four-bit synchronous up-and-down binary counter provided in an embodiment of this application;
[0021] Figure 2 This is a schematic diagram of the logic of each module of the four-bit synchronous binary counter provided in the embodiments of this application;
[0022] Figure 3 This is a schematic diagram of the external pin arrangement of the four-bit synchronous up-and-down binary counter provided in an embodiment of this application;
[0023] Figure 4 This is a schematic diagram of the modules inside the first functional area in the layout structure of the four-bit synchronous binary counter provided in this application embodiment;
[0024] Figure 5 This is a schematic diagram of the modules inside the second functional area in the layout structure of the four-bit synchronous binary counter provided in this application embodiment;
[0025] Figure 6 This is a schematic diagram of the modules inside the third functional area in the layout structure of the four-bit synchronous binary counter provided in this application embodiment.
[0026] The image is labeled as follows:
[0027] 01: Area 1, 02: Area 2, 03: Area 3;
[0028] 110: Input port, 120: Output port, 130: Power supply port, 140: Ground port;
[0029] 210: First functional area; 220: Second functional area; 230: Addition / subtraction control module;
[0030] 310: Third functional area; 320: Overflow control module;
[0031] P0 to P3: These are four-bit parallel input ports, respectively;
[0032] CP: Clock control port, PLb: Set control port, CEb: Tri-state control port, UD: Add / subtract control port;
[0033] VCC: Power supply port, GND: Ground port;
[0034] Q0 to Q3: These are four parallel output ports respectively;
[0035] RCb and TC: These are two overflow output signal ports, respectively. Detailed Implementation
[0036] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete. The same reference numerals denote the same objects throughout the drawings.
[0037] In the specification of this application, when a region / functional area / module is referred to as being "connected to" other regions / functional areas / modules, such as "connected to" other regions / functional areas / modules, the region / functional area / module can be directly connected to or directly coupled to other regions / functional areas / modules, or there may be an intervening third region / functional area / module; in addition, in the embodiments of this application, "connection" mainly refers to electrical connection, and "adjacent" or "adjacent" means that two regions are connected to each other, or that two regions are directly close to each other (excluding a third party) and separated by a preset distance.
[0038] This application defines "first direction" and "second direction" as reference directions. The above definitions are for the purpose of more accurately disclosing the technical solutions of this application and do not constitute a limitation on this application. It should be understood that in the embodiments of this application, descriptions such as "along the first direction" or "along the second direction" include both the setting and arrangement along the positive direction and the setting and arrangement along the negative direction.
[0039] exist Figure 1 In the diagram, the bracketed label used to represent a functional area, such as P0 in 220(P0), indicates the specific port corresponding to that functional area; the functional area is electrically connected to the corresponding port and can output signals to the corresponding port or receive signals from the corresponding port.
[0040] In order to improve the deficiencies in the aforementioned prior art, this application provides an overall layout structure for a four-bit synchronous up-and-down binary counter based on CMOS (Complementary Metal Oxide Semiconductor) technology by reasonably arranging its layout structure, while realizing the necessary functions of the counter product.
[0041] To provide a more complete disclosure of the embodiments of this application, the module architecture and working principle of a four-bit synchronous binary counter are described below.
[0042] like Figure 2 As shown, the four-bit synchronous binary counter includes an input port, an output port, an input module, an output module, a counting module, and multiple control modules.
[0043] The input module is used to preprocess the input signals from the input port, such as four-position signals, to avoid signal instability or the input signals being affected by electrostatic interference; the output module is used to improve the driving capability of the output signal and ensure the stability of the output signal.
[0044] The counting module is the core module of the counter product. For a four-bit counter, the counting module consists of four master-slave flip-flops and corresponding combinational logic circuits. It is controlled by the control module and can perform core functions such as counting, storage, and output.
[0045] The control module receives control signals from the input port and transmits them to the counting module to control it. The counter product has four control modules: a clock control module, an increment / decrement control module, a three-state control module, and a set control module. Each module operates independently, which improves stability and enables the implementation of predetermined functions.
[0046] Considering that the counting module has the most complex logic structure and the most wiring, requiring a large layout space, in the layout structure provided in this application embodiment, each counting module is placed centrally in the layout.
[0047] All input and output ports comply with general requirements for external leads or relevant specifications, such as... Figure 3 The package pins are arranged in a ring around the edge of the layout structure; to reduce the complexity of the leads and the trace distance, the input and output modules are set to be close to the corresponding input and output ports to avoid the impact of long-distance leads on signal transmission speed and stability; the position of each control module is set by balancing the connection distance between it and the input port and the counting module.
[0048] As mentioned above, the layout structure provided in this application embodiment is constructed with the counting module as the core, and the remaining modules are arranged around the counting module, ultimately forming the layout shown below. Figure 1 The layout structure shown.
[0049] Specifically, such as Figure 1 As shown, the layout structure includes:
[0050] The three regions, namely the first region 10, the second region 20, and the third region 30, are nested in layers from the outside in. Each region is separated by the dotted lines shown in the figure. The second region 20 surrounds the third region 30, and the first region 10 surrounds the second region 20.
[0051] like Figure 1 As shown, the first region 10 is set close to the edge of the layout structure (i.e. the chip edge), and the second region 20 is set between the first region 10 and the third region 30. Generally speaking, both the first region 10 and the second region 20 are ring-shaped.
[0052] The first area 10 is provided with multiple input ports (input pads, input PADs) 110 and multiple output ports (output pads, PADs) 120.
[0053] The second area 20 is further divided into multiple first functional areas 210, multiple second functional areas 220, and an independently set addition and subtraction control module 230.
[0054] The third area 30 is further divided into multiple third functional areas 310 and a separately configured overflow control module 320.
[0055] like Figure 4 As shown, the first functional area 210 is provided with a multi-level output driver module, which is used to receive the output signal from the third functional area 310, and amplify and drive the output signal before transmitting it to the output port 120, so as to provide a stable and effective output signal to the output port 120.
[0056] like Figure 4 As shown, within the first functional area 210, the area occupied by the multi-level output drive module increases progressively.
[0057] like Figure 5 As shown, the second functional area 220 is provided with an input module and a set control module, which are used to receive input signals from the input port 110 and transmit the input signals to the third functional area 310; typically, the aforementioned input signals specifically include parallel input four-position set data signals and various control (enable) signals, such as clock control signals, set control signals, tri-state control signals and addition / subtraction control signals.
[0058] like Figure 6As shown, the third functional area 310 is equipped with a counting module, a clock control module, and a three-state control module.
[0059] In a typical embodiment, such as Figure 1 As shown, the first region 10 is equipped with multiple sets of ESD protection structures and multiple sets of output stage MOSFETs. The ESD protection structures are connected to the input port 110; the output stage MOSFETs surround the aforementioned output port 120.
[0060] The output stage MOS transistor group, composed of multiple MOS transistors, is used to improve the driving capability of the output signal. Specifically, it includes output stage PMOS / NMOS transistors, and the output port 110 is surrounded by output stage PMOS and output stage NMOS transistors.
[0061] ESD protection structures include, for example, equivalent diode structures, which isolate power, ground, and input / output signals to prevent electrostatic discharge from damaging the device.
[0062] In the aforementioned embodiments, the equivalent diode structure in the ESD protection structure is reverse-connected to the ground terminal, that is, the positive terminal of the equivalent diode structure is connected to the ground terminal, and the negative terminal is connected to the corresponding input port 110. In a typical embodiment, the ESD protection structure is located below the corresponding input port 110. After the signal enters the chip through the port, it first passes through the ESD protection structure and then enters the input module (located in the second functional area 220) connected to the port. When electrostatic discharge is applied to the input port, the ESD protection structure can discharge a large amount of charge generated by electrostatic discharge to the ground wire before the input module, preventing excessive charge from directly impacting the internal devices of the input module, thus enabling the chip to have a certain anti-electrostatic discharge capability.
[0063] like Figure 1 As shown, in the embodiment, the first region 10 has a first side (right side) and a third side (left side) opposite each other along a first direction (lateral direction), and a second side (lower side) and a fourth side (upper side) opposite each other along a second direction (longitudinal direction).
[0064] From another perspective, the first region 10 has the first to fourth sides arranged clockwise.
[0065] A grounding port 140 is provided on the first side and a power port 130 is provided on the second side. Both the power port 130 and the grounding port 140 can be connected to the aforementioned ESD protection structure to avoid the impact of power voltage fluctuations or surges on the internal modules of the chip.
[0066] The ESD protection structure connected to the power port 130 specifically includes a MOS structure separately set under the power port 130, which constitutes a reverse diode structure between the power port 130 and the ground terminal.
[0067] In an optional embodiment, the power port 130 and the ground port 140 are respectively located at the middle position of their respective sides. In other words, the line connecting the power port 130 and the ground port 140 constitutes the center line of the layout structure along the first direction.
[0068] In the layout structure provided in the embodiment, the positions of the input module, output module, and various control modules required for the counter to operate are reasonably arranged as follows:
[0069] The input module of the counter is built into the second functional area 220. Multiple second functional areas 220 are distributed on the side of the second area 20 near the fourth side. They are used to preprocess the set data signals from the four-bit parallel input ports P0, P1, P2, and P3, and play the role of filtering and reducing interference.
[0070] The counter's output module consists of multiple multi-stage output drive modules built into the first functional area 210. Furthermore, it may include output stage PMOS and NMOS transistors surrounding the corresponding output ports 120 in the first area 10, collectively forming the output module. The first functional area 210 for setting (partial) output modules follows a proximity principle, placing them near the corresponding output ports 120 to reduce unnecessary wiring and improve the driving capability of the output signals.
[0071] In the aforementioned control module, the set control module is controlled by the set control signal from the set control port PLb, such as... Figure 5 As shown, the set control module is also built into the second functional area 220 to implement the asynchronous set function. The four set input ports PLB are independent of each other, and the second functional areas 220 of the four set control modules are also independent of each other. When the set control signal is valid, the counting module reads the set data signal from the four parallel input ports P0, P1, P2, and P3, and performs the set.
[0072] Among the aforementioned control modules, such as Figure 1 As shown, the addition / subtraction control module 230 is separately located in the lower center of the layout, specifically in the lower center of the second region 20. The addition / subtraction control module 230 is adjacent to the corresponding addition / subtraction control port UD and the tri-state control port CEb. Based on the addition / subtraction control signal input to the addition / subtraction control port UD, the addition / subtraction control module 230 controls the addition / subtraction operation state of the counting module. It achieves addition / subtraction switching through the logic processing of the addition / subtraction control signal and internal circuitry, allowing for free switching of modes that takes effect in the next counting clock cycle, making the counter product more flexible and adaptable to various application environments.
[0073] The third region 30 is the core part of the entire layout structure. In the embodiment, the third region 30 is provided with four third functional areas 310 and additional logic processing circuits.
[0074] The third functional area 310 houses a built-in counting module, clock control module, and tri-state control module, located at the center of the layout, all connected via metal wiring. Among them, such as... Figure 2 As shown, the counting module consists of four distributed master-slave flip-flops and corresponding combinational logic circuits. It is controlled by each control module and can perform the core functions of the product, such as counting, storage, and output.
[0075] like Figure 6 As shown, the three-state control module is built into the third functional area 310. This module controls the high-impedance output of the counter based on the three-state enable signal from the three-state control port CEb. When the aforementioned three-state enable signal is valid, the output port of the counter outputs a signal normally. When the aforementioned three-state enable signal is invalid (i.e., disabled), the output ports Q0 to Q3 and the overflow output signal port RCb are directly set to a high-impedance state, so that the output of the counter is invalid.
[0076] like Figure 6 As shown, the clock control module is also built into the third functional area 310. This module controls the counting frequency of the counting module through the clock signal from the clock control port CP.
[0077] In this embodiment, the counting module is independent of other control modules, which means that when no counting occurs, the contents of its internal counter are independent of the input of the tri-state control port CEb / addition / subtraction control port UD.
[0078] The overflow control module 320 is located on the right side of the third area 30. This module involves a wide variety of signal sources, including four output signals (Q0 to Q3) provided by the four third functional areas 310 respectively, as well as all control signals (CP, UD, CEb) except for the set control signal (PLb). It is mainly composed of combinational logic circuits and a large number of cross traces, and is responsible for generating the signals output by the two overflow output ports RCb and TC.
[0079] The signal output by the overflow output port TC is determined by the output states of Q0 to Q3 and the input state of the addition / subtraction control port UD; the overflow output port RCb is also controlled by the tri-state and clock control modules. The aforementioned TC and RCb ports are generally used to implement custom counting or status monitoring, and their different logics can meet the counting or wiring requirements in complex environments.
[0080] Specifically, when the input state of the addition / subtraction control port UD is in the addition state, and when the output states of Q0 to Q3 are 1, 1, 1, 1, the overflow output port TC outputs a high level; when the input state of the addition / subtraction control port UD is in the subtraction state, and when the output states of Q0 to Q3 are 0, 0, 0, 0, the overflow output port TC outputs a high level; the overflow output port TC can be used as an overflow flag after completing one count and can be used for cascading (i.e., providing a rising edge clock when the count is full).
[0081] Furthermore, since the overflow output port RCb is controlled by the clock signal within a single cycle, its pulse width is generally only half that of the TC port.
[0082] In the embodiment, the TC port has the characteristics of high speed and stable response, and can respond quickly and effectively when changing the number of counting bits; while RCb is slightly delayed than TC because it is additionally controlled by the tri-state CEb and the clock CP. However, since the general clock is a square wave signal (or pulse signal), using RCb as the output port for logic processing can effectively avoid problems such as edge collision caused by state switching. At the same time, being controlled by CEb makes it easier to protect the circuit or bus structure, and the reliability is higher.
[0083] In a typical embodiment, such as Figure 1 As shown, there are multiple output ports 120, specifically including four parallel output ports Q0, Q1, Q2, Q3 and overflow output ports RCb and TC.
[0084] The aforementioned four parallel output ports are located on the second side of the first region 10, and the overflow output ports RCb and TC are located on the fourth side.
[0085] In an alternative embodiment, the overflow output ports RCb and TC are located in a more central position on the fourth side.
[0086] like Figure 1 As shown, multiple first functional areas 210 are connected to multiple output ports 120 in a one-to-one correspondence. Specifically, multiple first functional areas 210(Q0), 210(Q1), 210(Q2), 210(Q3), 210(RCb), and 210(TC) are respectively connected to output ports Q0, Q1, Q2, Q3, RCb, and TC.
[0087] In an optional embodiment, at least one input port 110 is disposed between the four parallel output ports Q0 and Q3, such that the four parallel output ports are divided into two groups, typically, as shown below. Figure 1 As shown, the three-state control port CEb and the addition / subtraction control port UD are set between the four-bit parallel output ports Q0 to Q3, dividing the four-bit parallel output ports into Q1 and Q0 on the left and Q2 and Q3 on the right.
[0088] In a typical embodiment, such as Figure 4 As shown, the first functional area 210 is equipped with a three-level output drive module, and the drive strength of the three-level output drive module increases progressively.
[0089] In this embodiment, multiple input ports 110, such as Figure 1 As shown, it specifically includes four parallel input ports P0, P1, P2, and P3 for inputting four-position bit data, and also includes multiple control ports, namely the set control port PLb, the clock control port CP, the tri-state control port CEb, and the addition / subtraction control port UD.
[0090] like Figure 1 As shown, the tri-state control port CEb and the addition / subtraction control port UD are located on the second side of the first region 10, while the set control port PLb and the clock control port CP are located on the fourth side.
[0091] At least three of the four parallel input ports are located at the three corners of the layout structure; for example, Figure 1 As shown, P1 is set in the lower left corner, P0 is set in the upper left corner, and P3 is set in the upper right corner.
[0092] like Figure 1 As shown, multiple second functional areas 220(P0), 220(P1), 220(P2), and 220(P3) are connected adjacent to the four parallel input ports P0, P1, P2, and P3 in a one-to-one correspondence.
[0093] like Figure 1 As shown, the addition / subtraction control module 230 is adjacent to the tri-state control port CEb and the addition / subtraction control port UD, and the addition / subtraction control module 230 is located in the middle of the lower side of the second region 20.
[0094] In an embodiment, at least one output port 120 is located between the set control port PLb and the clock control port CP, typically, as shown below. Figure 1 As shown, the two overflow output ports RCb and TC are located between the set control port PLb and the clock control port CP.
[0095] In a typical embodiment, such as Figure 1 As shown, multiple third functional areas 310 are arranged along the first direction, that is, sequentially arranged horizontally in the figure. The overflow control module 320 is located at one end of the third area 30 along the first direction, so as to... Figure 1 As shown in the example, the overflow control module 320 is located at the right end of the overall third functional area 310.
[0096] In the foregoing embodiments, the arrangement of the input ports 110 and output ports 120 at the edge of the layout structure enables the chip using this layout structure to be adapted to... Figure 3 The package shown allows for shorter connections between each package pin and its corresponding chip port (PAD) and avoids crossing.
[0097] In alternative embodiments, such as Figure 1 As shown, there are four third functional areas 310, which process the logic of output signals Q0 to Q3 respectively. Therefore, the four third functional areas 310 correspond to and are adjacent to the four first functional areas 210(Q0), 210(Q1), 210(Q2), and 210(Q3).
[0098] The other two first functional areas 210(RCb) and 210(TC) are connected to the overflow control module 320.
[0099] In this embodiment, the addition / subtraction control module 230 is used to process both the input addition / subtraction control signal UD and the tri-state control signal CEb. The input module corresponding to the set control signal PLb is located on the left side of 220 (P2 / P3) in the figure, but is not shown in the figure. After passing through the aforementioned input module, the set control port PLb is connected to the set control module in each of the second functional areas 220 and participates in the basic enable logic processing.
[0100] The following is an example of the specific workflow of a counter chip product using the aforementioned layout structure:
[0101] Arranged according to the logical priority of the counter, the set function is executed first. A set of four-bit binary data, i.e., the set data signal, is input to the four parallel input ports P0 to P3. The set control module located in the second functional area 220 controls the above set data signal according to the received set control signal. If the input of the set control port PLb is L (low level, the same below), the set is executed, the circuit stops working, and the data output by the counter output ports Q0 to Q3 is consistent with the aforementioned set data signal; if the input of the set control port PLb is H (high level, the same below), the function is not executed, and the counter works normally.
[0102] Subsequently, the tri-state control module located in the third functional area 310 becomes active. This module is controlled by the input signal of the tri-state control port CEb. When the input of the tri-state control port CEb is H, the circuit stops working, the counting module will stop counting, and the output data of the output ports Q0 to Q3 will be held. If it is L, the circuit will operate normally.
[0103] Subsequently, the counter begins normal counting. When the clock control port CP receives a rising edge signal, the counting module starts counting. The addition / subtraction control module located in the second region 20 operates. When the addition / subtraction control port UD receives an H signal, the circuit is in addition mode, sequentially transmitting signals and performing addition counting. When the addition / subtraction control port UD receives an L signal, it performs subtraction counting. Simultaneously, the overflow output signal port TC detects and holds or changes the output signal. When the clock control port CP receives a falling edge signal, the overflow output signal port RCb detects and holds or changes the output signal until the next rising edge of the clock, completing one cycle.
[0104] It should be understood that the specific circuit structure or semiconductor structure of the aforementioned "modules" and "functional areas" can be determined by those skilled in the art based on the functional description of the "module" and "functional area". Due to space limitations, the specific structural features of the "module" and "functional area" are not described in detail in this embodiment, nor are they limited, as long as the required function can be achieved.
[0105] In summary, the layout structure of the four-bit synchronous binary counter provided in this application embodiment centrally positions the counting module at the center of the layout structure and arranges input / output ports (PADs) around the edge of the layout structure, forming a divergent layout centered on the counting module. This optimizes signal routing and achieves the best performance-to-area ratio, resulting in counter products using this layout structure having smaller chip size and smaller package size, and lower manufacturing costs.
[0106] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A layout structure of a four-bit synchronous up-down binary counter, characterized by, It includes a first region (10), a second region (20) and a third region (30), wherein the second region (20) surrounds the third region (30) and the first region (10) surrounds the second region (20); The first area (10) is provided with multiple input ports (110) and multiple output ports (120); the second area (20) includes multiple first functional areas (210), multiple second functional areas (220) and an addition / subtraction control module (230); the third area (30) includes multiple third functional areas (310) and an overflow control module (320); in: The first functional area (210) is provided with a multi-level output driving module, which is used to receive the output signal from the third functional area (310), and transmit the output signal to the output port (120) after amplification and driving. The second functional area (220) is provided with an input level module and a position control module, which are used to receive input signals from the input port (110) and transmit the input signals to the third functional area (310); The third functional area (310) is equipped with a counting module, a clock control module and a three-state control module.
2. The layout structure of claim 1, wherein, The first region (10) is provided with multiple sets of ESD protection structures and multiple sets of output stage MOS transistor groups; The ESD protection structure is connected to the input port (110); The output stage MOS transistor group is arranged to surround the output port (120).
3. The layout structure of claim 2, wherein, The first region (10) has a first side and a third side opposite to each other along a first direction, and a second side and a fourth side opposite to each other along a second direction; The first side is provided with a grounding port (140), and the second side is provided with a power port (130). Both the power port (130) and the grounding port (140) are connected to the ESD protection structure.
4. The layout structure of claim 3, wherein, The plurality of output ports (120) specifically include a four-bit parallel output port and an overflow output port; The four-bit parallel output port is located on the second side, and the overflow output port is located on the fourth side; The plurality of first functional areas (210) are arranged adjacent to the plurality of output ports (120) in a one-to-one correspondence.
5. The layout structure according to claim 4, characterized in that, At least one of the input ports (110) is disposed between the four parallel output ports, such that the four parallel output ports are divided into two groups.
6. The layout structure according to any one of claims 1 to 5, wherein, The first functional area (210) is provided with a three-level output drive module, and the drive intensity of the three-level output drive module increases step by step.
7. The layout structure of claim 3, wherein, The multiple input ports (110) specifically include a four-bit parallel input port, a set control port, a clock control port, a tri-state control port, and an addition / subtraction control port; The tri-state control port and the addition / subtraction control port are located on the second side, and the set control port and the clock control port are located on the fourth side; At least three of the four parallel input ports are respectively located at the three corners of the layout structure; The plurality of second functional areas (220) are arranged adjacent to each of the four parallel input ports in a one-to-one correspondence.
8. The layout structure of claim 7, wherein, The add-subtract control module (230) is adjacent to the three-state control port and the add-subtract control port.
9. The layout structure of claim 7, wherein, At least one of the output ports (120) is disposed between the set control port and the clock control port.
10. The layout structure of any one of claims 3-5, 7, 8, wherein, The plurality of third functional areas (310) are arranged along a first direction, and the overflow control module (320) is disposed at one end of the third area (30) along the first direction.