Fault online injection device
By designing an online fault injection device, the problems of cumbersome operation and insufficient accuracy of traditional fault testing methods are solved. It enables online fault injection and signal monitoring for multiple interfaces, thereby improving testing efficiency and accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHENGDU CHANGBO INSTR CO LTD
- Filing Date
- 2025-04-28
- Publication Date
- 2026-04-28
AI Technical Summary
Traditional fault testing methods are cumbersome to operate, affect the accuracy of test results, and cannot meet the modern demand for efficient and accurate multi-interface fault testing.
Design an online fault injection device, including a host and a fault injection component, with 1553B, RS422, digital and discrete fault injection functions, and realize online fault injection and monitoring of interface signals through an embedded hardware system.
It enables online fault injection and signal monitoring of multiple interfaces without disrupting system connections, improving testing efficiency and accuracy.
Smart Images
Figure CN224176960U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of interface fault simulation technology, and more specifically to an online fault injection device. Background Technology
[0002] In the research, development, production, and maintenance of electronic equipment, fault testing of communication and electrical signal interfaces is a crucial step in ensuring equipment reliability and stability. Traditional fault testing methods often require disconnecting the system, which is cumbersome and may affect the accuracy of test results, failing to meet the demands of modern, efficient, and precise testing. With the continuous development of communication technology and electronic equipment, the requirements for interface fault testing are becoming increasingly stringent. Therefore, providing an online fault injection device that can inject various interface faults without disrupting existing system connections, and also possess signal monitoring and simulation training functions, is a problem that urgently needs to be solved by those skilled in the art. Utility Model Content
[0003] In view of this, the present invention provides an online fault injection device, which solves the problems of cumbersome operation, affecting the accuracy of test results, and failing to meet the testing requirements of various interfaces in existing fault testing methods. It realizes online fault injection and signal monitoring functions for various interfaces, thereby improving testing efficiency and accuracy.
[0004] To achieve the above objectives, the present invention adopts the following technical solution: an online fault injection device, comprising: a host and a fault injection component;
[0005] The host computer controls and manages the fault injection component;
[0006] The fault injection components include: a 1553B fault injection component, an RS422 fault injection component, a digital fault injection component, and a discrete fault injection component, which are used to provide 1553B bus fault injection, RS422 bus fault injection, digital fault injection, and discrete fault injection, respectively.
[0007] Preferably, the host also provides a fault injection component slot for mounting the main control board and signal source.
[0008] Preferably, ruggedized laptops are also included;
[0009] The main control board provides a network communication interface, through which the ruggedized laptop can set fault injection parameters.
[0010] Preferably, it also includes: a display screen for displaying interface switching or parameter settings.
[0011] Preferably, the main control board adopts an embedded software and hardware system design, and the processor is an embedded processor.
[0012] Preferably, the host provides a human-machine interface to monitor the fault injection status.
[0013] As can be seen from the above technical solution, compared with the prior art, this utility model discloses an online fault injection device, a host, and fault injection components; the host controls and manages the fault injection components; the fault injection components include: a 1553B fault injection component, an RS422 fault injection component, a digital fault injection component, and a discrete fault injection component, used to provide 1553B bus fault injection, RS422 bus fault injection, digital fault injection, and discrete fault injection respectively. Primarily targeting communication interfaces such as the 1553B bus and RS422 bus, and electrical signal interfaces such as digital and discrete quantities, the device can generate various test signals for these interfaces and perform fault injection without disrupting the current system connection, used to verify the reliability of these interfaces and for simulation training. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0015] Figure 1 A three-dimensional schematic diagram of an online fault injection device provided by this utility model.
[0016] Figure 2 A schematic diagram of the front panel of an online fault injection device provided by this utility model.
[0017] Figure 3 A schematic diagram of the principle block of the 1553B fault injection component provided for an embodiment of this utility model.
[0018] Figure 4 A schematic diagram of the fault injection circuit for the physical and electrical layers of the 1553B bus communication provided in this embodiment of the utility model.
[0019] Figure 5 A schematic diagram of the cross-linking relationship of the 1553B fault injection component interface provided for an embodiment of this utility model.
[0020] Figure 6 A schematic diagram of a 1553B bus communication network provided for an embodiment of this utility model.
[0021] Figure 7A schematic diagram of the RS422 fault injection component provided for an embodiment of this utility model.
[0022] Figure 8 A schematic diagram of the fault injection circuit for the physical and electrical layers of RS422 bus communication provided in this embodiment of the utility model.
[0023] Figure 9 A schematic diagram of the cross-linking relationship of the RS422 fault injection component interface provided in this embodiment of the utility model.
[0024] Figure 10 A schematic diagram of the RS422 serial communication network structure provided for an embodiment of this utility model.
[0025] Figure 11 A block diagram illustrating the principle of a digital and discrete fault injection component provided in this embodiment of the utility model.
[0026] Figure 12 A schematic diagram of the digital physical layer and electrical layer fault injection circuit provided for an embodiment of this utility model.
[0027] Figure 13 A schematic diagram of the discrete physical layer and electrical layer fault injection circuit provided for an embodiment of this utility model.
[0028] Figure 14 A schematic diagram of the cross-linking relationship of the RS422 fault injection component interface provided for an embodiment of this utility model.
[0029] Figure 15 This is a schematic diagram of the electrical connection for fault injection of digital and discrete quantities provided in the embodiments of this utility model. Detailed Implementation
[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0031] This utility model discloses an online fault injection device, including: a host and a fault injection component;
[0032] The host computer controls and manages the fault injection component;
[0033] The fault injection components include: a 1553B fault injection component, an RS422 fault injection component, a digital fault injection component, and a discrete fault injection component, which are used to provide 1553B bus fault injection, RS422 bus fault injection, digital fault injection, and discrete fault injection, respectively.
[0034] Specifically, the fault injection component provides fault injection for 1553B bus, RS422 bus, digital quantity, and discrete quantity signals. The online fault injection device injects faults into interface signals through the corresponding fault injection component, controlled and managed by the host computer. The host computer provides a network communication interface, and instructors can set fault injection parameters via a ruggedized laptop.
[0035] Specifically, the host also provides a fault injection component slot for mounting the main control board and signal source.
[0036] Specifically, it also includes: a display screen used to show interface switching or parameter settings.
[0037] Specifically, the main control board adopts an embedded software and hardware system design, and the processor is an embedded processor.
[0038] Specifically, the system integration of the fault injection component is completed through the host, which provides a slot for the fault injection component, installs the main control board and signal source, controls and manages the fault injection component through the bus interface, and provides a network communication interface. Instructors can set the fault injection parameters through a ruggedized laptop.
[0039] The host computer adopts an embedded software and hardware system design to achieve the following functions:
[0040] It uses 220V (150V~230V) / 50Hz (45Hz~55Hz) AC power supply, provides a fault injection component mounting slot, and the power supply should be able to meet the power supply requirements of the main controller and each fault simulation board in the equipment.
[0041] Install the main control board to control and manage the fault injection components.
[0042] Install a signal source to provide noise interference signal source for 1553B and RS422.
[0043] Provides network communication interfaces.
[0044] Provide a human-machine interface to monitor the fault injection status.
[0045] Provides interface signal input and output interfaces, and performs fault injection on interface signals.
[0046] It provides an interface for signal monitoring, which can be connected to test instruments to monitor the signals.
[0047] Specifically, it also includes a ruggedized laptop computer;
[0048] The main control board provides a network communication interface, and the ruggedized laptop computer sets the fault injection parameters through the network communication interface.
[0049] In a specific embodiment of the present utility model, system integration is carried out through the host, and a 19-inch cabinet standard rack-mounted chassis installation structure is adopted, with a height of 5U and a weight not exceeding 35 Kg. The chassis appearance is as Figure 1 shown.
[0050] The human-machine interface, power switch, fault injection input / output interface, signal monitoring interface, debugging interface, network communication interface, UUT power monitoring interface, etc. are all designed on the front panel, as Figure 2 shown:
[0051] The display screen is designed with peripheral control buttons for display interface switching or parameter setting.
[0052] The system is powered by an AC 220V power supply (150V - 230Vac / 45Hz - 55Hz), and the power interface is designed on the rear panel, using a standard "pin" shaped power socket.
[0053] The device reserves a display interface externally, supports HDMI or VGA, and can be externally connected to a monitor to provide a human-machine interface.
[0054] 6U CPCI slots are designed inside the host, with a horizontal structure. Heat dissipation is carried out on the Eurocard structure functional boards through the left and right air ducts. The sharp edges and burrs of the test equipment that may cause damage to the operators and on-board equipment should be processed.
[0055] Specifically, the design of the 1553B fault injection component:
[0056] Function design
[0057] The 1553B fault injection component realizes fault injection at the physical layer, electrical layer, and protocol layer of the 1553B bus, and can realize the normal signal of the 1553B bus communication interface. The component has a function of recording the normal test process and can also look back at the inserted fault information replay function. The fault type and injection time can be set by software, and the fault can be injected into the test system in a replay manner. The functions are summarized in the following table:
[0058] Table 1 Summary of 1553B bus fault injection functions
[0059]
[0060] The 1553B fault injection component provides 2 channels of dual-redundant 1553B bus communication and can access up to 30 RTs at most.
[0061] Electrical Principle Design
[0062] The 1553B fault injection component provides two 1553B bus communication interfaces, one as an input and one as an output, providing 1553B bus communication fault injection at the physical, electrical, and protocol layers. The schematic diagram is shown below. Figure 3 As shown.
[0063] The component uses an FPGA to provide two 1553B protocol processors, one for receiving bus messages from the test system and the other for sending bus messages to the object under test, thereby realizing protocol-based fault injection.
[0064] Physical layer fault injection primarily involves altering the open-circuit resistance, termination resistance, and series resistance of the bus loop, which can be controlled via signal relay switches. Electrical layer fault injection requires changing the amplitude of the transmitted signal, which can be achieved by designing signal conditioning circuits in the line link and using an external signal source as a noise source to interfere with the interface signal. The electrical principles of physical and electrical layer fault injection in 1553B bus communication are as follows: Figure 4 As shown, the component controls the relay switches through a control interface, thereby enabling fault injection at the physical and electrical layers.
[0065] Fault injection at the 1553B bus communication protocol layer is achieved through the 1553B bus communication protocol processing, which is completed in the 1553B protocol processor and implemented by FPGA. The 1553B communication rate can be adjusted by changing the message frame period and message interval.
[0066] Interface cross-linking design
[0067] The 1553B fault injection component adopts a 6U CPCI Eurocard architecture design, providing two-way dual-redundant 1553B bus communication. The interface interconnection relationship is as follows: Figure 5 As shown.
[0068] The signal source interface is connected to a noise interference signal source, and interference noise is injected using a coupling method.
[0069] The 1553B fault injection component provides two dual-redundant 1553B bus communications. Generally, the 1553B bus communication unit is connected to the stub end of the bus communication network, thus the two 1553B bus communications operate on two separate bus segments. Figure 6 As shown.
[0070] like Figure 6 As shown, switching of the 1553B communication network can be achieved using two DPDT signal relay switches K1 and K2, and the logic relationship is shown in the table below:
[0071] Table 21553B Communication Network Control Logic
[0072]
[0073] When a communication network is built through coupler 2, normal signals of the 1553B bus communication interface can be realized, and faults can be injected into the test system through playback.
[0074] When multiple RTs need to be connected, a multi-port coupler can be configured, allowing up to 30 RTs (RT1 to RT30) to be connected to the Stub port. 1553B bus communication monitoring can be performed via the Stub interface.
[0075] Coupler 2 can be designed as an onboard component or accessed via a component panel interface.
[0076] Specifically, RS422 fault injection component design
[0077] Functional design
[0078] The RS422 fault injection component enables fault injection at the physical, electrical, and protocol layers of RS422 serial communication, ensuring normal signal transmission through the RS422 serial communication interface. The component records normal test procedures and allows for playback of inserted fault information. Fault type and injection time are configurable via software. Faults can be injected into the test system through playback. A summary of its functions is shown in the table below.
[0079] Table 3 Summary of RS422 bus fault injection functions
[0080]
[0081]
[0082] Electrical Principle Design
[0083] The RS422 fault injection component provides 8 RS422 serial communication interfaces, 4 of which are input interfaces and 4 are output interfaces. It provides RS422 bus communication fault injection at the physical layer, electrical layer, and protocol layer. The principle block diagram is as follows: Figure 7 As shown.
[0084] The component implements RS422 serial communication processing through FPGA. Four channels are used to receive RS422 serial communication data from the test system, and four channels are used to send serial communication data to the object under test, thereby realizing protocol-based fault injection.
[0085] Physical layer fault injection mainly involves altering the path connection state, signal short-circuit state, and bridging resistor open-circuit state, which can be controlled via signal relay switches. Electrical layer fault injection requires changing the amplitude of the transmitted signal and adding noise interference, which can be achieved by designing signal conditioning circuits in the line link and providing noise interference to the interface signal through external interference signals. The electrical principles of physical and electrical layer fault injection in RS422 bus communication are as follows: Figure 8 As shown, the component controls each relay switch through a bus interface, thereby enabling fault injection at the physical and electrical layers.
[0086] RS422 bus protocol layer fault injection is achieved through RS422 serial communication protocol processing. It is completed in the RS422 serial communication protocol processor and implemented by FPGA. The communication rate can be adjusted by changing the data transmission baud rate.
[0087] Interface cross-linking design
[0088] The RS422 fault injection component adopts a 6U CPCI Eurocard architecture design, providing 8 RS422 serial communication channels, including 4 inputs and 4 outputs. The interface interconnection relationship is as follows: Figure 9 As shown.
[0089] The RS422 input interface (IN) is used to connect to the test system, and the RS422 output interface (OUT) is used to connect to the object under test, thereby realizing RS422 bus fault injection at the protocol layer. The communication network structure is as follows: Figure 10 As shown.
[0090] The RS422 fault injection component mainly performs fault injection for RS422 TX+ / TX-, such as Figure 10 As shown, switching of the RS422 serial communication network can be achieved using two DPDT signal relay switches K1 and K2. The logic relationship is shown in the table below:
[0091] Table 4 RS422 Communication Network Control Logic
[0092]
[0093]
[0094] When K2 is closed, the RS422 bus communication interface can achieve normal signal, and the fault can be injected into the test system through playback.
[0095] Specifically, design of digital and discrete fault injection components.
[0096] Functional design
[0097] This project involves both digital and discrete quantities, all of which are state variables. A fault injection component for digital and discrete quantities is used to inject faults at the physical, electrical, and protocol layers, enabling normal signal transmission at the digital and discrete quantity interfaces. The component has a normal test process recording function and a function to replay inserted fault information. The fault type and injection time can be set by software. Faults can be injected into the test system through playback. A summary of the functions is shown in the table below:
[0098] Table 5 Summary of Digital and Discrete Quantity Fault Injection Functions
[0099]
[0100]
[0101] Electrical Principle Design
[0102] The digital and discrete fault injection component provides 10 digital input / output channels and 10 discrete input / output channels, offering digital and discrete fault injection at both the physical and electrical layers. The block diagram is shown below. Figure 11 As shown.
[0103] The component uses an FPGA to implement digital input / output processing and discrete input / output processing. Ten digital input channels are used to receive digital outputs from the test system, ten discrete input channels are used to receive discrete outputs from the test system, ten digital output channels are used to output digital quantities to the object under test, and ten discrete output channels are used to output discrete quantities to the object under test, thereby realizing fault injection of digital and discrete quantities.
[0104] Physical layer fault injection for digital and discrete quantities mainly alters the on / off state, impedance, and input impedance of signals and signal loops, which can be controlled via signal relay switches. Electrical layer fault injection requires changing the signal amplitude of digital quantities and the switching state of discrete quantities. The signal amplitude can be adjusted using signal conditioning circuits, and the switching state can be controlled by adjusting the output state of discrete quantities.
[0105] The electrical principle of fault injection in digital physical layer and electrical layer is as follows: Figure 12 As shown, the component controls each relay switch through the bus interface, thereby enabling fault injection into the digital physical layer and electrical layer.
[0106] Discrete quantity physical layer and electrical layer fault injection electrical principles as follows Figure 13As shown, the component controls each relay switch via a bus interface, thereby enabling fault injection at the discrete physical and electrical layers. For fault injection at the digital and discrete protocol layers, the digital and discrete input / output processing unit acquires the digital and discrete status of the test system and controls the digital and discrete output logic according to preset fault injection parameters. The digital and discrete input / output processing unit can acquire the digital and discrete status via optocouplers.
[0107] Interface cross-linking design
[0108] The digital and discrete fault injection components adopt a 6U CPCI Eurocard architecture, providing 10 digital inputs, 10 discrete inputs, 10 digital outputs, and 10 discrete outputs. The interface interconnection relationships are as follows: Figure 14 As shown.
[0109] The input interface (IN) is used to connect to the test system, and the output interface (OUT) is used to connect to the object under test. It can implement fault injection of digital and discrete quantities at the protocol layer. The electrical connection relationship is as follows: Figure 15 As shown.
[0110] Digital fault injection is switched via relay switches K1 and K2, and the logic relationship is shown in the table below:
[0111] Table 6 Digital Fault Injection Control Logic
[0112]
[0113] When K2 is closed, a normal signal from the digital interface can be achieved, and a fault can be injected into the test system through playback.
[0114] Discrete quantity fault injection is switched via relay switches K1 and K3, and the logic relationship is shown in the table below:
[0115] Table 7 Discrete Quantity Fault Injection Control Logic
[0116]
[0117] When K3 is closed, a normal signal from the discrete interface can be achieved, and a fault can be injected into the test system through playback.
[0118] This utility model embodiment features a specially designed packaging box with a pull-rod design. The interior is filled with rigid foam for shock absorption and is divided into sections, facilitating the storage and transportation of the equipment.
[0119] This invention primarily targets communication interfaces such as the 1553B bus and RS422 bus, as well as electrical signal interfaces such as digital and discrete quantities. The device can generate various test signals for these interfaces and inject faults without disrupting the current system connection, thereby verifying the reliability of these interfaces and performing simulation training.
[0120] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0121] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A fault injection device in the online manner, characterized in that, include: Host and fault injection components; The host computer controls and manages the fault injection component; The fault injection components include: a 1553B fault injection component, an RS422 fault injection component, a digital fault injection component, and a discrete fault injection component, which are used to provide 1553B bus fault injection, RS422 bus fault injection, digital fault injection, and discrete fault injection, respectively.
2. The online fault injection device according to claim 1, characterized in that, The host also provides a fault injection component slot for mounting the main control board and signal source.
3. The online fault injection device according to claim 2, characterized in that, This also includes ruggedized laptops; The main control board provides a network communication interface, through which the ruggedized laptop can set fault injection parameters.
4. The online fault injection device according to claim 1, characterized in that, Also includes: The display screen is used to show interface switching or parameter settings.
5. The online fault injection device according to claim 2, characterized in that, The main control board adopts an embedded software and hardware system design, and the processor is an embedded processor.
6. The online fault injection device according to claim 1, characterized in that, The host provides a human-machine interface to monitor the fault injection status.