Communication abnormity reset circuit

Abstract

The utility model discloses a communication abnormity reset circuit which comprises a detection module, a power supply module and a communication module. When a detection module detects that a communication module is abnormal, a soft and hard reset combination mode is adopted for processing, soft reset is that the communication module is controlled to reset through a first control signal, and hard reset is that a power supply module is controlled to be powered off and then powered on through a second control signal. The grading processing mechanism not only can find and process communication abnormity in time, but also can take corresponding processing measures according to the severity of the abnormity, thereby avoiding tedious operation of manually performing power-off restarting by a user, improving the convenience of product use, and meanwhile, through a strategy of firstly trying soft reset and then adopting hard reset, the user experience is improved. Interference to normal communication can be reduced to the maximum extent while the reset effect is guaranteed, and therefore the user experience is improved.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a communication fault reset circuit. Background Technology

[0002] In the field of electronic products, peripheral electronic devices such as Bluetooth keyboards interact with host devices via communication technology. Because these products operate as slave devices, unlike host devices which can provide system prompts or interface feedback to users promptly identify problems when communication failures occur, the current industry-standard solution is to reset via hardware power-off restart. This requires users to manually disconnect the device from the host or power on / off via a power switch. This approach is not only cumbersome but also disrupts communication between the device and host, causing application lag and, in severe cases, rendering the device completely unusable, significantly degrading the user experience. Therefore, how to achieve automatic detection and handling of abnormal states, avoiding manual user intervention, is a pressing technical problem that needs to be solved. Utility Model Content

[0003] The purpose of this invention is to provide a communication abnormality reset circuit to realize the automatic detection and handling of abnormal states.

[0004] This utility model provides a communication fault reset circuit, including: a power supply module, a communication module, and a detection module;

[0005] The power supply module is connected to the communication module in a one-to-one correspondence, and is used to supply power to the communication module;

[0006] The detection module is used to detect the working status of the communication module. When the detection module detects a communication abnormality in the communication module, it outputs a first control signal to control the communication module to perform a soft reset. If the communication module does not return to normal working status, the detection module outputs a second control signal to control the power supply module corresponding to the communication module to power off and then power on again.

[0007] Furthermore, the power supply module includes an LDO; the LDO is used to supply power to the communication module.

[0008] Furthermore, the power input terminal of the LDO is connected to the input voltage through a first filter circuit, and the enable terminal is electrically connected to the second control signal; the switching output terminal of the filter circuit outputs the power supply voltage to the communication module through a second filter circuit; the feedback terminal of the filter circuit samples the power supply voltage through a voltage divider circuit, and adjusts the power supply voltage according to the sampled feedback voltage.

[0009] Furthermore, the first filter circuit includes at least one capacitor;

[0010] The input voltage is filtered by the capacitor before being input to the power input terminal.

[0011] Furthermore, the filter circuit includes at least one capacitor and a first inductor;

[0012] One end of the first inductor is connected to the output terminal of the switch, and the other end is connected to one end of the capacitor to output the power supply voltage. The other end of the capacitor is grounded.

[0013] Furthermore, the voltage divider circuit includes a first resistor and a second resistor;

[0014] One end of the first resistor is electrically connected to the power supply voltage, and the other end is connected to one end of the second resistor, while the other end of the second resistor is grounded.

[0015] The feedback terminal is connected to the end of the first resistor and the second resistor.

[0016] Furthermore, the detection module is a CPU.

[0017] Furthermore, the communication module includes at least one of a BLE communication module, an IIC communication module, an SPI communication module, an SLE communication module, and a MIPI communication module.

[0018] Compared with the prior art, the present invention has at least the following technical effects:

[0019] When the detection module detects an anomaly in the communication module, it employs a combination of hard and soft resets. A soft reset uses a first control signal to reset the communication module, while a hard reset uses a second control signal to power off and then on the power supply module. This tiered processing mechanism not only promptly detects and handles communication anomalies but also takes appropriate measures based on the severity of the anomaly. This avoids the cumbersome manual power-off and restart operations for users, improving product usability. Furthermore, by first attempting a soft reset and then a hard reset, the strategy minimizes interference with normal communication while ensuring the reset effect, thereby enhancing the user experience. Attached Figure Description

[0020] Figure 1 This is a structural block diagram of a communication fault reset circuit in one embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the circuit structure of the power supply module in one embodiment of the present invention;

[0022] Figure 3 This is a partial circuit diagram of the detection module in one embodiment of the present invention;

[0023] Figure 4 This is a partial circuit structure diagram of the BLE communication module in one embodiment of the present invention;

[0024] Figure 5 This is a partial circuit structure diagram of the SLE communication module in one embodiment of the present invention. Detailed Implementation

[0025] The following description, in conjunction with schematic diagrams, illustrates a communication fault reset circuit according to the present invention, which represents a preferred embodiment of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present invention.

[0026] The present invention will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0027] Please refer to Figures 1-5 This embodiment discloses a communication fault reset circuit, including: a detection module, a power supply module and a communication module.

[0028] In this embodiment, a power supply module is connected to a communication module in a one-to-one correspondence to supply power to the communication module; a detection module is used to detect the working status of the communication module; when the detection module detects a communication abnormality in the communication module, it outputs a first control signal to control the communication module to perform a soft reset; if the communication module does not return to normal working status, the detection module outputs a second control signal to control the power supply module corresponding to the communication module to power off and then power on again.

[0029] In this embodiment, the number of power supply modules and communication modules can be set according to requirements and is not limited here. For example, it can be 2, 3, or 4.

[0030] In this embodiment, a combination of two reset methods is used. When the detection module determines that the communication module is in an abnormal communication state, it first performs a soft reset, that is, directly controls the communication module to reset. If the soft reset fails to restore the communication module to normal, a hard reset function is activated. That is, the communication module outputs a second control signal to control the power supply module corresponding to the communication module to cut off power and then power on. The advantages of using the above reset methods are: soft reset is fast but ineffective for serious faults, while hard reset is thorough but will interrupt all running tasks. Trying soft reset first allows for a rapid response to minor faults. Hard reset is used only after soft reset fails, which can avoid frequent power outages and improve fault handling efficiency.

[0031] As can be seen, in this embodiment, by using a combination of soft reset and hard reset when the detection module detects an anomaly in the communication module, this hierarchical processing mechanism can not only detect and handle communication anomalies in a timely manner, but also take corresponding measures according to the severity of the anomaly. This avoids the tedious operation of manually powering off and restarting the device, improving the convenience of product use. At the same time, by trying a soft reset first and then using a hard reset, the reset effect can be guaranteed while minimizing interference with normal communication, thereby improving the user experience.

[0032] In one specific embodiment, the power supply module includes an LDO (low-voltage linear regulator); the LDO is used to supply power to the communication module.

[0033] Please continue to refer to this. Figure 2 The power input terminal VIN of the LDO U505 is connected to the input voltage VBAT through the first filter circuit, and the enable terminal EN is electrically connected to the second control signal VDD_EN. The switch output terminal SW of the filter circuit outputs the power supply voltage VDD_IN to the communication module through the second filter circuit. The feedback terminal FB of the filter circuit samples the power supply voltage VDD_IN through the voltage divider circuit and adjusts the power supply voltage VDD_IN according to the sampled feedback voltage.

[0034] In this embodiment, the first filter circuit includes at least one capacitor, wherein the capacitor is used to filter out noise and ripple of the VBAT power supply and stabilize the input voltage VBAT.

[0035] It is understood that those skilled in the art can select the number and type of capacitors installed between the input voltage VBAT and the power input terminal VIN based on actual cost requirements and the specific level of interference.

[0036] Please continue to refer to this. Figure 2In one specific embodiment, the power input terminal VIN of the LDO is connected to the input voltage VBAT in sequence through three parallel capacitors (C315, C514 and C515).

[0037] Furthermore, in this embodiment, the second control signal VDD_EN output by the detection module is input to the enable terminal EN, which can control the working state of the LDO. When the second control signal VDD_EN controls the LDO to power off and then power on again, the communication module will also power off and then power on, thereby completing a restart and reset.

[0038] In one specific embodiment, when VDD_EN is high, the LDO is turned on and outputs the supply voltage VDD_IN to the communication module; conversely, if VDD_EN is low, the LDO is turned off.

[0039] In one specific embodiment, when the VDD_EN signal is high, the output voltage is 3.3V. Those skilled in the art can select different level signals as enable signals according to actual conditions, such as 1.8V, 2.5V, or 5V.

[0040] In this embodiment, the second filter circuit includes at least one capacitor and a first inductor L503.

[0041] Specifically, one end of the first inductor L503 is connected to the switch output terminal SW, and the other end is connected to one end of the capacitor to output the supply voltage VDD_IN. The other end of the capacitor is grounded.

[0042] In this embodiment, at least one capacitor and a first inductor form an EMC filter network. The first inductor is used to suppress high-frequency interference and surge current, while the capacitor is used to bypass high-frequency interference signals to ground, thereby reducing the radiation of electromagnetic noise from the circuit and preventing external electromagnetic interference from affecting the normal operation of the circuit.

[0043] It is understandable that those skilled in the art can select the number and type of capacitors to be installed based on actual cost requirements and the specific level of interference.

[0044] Please continue to refer to this. Figure 2In one specific embodiment, the filter circuit includes a first capacitor C516, a second capacitor C517, a third capacitor C518, and a first inductor L503. One end of the first inductor L503 is connected to the switch output terminal SW, and the other end is connected to one end of the first capacitor C516; the other end of the first capacitor C516 is connected to the feedback terminal FB. One end of the second capacitor C517 is connected to one end of the first capacitor C516, and the other end is grounded. One end of the third capacitor C518 is connected to one end of the second capacitor C517 and outputs the supply voltage VDD_IN, and the other end is grounded.

[0045] In this embodiment, the voltage divider circuit includes a first resistor and a second resistor R511.

[0046] Specifically, one end of the first resistor is electrically connected to the supply voltage VDD_IN, and the other end is connected to one end of the second resistor R511, while the other end of the second resistor R511 is grounded.

[0047] In the actual design process, those skilled in the art need to select a suitable LDO based on the load power consumption of the actual communication module. Preferably, the rated output power of the LDO is 20% higher than the rated power consumption of the communication module. This ensures that the LDO does not operate under full load, avoids overheating, and extends its service life. At the same time, since different communication modules have specific time requirements for the power-on and power-off sequence, i.e., the time interval required from the start of power supply to the module being fully operational, or from power-off to complete shutdown, it is possible to select an LDO device with suitable start-up and shutdown times and control the timing of the VDD_EN signal through software to ensure compliance with the power-on and power-off time specifications of each functional module, thereby ensuring that the communication module can operate normally.

[0048] Furthermore, in this embodiment, the detection module is a CPU. Please refer to... Figure 3 The CPU has multiple communication ports (I2C1 pins such as I2C1_SCL and I2C1_SDA shown in the figure), interrupt ports (INT pins such as MOTO_INT and SAR_INT shown in the figure), reset control terminals (RST pins such as MOTO_RST), and enable signal output terminals (VDD_EN output pin).

[0049] The CPU maintains normal communication with various functional modules through communication ports such as IIC. The communication modules report their operating status to the CPU via interrupt ports (such as MOTO_INT and SAR_INT). When the CPU detects no response from a communication port, receives an abnormal interrupt signal from the interrupt port, or experiences abnormal communication data, an external circuit (e.g., a timer) outputs a high-level signal to the CPU. When the CPU's UART_RX pin receives a high-level signal, it outputs a high-level signal (the first control signal) through the reset control terminal (MOTO_RST) to control the communication module to reset. If the soft reset fails, the CPU controls the LDO to power down and then power on again through the enable signal output terminal (VDD_EN), thereby controlling a hard reset of the communication module.

[0050] Furthermore, in this embodiment, the communication module includes at least one of the following: BLE communication module (Bluetooth Low Energy Communication Module), IIC communication module (Integrated Circuit Bus Communication Module), SPI communication module (Serial Peripheral Interface Communication Module), SLE communication module (Starlight Communication System Access Module), and MIPI communication module (Mobile Industry Processor Interface Communication Module).

[0051] Please refer to Figure 4 Pins AD14, W1, AD23, A22, B1, AB2, and Y2 are the power supply interfaces for the BLE communication module. The power supply voltage VDD_IN is input to these seven pins respectively. Preferably, a filter circuit is also connected between each pin and the output of the LDO. This filter circuit consists of multiple capacitors connected in parallel and is used to decouple and filter each power supply pin.

[0052] In one specific embodiment, the number of capacitors is 5 ( Figure 3 As shown in C502-C507), those skilled in the art can select the number and type of capacitors according to actual cost requirements and the specific level of interference.

[0053] Please refer to this again. Figure 5 Pins G1 and C1 are the power supply interfaces for the SLE communication module. The power supply voltage VDD_IN is input to pins G1 and C1 respectively. Preferably, a filter circuit is also connected between each pin and the output of the LDO. This filter circuit is also composed of multiple capacitors connected in parallel, used to decouple and filter each power supply pin.

[0054] In one specific embodiment, the number of capacitors is 2 ( Figure 4As shown in C208 and C210), those skilled in the art can select the number and type of capacitors according to actual cost requirements and the specific level of interference.

[0055] Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this utility model and their equivalents, this utility model also intends to include these modifications and variations.

Claims

1. A communication fault reset circuit, characterized in that, include: Power supply module, communication module, and detection module; The power supply module is connected to the communication module in a one-to-one correspondence, and is used to supply power to the communication module; The detection module is used to detect the working status of the communication module. When the detection module detects a communication abnormality in the communication module, it outputs a first control signal to control the communication module to perform a soft reset. If the communication module does not return to normal working status, the detection module outputs a second control signal to control the power supply module corresponding to the communication module to power off and then power on again.

2. The communication fault reset circuit as described in claim 1, characterized in that, The power supply module includes an LDO; the LDO is used to supply power to the communication module.

3. The communication fault reset circuit as described in claim 2, characterized in that, The power input terminal of the LDO is connected to the input voltage through the first filter circuit, and the enable terminal is electrically connected to the second control signal; the switch output terminal of the filter circuit outputs the power supply voltage to the communication module through the second filter circuit; the feedback terminal of the filter circuit samples the power supply voltage through the voltage divider circuit, and adjusts the power supply voltage according to the sampled feedback voltage.

4. The communication fault reset circuit as described in claim 3, characterized in that, The first filter circuit includes at least one capacitor; The input voltage is filtered by the capacitor before being input to the power input terminal.

5. The communication fault reset circuit as described in claim 4, characterized in that, The filter circuit includes at least one capacitor and a first inductor; One end of the first inductor is connected to the output terminal of the switch, and the other end is connected to one end of the capacitor to output the power supply voltage. The other end of the capacitor is grounded.

6. The communication fault reset circuit as described in claim 5, characterized in that, The voltage divider circuit includes a first resistor and a second resistor; One end of the first resistor is electrically connected to the power supply voltage, and the other end is connected to one end of the second resistor, while the other end of the second resistor is grounded. The feedback terminal is connected to the end of the first resistor and the second resistor.

7. The communication fault reset circuit as described in claim 1, characterized in that, The detection module is a CPU.

8. The communication fault reset circuit as described in claim 1, characterized in that, The communication module includes at least one of BLE communication module, IIC communication module, SPI communication module, SLE communication module and MIPI communication module.

Images