PXIE high-speed storage module

Abstract

The utility model discloses a PXIE high-speed storage module which comprises a 3U PXIE standard card board, an FPGA module, an optical fiber module and an SSD storage group are welded on the 3U PXIE standard card board, and the FPGA module is electrically connected with the optical fiber module through GTH and I2C data lines; the SSD storage group comprises two SSDs (Solid State Disks) which are electrically connected with the FPGA module through PCIE (Peripheral Component Interface Express) X4 data lines; according to the utility model, the two SSDs are independently connected with the FPGA module through the PCIE X4 interface to form a 2 * PCIE X4 parallel storage channel. When data is written or read, the FPGA module can distribute data to the two SSDs at the same time, bandwidth superposition is achieved, the SSDs support the NVME protocol, and compared with a traditional SATA protocol, delay can be greatly reduced, the throughput capacity can be greatly improved, and the high-speed read-write requirement can be met; and a PCIE channel is used as a main data path of a host end, and PCIE GEN3X8 can support unidirectional transmission with the highest speed of about 8GB / s, so that high-speed data exchange between the host and the storage module is ensured.

Description

Technical Field

[0001] This utility model relates to the field of PXIE board equipment technology, specifically a PXIE high-speed storage module. Background Technology

[0002] Currently, storage boards on the market are roughly divided into two types: one is VPX 6U storage modules or larger PCIe storage modules, which cannot meet the miniaturization requirements of measurement and control equipment; the other is PXIe specification storage boards, which can only provide PCIe 2.0 x8 channels, with a maximum read speed of 2GB / s and a maximum write speed of 2.5GB / s, which is not high enough in performance and cannot be triggered synchronously.

[0003] A search revealed a patent application with application number 201710368307.0 that discloses a design method for a PowerPC-based SRIO interface solid-state drive, which connects multiple SATA3.0 SSDs after synchronizing one PowerPC PCIe via an FPGA.

[0004] While this architecture improves read / write speeds and storage capacity to some extent, it still cannot meet the performance requirements of a single module storage capacity of 16TB and a continuous read / write bandwidth of 6Gb / s (6Gbp / s) or higher. Furthermore, the module size and architecture do not meet the high-speed storage requirements of the PXIE specification.

[0005] Patent application CN202022872561.4 discloses a high-performance storage board with a 3U PXIe form factor, offering a maximum storage capacity of 8TB. ​​However, its maximum read speed is 2GB / s and its maximum write speed is 2.5GB / s, which cannot meet the data acquisition requirements of a high-speed ADC with a bandwidth of 1Gbps. Utility Model Content

[0006] The purpose of this invention is to provide a PXIE high-speed storage module that meets the high-speed storage requirements of the PXIE specification in terms of module size and architecture, while achieving a single module storage capacity of 8TB and a continuous read / write bandwidth of over 3GB / s.

[0007] To achieve the above objectives, this utility model provides the following technical solution: a PXIE high-speed storage module, comprising a 3U PXIE standard card board, wherein an FPGA module, an optical fiber module, and an SSD storage group are soldered onto the 3U PXIE standard card board, and the FPGA module connects to GTH and I... 2 The C data cable is electrically connected to the fiber optic module;

[0008] The SSD storage group includes two SSD solid-state drives that are electrically connected to the FPGA module via a PCIe x4 data cable.

[0009] Preferably, the capacity of each SSD is set to 4TB.

[0010] Preferably, the 3U PXIE standard board includes a board body and a PXIE standard connector soldered onto the board body. The PXIE standard connector is electrically connected to a PXIe-XJ3 interface and a PXIe-XJ4 interface. The FPGA module is electrically connected to the PXIe-XJ3 interface through one PCIE X8 port.

[0011] Preferably, the FPGA module is connected to the MPO optical receiver module in the optical fiber module via 12 GTH RX channels, and the FPGA module is connected to the MPO optical transmitter module in the optical fiber module via 12 GTH TX channels.

[0012] Preferably, the FPGA module is electrically connected to a DDR3 cache module for temporary data caching.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] 1. This utility model uses two SSD solid-state drives connected independently to an FPGA module via a PCIe x4 interface to form a "2×PCIe x4" parallel storage channel. When data is written or read, the FPGA module can simultaneously allocate data to the two SSDs, achieving bandwidth aggregation. The SSDs support the NVMe protocol, which significantly reduces latency and increases throughput compared to the traditional SATA protocol, meeting high-speed read and write requirements. Furthermore, the PCIe channel serves as the main data path on the host side, and PCIe Gen3 x8 can support unidirectional transmission up to approximately 8GB / s, ensuring high-speed data exchange between the host and the storage module. This allows the module to achieve a storage capacity of 8TB while meeting performance requirements of continuous read and write bandwidths of over 3GB / s.

[0015] 2. The 3U PXIE standard card design conforms to the PXIE specification in terms of module size and architecture, meeting the miniaturization requirements of measurement and control equipment. Compared with VPX 6U storage modules or larger PCIE storage modules, it has a greater advantage in terms of space occupation.

[0016] 3. The FPGA module is connected to the DDR3 cache module as a buffer pool for data read and write, which can smooth the speed difference between the SSD and the high-speed interface and reduce bandwidth fluctuations caused by the SSD's erase and write latency. Attached Figure Description

[0017] Figure 1 This is a layout diagram of the PXIE high-speed storage module of this utility model;

[0018] Figure 2 This is a test graph of the read and write speeds of the PXIE high-speed storage module during three sampling periods when it is working.

[0019] Figure 3 These are the read and write speed test charts for eight additional sampling periods during the operation of the PXIE high-speed storage module of this utility model. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] Please see Figure 1-3 This utility model provides a technical solution: a PXIE high-speed storage module, including a 3U PXIE standard card board, on which an FPGA module, an optical fiber module, and an SSD storage group are soldered. The FPGA module connects to GTH and I... 2 The C data cable is electrically connected to the fiber optic module;

[0022] The FPGA module, model XCKU11P-2FFVA1156I, supports the PCIE GEN3 standard, providing computing power for high-speed data processing. The fiber optic module, model HTG8503-PH-T002SF, supports high-speed optical signal transmission. As the main control core, the FPGA module can handle tasks such as storage read / write and interface protocol conversion in parallel, avoiding data processing bottlenecks.

[0023] The SSD storage group includes two SSDs electrically connected to the FPGA module via a PCIe x4 data cable. The SSDs used are Samsung 990 Pro models to ensure storage performance.

[0024] Each SSD has a capacity of 4TB and connects to a Samsung 990 Pro SSD via two PCIe x4 interfaces, with a single drive capacity of 4TB and a total capacity of 8TB. ​​The theoretical unidirectional bandwidth of the PCIe Gen3 x4 interface is approximately 4GB / s, with each lane providing approximately 1GB / s. With four lanes, the bandwidth of two SSDs can be aggregated through parallel read / write operations. When data is being written or read, the FPGA module can simultaneously allocate data to both SSDs, achieving bandwidth aggregation. For example, a single drive's continuous read / write bandwidth is approximately 1.5GB / s, and two drives in parallel can achieve speeds exceeding 3GB / s.

[0025] SSDs support the NVMe protocol, which significantly reduces latency and increases throughput compared to the traditional SATA protocol, meeting high-speed read and write requirements.

[0026] The 3U PXIE standard card includes a card body and a PXIE standard connector soldered onto the card body. The PXIE standard connector is electrically connected to a PXIe-XJ3 interface and a PXIe-XJ4 interface. The FPGA module is electrically connected to the PXIe-XJ3 interface through one PCIE X8 port.

[0027] The 3U PXIE standard card conforms to the PXIE standard and achieves physical and electrical connection with the host system through PXIE standard connectors. The PXIe-XJ3 and PXIe-XJ4 interfaces serve as data exchange channels. The PCIE x8 host interface connects to the PXIe-XJ3 interface via one PCIE GEN3 x8 port, theoretically providing a unidirectional bandwidth of approximately 8GB / s and a bidirectional bandwidth of 16GB / s. This provides a high-speed channel for data to and from the storage module. The module clock signal and trigger signal are connected to the PXIe-XJ4 interface through the FPGA module, ensuring the synchronization of data acquisition and storage when multiple devices work together, and avoiding transmission efficiency degradation due to timing discrepancies.

[0028] The FPGA module is connected to the MPO optical receiver module in the fiber optic module via 12 GTH RX channels, and the FPGA module is connected to the MPO optical transmitter module in the fiber optic module via 12 GTH TX channels. It supports 12 parallel optical signal transmission and reception channels through the PXIe-67XX module, which can realize direct access to external high-speed data streams. The single-channel transmission rate can reach 10.3125Gbps, which can meet the external high-speed data access requirements.

[0029] The FPGA module is electrically connected to a DDR3 cache module for temporary data caching. This acts as a buffer for data read / write operations, smoothing out speed differences between the SSD storage group and the high-speed interface, and reducing bandwidth fluctuations caused by SSD storage group write / erase delays. The FPGA module slices the data and writes it in parallel to the two SSDs, using a pipelined architecture to achieve continuous data transfer and avoid idle storage channels.

[0030] During use, hardware assembly is performed: Prepare a 3UPXIE compliant card board, ensuring its size and interfaces conform to relevant specifications. Solder the CKU11P-2FFVA1156I FPGA module, HTG8503-PH-T002SF fiber optic module, Samsung 990Pro SSD solid-state drive, and DDR3 cache module to their respective positions on the card board. According to design requirements, connect the FPGA module and SSD storage group via a PCIe x4 data cable, and connect the FPGA module and fiber optic module via GTH and I... 2 Connect the C data cable to connect the FPGA module to the PXIe-XJ3 interface via one PCIe x8 port, and connect the FPGA module to the PXIe-XJ4 interface to transmit clock and trigger signals.

[0031] Data storage process: External data is transmitted to the FPGA module via the PXIe-XJ3 interface. After processing, the FPGA module writes the data to the SSDs in the SSD storage group via the PCIe x4 interface. The DDR3 cache module acts as a buffer during data storage, ensuring the stability of data writing.

[0032] Data readback process: When data needs to be read back, the FPGA module reads data from the SSD storage group and transmits it to the external device via the PXIe-XJ4 interface. During the data readback process, the DDR3 cache module is also used to improve data transmission efficiency; the clock signal and trigger signal transmitted through the PXIe-XJ4 interface enable the module to work synchronously with other devices, ensuring the accuracy and consistency of data acquisition and storage.

[0033] This storage module uses an FPGA module and a fiber optic module on a 3U PXIE standard card board. The FPGA module is connected to an external SSD storage group. When data is written or read, the FPGA module can simultaneously allocate data to the two SSD solid-state drives to achieve bandwidth aggregation. Compared with traditional storage modules, its module size and architecture can meet the high-speed storage requirements of the PXIE specification, and the storage capacity of a single module can reach 8TB, with a continuous read and write bandwidth of more than 3GB / s.

[0034] like Figure 2 , Figure 3The image shows the read / write speed test graphs for the PXIE high-speed storage module at different sampling periods. 1C05 in decimal is 7173, and 1S in ns is 1,000,000,000. With each cycle lasting 4ns, 1s is 250,000,000, and the speed is 250,000,000 * 7173 / 1024 = 1.75GB. The two SSDs achieved a read / write speed of 3.5GB, meeting performance requirements exceeding 3GB / s.

[0035] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A PXIE high-speed storage module, characterized in that: This includes a 3U PXIE standard card board, on which an FPGA module, a fiber optic module, and an SSD storage array are soldered. The FPGA module connects to GTH and I... 2 The C data cable is electrically connected to the fiber optic module; The SSD storage group includes two SSD solid-state drives that are electrically connected to the FPGA module via a PCIe x4 data cable.

2. The PXIE high-speed storage module according to claim 1, characterized in that: Each of the SSDs is configured with a capacity of 4TB.

3. A PXIE high-speed storage module according to claim 2, characterized in that: The 3U PXIE standard card includes a card body and a PXIE standard connector soldered onto the card body. The PXIE standard connector is electrically connected to a PXIe-XJ3 interface and a PXIe-XJ4 interface. The FPGA module is electrically connected to the PXIe-XJ3 interface through one PCIE X8 port.

4. A PXIE high-speed storage module according to claim 3, characterized in that: The FPGA module is connected to the MPO optical receiver module in the fiber optic module via 12 GTH RX channels, and the FPGA module is connected to the MPO optical transmitter module in the fiber optic module via 12 GTH TX channels.

5. A PXIE high-speed storage module according to claim 1, characterized in that: The FPGA module is electrically connected to a DDR3 cache module for temporary data caching.

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