Self-locking power supply control circuit based on self-resetting switch
By using a power control circuit that links a self-locking switch with a MOS switch and an NPN switch, the problems of high cost of self-locking switches and power failure of equipment are solved, achieving low cost, miniaturization and reliable shutdown, expanding the applicable scenarios and improving system stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHENZHEN GIEC DIGITAL CO LTD
- Filing Date
- 2025-05-20
- Publication Date
- 2026-05-01
AI Technical Summary
In existing power control circuits, self-locking switches are expensive and large in size, and directly shutting off the power may cause equipment malfunctions and data loss.
A self-locking power control circuit based on a self-resetting switch is adopted. Through the linkage of MOS switch and NPN switch with the main control of the equipment, the power supply is cut off after the system completes the normal shutdown process to avoid power failure of the equipment.
It achieves low-cost, small-size, and widely applicable power control, ensuring reliable equipment shutdown, avoiding system anomalies and data loss, and improving system stability.
Smart Images
Figure CN224191822U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of power supply technology, and in particular to a self-locking power supply control circuit based on a self-resetting switch. Background Technology
[0002] Power control circuits are a crucial component of electronic systems, managing and regulating the conversion, distribution, and protection of electrical energy to ensure stable and efficient equipment operation. Currently, most power control circuits in the industry employ self-locking switches, which remain in a conductive state when pressed and return to a cut-off state when pressed again. However, the complex mechanical structure of self-locking switches leads to higher costs; the presence of springs within the switches results in a longer overall length, making them difficult to integrate into compact product designs. Furthermore, power control circuits using self-locking switches directly shut off the power during switchover, instantly cutting off the power supply to the main control unit. This causes the main control unit to lose power before completing the normal shutdown process, potentially leading to system anomalies and data loss. Utility Model Content
[0003] Therefore, it is necessary to address the above-mentioned shortcomings by providing a self-locking power control circuit based on a self-resetting switch that is lower in cost, smaller in size, has a wider range of applications, and can ensure that the system shuts down in a correct and reliable manner.
[0004] A self-locking power control circuit based on a self-resetting switch is connected to a device main controller and used to control the on / off state between a power input terminal and a power output terminal. The device main controller is connected to the power output terminal and is used to receive input signals and generate output signals. The self-locking power control circuit includes a first MOS switch connected between the power input terminal and the power output terminal and used to output the input signal; an NPN switch connected to the first MOS switch, the power input terminal, the power output terminal, and the device main controller to receive the output signal; a self-resetting switch connected to the power output terminal, the device main controller, and the first MOS switch; a second MOS switch connected in parallel with the first MOS switch between the power input terminal and the power output terminal and connected to the NPN switch; and a third MOS switch connected to the power input terminal and the NPN switch.
[0005] In one embodiment, the source of the first MOS switch is connected to the power input terminal, the drain of the first MOS switch is connected to the power output terminal, the gate of the first MOS switch is connected to the collector of the NPN switch, the emitter of the NPN switch is grounded, the base of the NPN switch is connected to the power output terminal, the device main controller, and the drain of the third MOS switch, the gate of the second MOS switch is connected to the power input terminal, the collector of the NPN switch, and the reset switch, the source of the second MOS switch is grounded, and the drain of the second MOS switch is connected to the power output terminal.
[0006] In one embodiment, the first MOS switch is a PMOS transistor, and the second and third MOS switches are NMOS transistors.
[0007] In one embodiment, the self-locking power control circuit further includes at least one filter capacitor disposed on the connection line between the first MOS switch and the power output terminal, the filter capacitor being grounded.
[0008] In one embodiment, when the number of filter capacitors is greater than 1, multiple filter capacitors are connected in parallel on the connection line between the first MOS switch and the power output terminal.
[0009] In one embodiment, a first current-limiting resistor is provided on the connection line between the NPN switch and the power input terminal; a first debugging reserve resistor is provided on the connection line between the NPN switch and the power output terminal; a second current-limiting resistor is provided on the connection line between the NPN switch and the power output terminal; a second debugging reserve resistor is provided on the connection line between the second current-limiting resistor and the NPN switch; a third current-limiting resistor is provided on the connection line between the self-resetting switch and the second debugging reserve resistor; a fourth current-limiting resistor is provided on the connection line between the second MOS switch and the power output terminal; a third debugging reserve resistor is provided on the connection line between the second MOS switch and the power input terminal; a fifth current-limiting resistor is provided on the connection line between the third MOS switch and the NPN switch; and a fourth debugging reserve resistor is provided on the connection line between the third MOS switch and the power input terminal.
[0010] In one embodiment, the resistance of the second current-limiting resistor is 1k-4.7kΩ.
[0011] In one embodiment, the package size of the fourth current-limiting resistor and the fifth current-limiting resistor is not less than 1.6mm × 0.8mm.
[0012] In one embodiment, a first diode is provided on the connection line between the self-resetting switch and the second MOS switch, and a second diode is provided on the connection line between the self-resetting switch and the device main control. The cathodes of the first diode and the second diode are respectively connected to the self-resetting switch.
[0013] In one embodiment, the self-locking power control circuit further includes a pull-up resistor connected in parallel to the connection line between the second diode and the device main control, the pull-up resistor being connected to an external analog power supply.
[0014] The self-locking power control circuit based on a self-resetting switch of this invention uses a self-resetting switch to achieve the self-locking function of the power control circuit. Through linkage control with the main control unit of the equipment via the self-resetting switch and an NPN switch, the main control unit does not immediately shut off the power after the self-resetting switch is pressed. Instead, it waits for the system to complete the normal shutdown process before cutting off the power supply via the output signal fed back from the main control unit. This ensures that the equipment system shuts down correctly and reliably, avoiding system anomalies and data loss caused by the main control unit losing power before completing the normal shutdown process. Its switch control logic is more complete, providing a guarantee for the complete shutdown process and improving system stability. Due to the smaller size and lower cost of the self-resetting switch compared to the self-locking switch, the overall product cost is lower, and its structural adaptability is wider, expanding the applicable scenarios of the self-locking power control circuit. Attached Figure Description
[0015] Figure 1 This is a circuit block diagram showing the connection between the self-locking power control circuit and the main control unit of the device in one embodiment of the present invention;
[0016] Figure 2 This is a circuit diagram of the main control unit of the device in one embodiment of the present invention;
[0017] Figure 3 This is a circuit diagram of a self-locking power supply control circuit in one embodiment of the present invention. Detailed Implementation
[0018] To make the above-mentioned objects, features, and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a full understanding of this utility model. However, this utility model can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this utility model. Therefore, this utility model is not limited to the specific embodiments disclosed below.
[0019] Please see Figure 1This utility model discloses a self-locking power control circuit based on a self-resetting switch, which is low-cost, small in size, has a wider range of applications, and ensures that the system shuts down in a correct and reliable manner. This self-locking power control circuit is connected to the device's main controller 10 and is used to control the connection and disconnection between the power input terminal and the power output terminal. The device's main controller 10 is connected to the power output terminal and is used to receive input signals and generate output signals. The self-locking power control circuit includes a first MOS switch 100 connected between the power input terminal and the power output terminal and used to output the input signal; an NPN switch 200 connected to the first MOS switch 100, the power input terminal, the power output terminal, and the device's main controller 10 to receive the output signal; a self-resetting switch 300 connected to the power output terminal, the device's main controller 10, and the first MOS switch 100; a second MOS switch 400 connected in parallel with the first MOS switch 100 between the power input terminal and the power output terminal and connected to the NPN switch 200; and a third MOS switch 500 connected to the power input terminal and the NPN switch 200. In this embodiment, the second MOS switch 400 is also connected to the self-resetting switch 300.
[0020] In this embodiment, the device master controller 10 is the main controller of the controlled device, used to control the device system's power-on and power-off processes. For details, please refer to... Figure 1-3 , Figure 2 U6008 in this embodiment refers to the device master controller 10. ShutDown_IN is the control signal input from the self-resetting switch 300 to the device master controller 10, i.e., the input signal; ShutDown_OUT is the control signal output from the device master controller 10, i.e., the output signal; VBAT is the power input terminal, and SYS is the power output terminal. In this embodiment, pin 29 of the device master controller U6008 is the power detection pin, pins 36 and 37 are power input pins, pins 30, 35, and 38 are GND pins (ground pins), and pins 1 and 2 are GPIO pins, which can be used as signal input and output pins, with pin 1 being the input pin and pin 2 being the output pin. In one embodiment, the device master controller 10 includes a power input terminal (pins 36 and 37) and a signal input terminal (pin 29) connected to the power output terminal, respectively. Multiple grounded capacitors are connected in parallel between the power input terminal and the power output terminal, and between the signal input terminal and the power output terminal. Specifically, between the power input terminal and the power output terminal, there are grounded capacitors 3C78, 3C77, and 3C76 connected in parallel in sequence, and between the signal input terminal and the power output terminal, there are grounded capacitors 3C75, 3C74, and 3C73 connected in parallel in sequence.
[0021] NPN switch 200 ( Figure 3The transistor 6Q9 in this example refers to a circuit design that uses an NPN bipolar junction transistor (BJT) as an electronic switch. Its core function is to control the base current, causing the transistor to switch between the cutoff region (off) and the saturation region (on), thereby controlling the on / off state of the load circuit. A self-resetting switch is a switch that automatically returns to its initial state after the external force disappears. It typically contains a spring or other elastic element. When an external force (such as pressing or flicking) is applied, the switch contacts close or open; after the external force disappears, the spring returns the contacts to their original position. Preferably, the self-resetting switch 300 in this embodiment (i.e., Figure 3 In the diagram, k2 is a toggle switch. Pins 3 and 4 of the self-resetting switch k2 are connected to ground (GND) to provide a low-level signal to the self-resetting switch 300. When the self-resetting switch 300 is pressed, its pins 1 and 2 are turned on.
[0022] In one embodiment, the source of the first MOS switch 100 is connected to the power input terminal, the drain of the first MOS switch 100 is connected to the power output terminal, the gate of the first MOS switch 100 is connected to the collector of the NPN switch 200, the emitter of the NPN switch 200 is grounded, the base of the NPN switch 200 is connected to the power output terminal, the device master controller 10, and the drain of the third MOS switch 500, the gate of the second MOS switch 400 is connected to the power input terminal, the collector of the NPN switch 200, and the reset switch 300, the source of the second MOS switch 400 is grounded, and the drain of the second MOS switch 400 is connected to the power output terminal.
[0023] In addition, in this embodiment, the first MOS switch 100 (i.e. Figure 3 The 1Q31 in the circuit is a PMOS transistor used to control the conduction between the power input terminal (VBAT) and the power output terminal (SYS). The self-locking power control circuit also includes at least one filter capacitor (i.e., ...) located on the connection line between the first MOS switch 100 (1Q31) and the power output terminal (SYS). Figure 3 The filter capacitor (3C72 in the original text) is grounded to filter the power signal between the power input and power output terminals. Furthermore, when the number of filter capacitors is greater than one, multiple filter capacitors are connected in parallel on the connection line between the first MOS switch 100 and the power output terminal to improve the filtering effect. The second MOS switch 400 (i.e., Figure 3 The 3Q4) and the third MOS switch 500 (i.e. Figure 3 In this context, 3Q5) is an NMOS transistor. The second MOS switch 400 is used to quickly discharge the remaining voltage at the power output terminal (SYS) after power-off, and the third MOS switch 500 is used to pull down the base of NPN switch 200 during power-off, thus turning off NPN switch 200. NPN switch 200 (i.e....) Figure 3The 6Q9 in the NPN switch is crucial for the power-off function. When the base of the NPN switch 200 is pulled low, the NPN switch 200 is no longer conducting, thus making the gate of the first MOS switch 100 (1Q31) high, which cuts off the voltage at the power output terminal (SYS). When the NPN switch 200 is powered on, it is continuously conducted by the voltage fed back from the power output terminal (SYS). After the device master controller 10 outputs ShutDown_OUT at a low level (the ShutDown_OUT signal pin needs to be connected to the OD gate of the device master controller 10), the base of the NPN switch 200 is simultaneously pulled low by both the device master controller 10 and the third MOS switch 500 (3Q5), ensuring that the NPN switch 200 will no longer conduct.
[0024] In one embodiment, the NPN switch 200 (i.e. Figure 3 The connection line between the 6Q9 and the power input terminal (VABT) is equipped with a first current-limiting resistor (i.e., Figure 3 The resistor 6R32 in the first current-limiting resistor is used as a current-limiting resistor when the NPN switch 200 is turned on; the connection line between the NPN switch 200 and the power output terminal (SYS) is provided with a first debugging reserved resistor (i.e. Figure 3 The resistor 6R33 in the circuit provides an interface for adjusting circuit parameters to avoid repeated modifications to the circuit structure. A second current-limiting resistor (i.e., 6R33) is provided on the connection line between the NPN switch 200 and the power output terminal. Figure 3 The resistor in the middle is 6R37), and the second current-limiting resistor is provided with a second debugging reserved resistor (i.e., the second debugging reserved resistor) on the connection line between the second current-limiting resistor and the NPN switch 200. Figure 3 When the ShutDown_OUT signal of the main control unit 10 is input to the self-locking power control circuit (resistor 6R34 in the circuit), it is fed back to the NPN switch 200 via the second debugging reserved resistor. A third current-limiting resistor (i.e., 6R34 in the circuit) is provided on the connection line between the self-reset switch 300 and the second debugging reserved resistor. Figure 3 The resistor in the middle is 6R35); a fourth current-limiting resistor (i.e., 6R35) is provided on the connection line between the second MOS switch 400 and the power output terminal. Figure 3 The resistor 2R143 in the middle is used as the current-limiting resistor for the second MOS switch 400; a third debugging reserved resistor (i.e., Figure 3 The resistor 2R127 in the middle); a fifth current-limiting resistor (i.e., the resistor in the middle) is provided on the connection line between the third MOS switch 500 and the NPN switch 200. Figure 3 The resistor 2R144 in the circuit is used as the current-limiting resistor for the third MOS switch 500; a fourth debugging reserve resistor (i.e., ...) is provided on the connection line between the third MOS switch 500 and the power input terminal. Figure 3 (The resistor in the middle is 2R145).
[0025] Furthermore, in this embodiment, the resistance value of the second current-limiting resistor is 1k-4.7kΩ to avoid the problem of the NPN switch 200 failing to be properly pulled low due to an excessively low resistance value, thus preventing the power-off process; and to avoid the problem of the power output terminal (SYS) feeding too low a current to the base of the NPN switch 200 due to an excessively high resistance value, thus affecting the normal conduction of the NPN switch 200 and preventing the power-on process. Preferably, the resistance value of the second current-limiting resistor is 3.3kΩ. In addition, the smaller the resistance values of the fourth and fifth current-limiting resistors, the faster their discharge speed. However, excessively small resistances can lead to excessive current, which can easily affect the lifespan of the second MOS switch 400 and the third MOS switch 500. In this embodiment, the package size of the fourth and fifth current-limiting resistors is not less than 1.6mm × 0.8mm (i.e., the package size is not less than 0603), the length of the package is not less than 1.6mm, and the width is not less than 0.8mm, in order to avoid resistor burnout caused by insufficient power of the fourth and fifth current-limiting resistors.
[0026] In one embodiment, a first diode (i.e., ...) is provided on the connection line between the self-resetting switch 300 and the second MOS switch 400. Figure 3 The diode 2D11 in the circuit is provided, and a second diode (i.e., diode 2D11) is provided on the connection line between the self-resetting switch 300 and the main control unit 10 of the equipment. Figure 3 The first diode (2D12) and the cathodes of the second diode are respectively connected to the self-locking switch 300. In this embodiment, by setting the first and second diodes, reverse current flow is prevented, so that the ShutDown_IN terminal (output terminal of the self-locking power control circuit) can correctly identify the pull-down signal (closed signal) of the self-locking switch k2, and at the same time, the second MOS switch 400 and the third MOS switch 500 can be turned on normally according to their functions. In addition, the self-locking power control circuit also includes a pull-up resistor (i.e., ...) connected in parallel on the connection line between the second diode and the device main control 10. Figure 3 The resistor 2R147 in the circuit is connected to an external analog power supply. A stable initial high level is provided for the ShutDown_IN terminal by connecting a pull-up resistor in parallel with the connection line between the second diode and the device master control 10.
[0027] When the reset switch 300 is pressed, the gate of the first MOS switch 100, which controls the power input and power output terminals, is pulled down to ground, thus turning it on and connecting the power input and power output terminals. After turning on, the power output terminal feeds a signal to the NPN switch 200 (i.e., the NPN transistor), causing the NPN switch 200 to turn on. Once the NPN switch 200 is on, the gate of the first MOS switch 100 is pulled low again. At this point, even if the reset switch 300 is released, the first MOS switch 100 remains on, thus eliminating the need to continuously press the reset switch 300 to maintain system power. During this process, the power input at the power output terminal (SYS) is filtered by capacitors 3C78, 3C77, and 3C76 before flowing into pins 36 and 37 of the device's main controller U6008, providing power to the device's main controller U6008. Simultaneously, the power input at the power output terminal (SYS) is filtered sequentially by capacitors 3C75, 3C74, and 3C73 before flowing into pin 29 of the device's main controller U6008. When the main controller 10 detects power on this pin, it indicates a power-on readiness state, allowing the main controller 10 to control system startup. Pins 30, 35, and 38 provide reference levels for the main controller 10.
[0028] When the self-resetting switch 300 is pressed again, the first MOS switch 100 (i.e. Figure 3 The 1Q31 outputs the ShutDown_IN signal to pin 1 of the device master controller U6008, notifying the device master controller 10 that after completing the shutdown process, the device master controller 10 outputs the ShutDown_OUT signal through pin 2 and feeds it back to the NPN switch 200 (i.e., ...). Figure 3 The transistor 6Q9 in the middle controls the first MOS switch 100 between the power input terminal and the power output terminal to turn off, thereby turning off the power output to the device main controller 10 (i.e. the power output terminal signal SYS).
[0029] The self-locking power control circuit based on the self-resetting switch 300 of this utility model implements the self-locking function of the power control circuit using the self-resetting switch 300. Through the linkage control of the self-resetting switch 300 and the NPN switch 200 with the main control unit 10, after the self-resetting switch 300 is pressed, the main control unit 10 does not immediately shut off the power, but waits for the system to complete the normal shutdown process before controlling the power supply to be cut off through the output signal fed back by the main control unit 10. This ensures that the equipment system shuts down in a correct and reliable manner, avoiding system anomalies and data loss caused by the main control unit 10 losing power before completing the normal shutdown process. Its switch control logic is more complete, providing a guarantee for the complete shutdown process of the system and improving system stability. Due to the smaller size and lower cost of the self-resetting switch 300 compared to the self-locking switch, the overall product cost is lower, and the structural adaptability is wider, expanding the applicable scenarios of the self-locking power control circuit.
[0030] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0031] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.
Claims
1. A self-locking power control circuit based on a self-resetting switch, connected to a device main controller and used to control the connection and disconnection between the power input terminal and the power output terminal, wherein the device main controller is connected to the power output terminal and used to receive input signals and generate output signals, characterized in that, The self-locking power control circuit includes a first MOS switch connected between the power input terminal and the power output terminal and used to output the input signal; an NPN switch connected to the first MOS switch, the power input terminal, the power output terminal, and the device main controller to access the output signal; a self-resetting switch connected to the power output terminal, the device main controller, and the first MOS switch; a second MOS switch connected in parallel with the first MOS switch between the power input terminal and the power output terminal and connected to the NPN switch; and a third MOS switch connected to the power input terminal and the NPN switch.
2. The self-locking power supply control circuit according to claim 1, characterized in that, The source of the first MOS switch is connected to the power input terminal, the drain of the first MOS switch is connected to the power output terminal, the gate of the first MOS switch is connected to the collector of the NPN switch, the emitter of the NPN switch is grounded, the base of the NPN switch is connected to the power output terminal, the device main control, and the drain of the third MOS switch, the gate of the second MOS switch is connected to the power input terminal, the collector of the NPN switch, and the reset switch, the source of the second MOS switch is grounded, and the drain of the second MOS switch is connected to the power output terminal.
3. The self-locking power supply control circuit according to claim 1, characterized in that, The first MOS switch is a PMOS transistor, and the second and third MOS switches are NMOS transistors.
4. The self-locking power supply control circuit according to claim 1, characterized in that, It also includes at least one filter capacitor disposed on the connection line between the first MOS switch and the power output terminal, the filter capacitor being grounded.
5. The self-locking power supply control circuit according to claim 4, characterized in that, When the number of filter capacitors is greater than 1, multiple filter capacitors are connected in parallel on the connection line between the first MOS switch and the power output terminal.
6. The self-locking power supply control circuit according to claim 1, characterized in that, The connection line between the NPN switch and the power input terminal is provided with a first current-limiting resistor; the connection line between the NPN switch and the power output terminal is provided with a first debugging reserve resistor; the connection line between the NPN switch and the power output terminal is provided with a second current-limiting resistor; the connection line between the second current-limiting resistor and the NPN switch is provided with a second debugging reserve resistor; the connection line between the self-resetting switch and the second debugging reserve resistor is provided with a third current-limiting resistor; the connection line between the second MOS switch and the power output terminal is provided with a fourth current-limiting resistor; the connection line between the second MOS switch and the power input terminal is provided with a third debugging reserve resistor. A fifth current-limiting resistor is provided on the connection line between the third MOS switch and the NPN switch, and a fourth debugging reserve resistor is provided on the connection line between the third MOS switch and the power input terminal.
7. The self-locking power supply control circuit according to claim 6, characterized in that, The resistance of the second current-limiting resistor is 1kΩ-4.7kΩ.
8. The self-locking power supply control circuit according to claim 6, characterized in that, The package size of the fourth and fifth current-limiting resistors shall not be less than 1.6mm × 0.8mm.
9. The self-locking power supply control circuit according to claim 1, characterized in that, A first diode is provided on the connection line between the self-resetting switch and the second MOS switch, and a second diode is provided on the connection line between the self-resetting switch and the main control unit of the equipment. The cathodes of the first diode and the second diode are respectively connected to the self-resetting switch.
10. The self-locking power supply control circuit according to claim 9, characterized in that, It also includes a pull-up resistor connected in parallel to the connection line between the second diode and the main control unit of the device, and the pull-up resistor is connected to an external analog power supply.