Display substrate and display panel

Abstract

The utility model provides a display substrate and a display panel, and relates to the technical field of display, the display substrate comprises a display area and a peripheral area located on one side of the display area, the peripheral area comprises a plurality of first signal lines, each first signal line comprises a first line segment, a second line segment and a patch cord located between the first line segment and the second line segment, and the first line segment and the second line segment are arranged on different layers; the extension directions of the first line segment and the second line segment are consistent, and the extension direction of the patch cord intersects with the first line segment and the second line segment; the line width of the patch cord is larger than that of the first line segment and that of the second line segment, and the patch cord is provided with at least one connection via hole used for electrically connecting the first line segment and the second line segment. The frame of the display substrate is narrow, the yield is high, and the display effect is good.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate and a display panel. Background Technology

[0002] With the rapid development of OLED (Organic Light-Emitting Diode) display technology, people have increasingly higher requirements for the characteristics of OLED display products. In addition, as display products become thinner and smaller, the bezel width of display panels is also gradually narrowing.

[0003] However, as the bezel width of display panels decreases, the wiring space is drastically compressed, making it easy to encounter problems where the bezel width and manufacturing process (such as short circuits caused by metal residue) cannot be balanced. Utility Model Content

[0004] The embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, embodiments of this application provide a display substrate, which includes a display area and a peripheral area located on one side of the display area.

[0006] The surrounding area includes multiple first signal lines, each first signal line including a first segment and a second segment disposed in different layers, and a connector connecting the first segment and the second segment;

[0007] The first line segment and the second line segment extend in the same direction, and the extension direction of the adapter line intersects with the first line segment and the second line segment respectively;

[0008] The adapter cable has a wire width greater than that of the first and second wire segments, and the adapter cable is provided with at least one connection via for electrically connecting the first and second wire segments.

[0009] In some display substrates provided in the embodiments of this application, at least some of the connection vias have a maximum width greater than the line width of the first line segment or the second line segment.

[0010] In some display substrates provided in embodiments of this application, at least a portion of the minimum width of the connecting vias is greater than the line width of a portion of the first line segment and greater than the line width of a portion of the second line segment.

[0011] In some display substrates provided in the embodiments of this application, the horizontal distance between two adjacent connecting vias is greater than the line width of the first line segment or the line width of the second line segment.

[0012] In some display substrates provided in the embodiments of this application, the adapter cable is disposed on the same layer as the first line segment; and / or, the adapter cable is disposed on the same layer as the second line segment.

[0013] In some display substrates provided in the embodiments of this application, the orthographic projections of any two adjacent adapter lines on the substrate of the display substrate do not overlap.

[0014] In some display substrates provided in embodiments of this application, the peripheral region includes an organic layer disposed on the substrate, the organic layer including at least one groove, and the orthographic projection of a portion of the first signal line on the substrate overlaps with the orthographic projection of the area enclosed by the outer contour of the groove on the substrate.

[0015] In some display substrates provided in the embodiments of this application, the orthographic projection of a portion of the adapter line on the substrate overlaps with the orthographic projection of the area enclosed by the outer contour of the groove on the substrate, and the extension direction of the groove intersects with the extension direction of the adapter line.

[0016] In some display substrates provided in the embodiments of this application, the orthographic projection of some of the connecting vias on the substrate falls within the area enclosed by the outer contour of the groove on the substrate, while the orthographic projection of some of the connecting vias on the substrate falls outside the area enclosed by the outer contour of the groove on the substrate.

[0017] In some display substrates provided in the embodiments of this application, there is at least one of the connection vias, the orthographic projection of which overlaps with the orthographic projection of the area enclosed by the outer contour of the groove on the substrate.

[0018] In some display substrates provided in the embodiments of this application, the organic layer includes at least two grooves, a partition dam is provided between the two grooves, a portion of the adapter wire is provided on the side of the partition dam away from the substrate, and the length of the adapter wire on the side of the partition dam away from the substrate is greater than the length of the adapter wire located in the groove.

[0019] In some display substrates provided in the embodiments of this application, the orthographic projection of some of the connecting vias on the substrate overlaps with the orthographic projection of the barrier dam on the substrate;

[0020] Among the overlapping connecting through holes of the partition dam, at least a portion of the connecting through holes have a length along the direction perpendicular to the extension of the partition dam that is greater than or equal to the length of the outer contour of the groove in the area where the overlapping connecting through holes have a length along the same direction.

[0021] In some display substrates provided in the embodiments of this application, the area where the connecting via overlaps with the barrier dam includes a first area and a second area located on both sides of the first area;

[0022] The length of the connecting via in the first region along the direction perpendicular to the extension of the barrier dam is greater than the length of the connecting via in the second region along the direction perpendicular to the extension of the barrier dam, and the dimension of the connecting via in the first region along the width direction of the barrier dam is smaller than the width of the barrier dam.

[0023] In some display substrates provided in embodiments of this application, the connection via in the second region is disposed at 1 / 3 of the width of the partition dam.

[0024] In some display substrates provided in embodiments of this application, a portion of the first line segment and / or a portion of the second line segment are disposed on the side of the partition dam away from the substrate and are electrically connected to the connection via in the second region;

[0025] The first and second wire segments of the connecting via electrical connection in the first region are respectively disposed in the grooves on both sides of the barrier dam.

[0026] In some display substrates provided in the embodiments of this application, the extending direction of the connecting via in the overlapping area of ​​the partition dam intersects with the extending direction of the connecting via in the overlapping area of ​​the groove.

[0027] In some display substrates provided in the embodiments of this application, the extending direction of the connecting via in the overlapping area of ​​the partition dam intersects with the extending direction of the partition dam, and the extending direction of the connecting via in the overlapping area of ​​the groove is consistent with the extending direction of the groove.

[0028] In some display substrates provided in embodiments of this application, the number of first signal lines disposed on the partition dam along the width direction of the partition dam is less than the number of first signal lines disposed in the groove along the width direction of the groove.

[0029] In some display substrates provided in the embodiments of this application, the line width of the adapter cable is greater than or equal to twice the line width of the first line segment or the second line segment.

[0030] Secondly, embodiments of this application provide a display panel including a display substrate as described in any one of the first aspects.

[0031] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1A A partial top view of a display panel in a related art provided for an embodiment of this application;

[0034] Figure 1B A top view of a display panel in another related technology provided for an embodiment of this application;

[0035] Figure 2 for Figure 1A or Figure 1B A magnified view of a portion within the dashed ellipse;

[0036] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure along the M1M2 direction;

[0037] Figure 4 A top view of the wiring structure of the peripheral area of ​​a display substrate provided for an embodiment of this application;

[0038] Figure 5 A top view of the second type of display substrate peripheral area wiring provided for embodiments of this application;

[0039] Figure 6 A top view of the wiring structure of the peripheral area of ​​a display substrate provided in an embodiment of this application;

[0040] Figure 7A A top view of the fourth type of display substrate peripheral area wiring provided in the embodiments of this application;

[0041] Figure 7B for Figure 7A A schematic diagram of the cross-sectional structure along the M3M4 direction;

[0042] Figure 7C for Figure 7A A schematic diagram of the cross-sectional structure along the M5M6 direction;

[0043] Figure 7D for Figure 7A A schematic diagram of the cross-sectional structure along the M7M8 direction;

[0044] Figure 8 This is a schematic diagram of a cross-sectional structure in the display area of ​​a display substrate, provided as an embodiment of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0047] In the embodiments of this application, the use of terms such as "first" and "second" to describe the same or similar items with essentially the same function and effect is only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0048] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. "At least one" refers to one or more, and "more than one" refers to at least two.

[0049] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0050] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0051] With the continuous development of display technology, Organic Light-Emitting Diode (OLED) displays have become a research hotspot and technological development direction for major manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-emissive nature, and wide viewing angle. Currently, OLED displays are widely used in various electronic products, from small items like smart bracelets, smartwatches, smartphones, and tablets to large items like laptops, desktop computers, and televisions. Therefore, the market demand for active-matrix OLED displays is increasingly strong.

[0052] In recent years, OLED display products have undergone rapid upgrades, and the market's pursuit of product aesthetics has led to a trend of increasingly narrower bezels on mobile phones. At the same time, as display products move towards thinner and smaller designs, higher demands are placed on the design of display panel bezels. In particular, the significantly narrower bottom bezel of the display panel results in a substantial reduction in the wiring space within the bottom bezel of the TSP (Touch Screen Panel).

[0053] However, to balance wiring space and resistance differences between signal lines of varying lengths, conventional jumper hole placement methods are highly susceptible to short circuits caused by metal residue, seriously threatening the normal operation of the display panel. Furthermore, the probability of short circuits due to metal residue increases dramatically when jumper holes are located near the OLED tray. Therefore, how to rationally consider the placement of jumper holes within limited wiring space, ensuring both low short-circuit risk and touch accuracy, has become a critical issue that urgently needs to be addressed in the current OLED touch product field.

[0054] Figure 1Aand Figure 1B Top view structural diagrams of two display panels in related technologies are provided. Figure 2 for Figure 1A or Figure 1B An enlarged illustration within the dashed ellipse. Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure along the M1M2 direction. Figure 3 As can be seen, an insulating layer 20 is disposed between two adjacent metal layers. In related technologies, such as... Figure 2 As shown, the touch signal line (TX) or display drive signal line (RX) in the fan-out area B1 uses a double-layer metal alternating routing method to overcome the problems of high routing density and large resistance differences between different signal lines. Specifically, at the jumper positions of the two metal routing layers, they are electrically connected via vias. The two line segments that need to be electrically connected via the jumper usually extend in the same direction and have a partial overlap area, which is where the jumper via is located. However, as the width of the display panel bezel decreases, the wiring space is drastically compressed. The line width of the two line segments electrically connected via the jumper is reduced, and the space and size for setting the jumper via are also compressed. This makes it very easy for material residues, such as metal residues, to appear near the jumper via location due to poor etching during actual manufacturing. This can easily lead to short circuits in subsequent processes.

[0055] Based on this, embodiments of this application provide a display substrate and a display panel. The display substrate includes a display area and a peripheral area located on one side of the display area. The peripheral area includes a plurality of first signal lines. The first signal lines include first line segments and second line segments disposed in different layers, and a transition line located between the first line segments and the second line segments. The extension directions of the first line segments and the second line segments are consistent, and the extension directions of the transition line intersect the first line segments and the second line segments respectively. The line width of the transition line is greater than the line width of the first line segments and the second line segments, and at least one connection via is provided on the transition line for electrically connecting the first line segments and the second line segments.

[0056] In the embodiments of this application, by setting an adapter line that intersects with the first line segment and the second line segment, and setting the line width of the adapter line to be greater than the line width of the first line segment and the second line segment, and setting at least one connecting via on the adapter line, on the one hand, since the extension directions of the first line segment and the second line segment are consistent, and the extension directions of the adapter line intersect with the first line segment and the second line segment respectively, setting the connecting via on the adapter line does not increase the size and design space of the first line segment and the second line segment along their width direction, which can ensure a narrower width of the peripheral area, which is beneficial to the manufacture of narrow-bezel display products; on the other hand, since the line width of the adapter line is greater than the line width of the first line segment and the second line segment, the extension direction of the adapter line intersects with the first line segment and the second line segment respectively, setting the connecting via on the adapter line does not increase the size and design space of the first line segment and the second line segment along their width direction, which can ensure a narrower width of the peripheral area, which is beneficial to the manufacture of narrow-bezel display products; The width is greater than that of the first and second line segments. The connection vias on the adapter have more flexible design space and size, thus avoiding process defects (such as material residue when opening) caused by small connection via size or limited design position. On the other hand, the jumper design between different film layers makes the length difference between different first signal lines 1 smaller. Due to the high size flexibility of the connection vias Via, the contact resistance difference between different first signal lines 1 is small, thus making the resistance difference between the first signal lines 1 smaller and enabling high-precision touch control.

[0057] The display substrate and display panel provided in the embodiments of this application will now be described and introduced in detail with reference to the accompanying drawings.

[0058] Embodiments of this application provide a display substrate, including a display area AA and a peripheral area BB located on one side of the display area AA, wherein the peripheral area BB includes a fan-out area B1.

[0059] like Figure 4 As shown, the peripheral area BB (fan-out area B1) includes multiple first signal lines 1. Each first signal line 1 includes a first segment 11 and a second segment 12 arranged in different layers, and a connector 13 connecting the first segment 11 and the second segment 12. The extension directions of the first segment 11 and the second segment 12 are consistent, and the extension directions of the connector 13 intersect the first segment 11 and the second segment 12 respectively. The line width d1 of the connector 13 is greater than the line widths (d2 and d3) of the first segment 11 and the second segment 12. The connector 13 is provided with at least one connection via Via for electrically connecting the first segment 11 and the second segment 12.

[0060] In this context, "different layer arrangement" refers to the first line segment 11 and the second line segment 12 being located on different conductive layers (e.g., on metal layers M1 and M2 respectively). The different conductive layers are isolated by an insulating layer, but the first line segment 11 and the second line segment 12 maintain the same extension direction (e.g., both are horizontal or vertical). This design avoids congestion in wiring on the same layer and reduces signal crosstalk.

[0061] For example, the first signal line 1 can be a first touch signal line TX and / or a second touch signal line RX.

[0062] For example, the first segment 11 and the second segment 12 are disposed on adjacent conductive layers. For instance, the M1 metal layer and the M2 metal layer are disposed adjacent to each other, and there are no other conductive layers between them, but rather an insulating layer.

[0063] In exemplary embodiments, a single-layer molybdenum (Mo), a stacked molybdenum / aluminum / molybdenum (Mo / Al / Mo), a stacked titanium / aluminum / titanium (Ti / Al / Ti), a double-layer molybdenum / niobium / copper (MoNb / Cu), a double-layer molybdenum / niobium / titanium / copper (MoNiTi / Cu), or a double-layer titanium / copper (Ti / Cu) can be used as the aforementioned metal layer.

[0064] In an exemplary embodiment, the materials of the M1 metal layer and the M2 metal layer can be the same.

[0065] It should be noted that the direction of extension refers to the extension trend of the routing, and does not represent a restriction on the shape of the routing. For example, the routing can be a straight line; for another example, the routing can be a diagonal line; for yet another example, the routing can be a stepped line; and for yet another example, the routing can be an arc line.

[0066] Since the extension directions of the first line segment 11 and the second line segment 12 are consistent, when the extension direction of the adapter 13 intersects the first line segment 11 and the second line segment 12 respectively, the following situations may occur: for example, the extension direction of the adapter 13 is perpendicular to the extension directions of the first line segment 11 and the second line segment 12 respectively; or for example, there is a preset angle between the extension direction of the adapter 13 and the extension directions of the first line segment 11 and the second line segment 12 respectively, and the angle between the adapter 13 and the first line segment 11 is approximately equal to the angle between the adapter 13 and the second line segment 12.

[0067] The line width d1 of the adapter cable 13 is greater than the line widths (d2 and d3) of the first segment 11 and the second segment 12, and the line width d1 of the adapter cable 13 is greater than the length or width of the connecting via Via.

[0068] There is no limitation on whether the line widths (d2 and d3) of the first line segment 11 and the second line segment 12 are equal.

[0069] For example, the line width d3 of the first line segment 11 and the line width d2 of the second line segment 12 can both be in the range of 3 micrometers to 4 micrometers.

[0070] In some embodiments, the line width d3 of the first line segment 11 is approximately equal to the line width d2 of the second line segment 12.

[0071] In an exemplary embodiment, the via can be filled with a conductive material, such as tungsten (W).

[0072] The shape of the aforementioned connecting via is not limited here. For example, the shape of the connecting via can be an arc, a polygon, or a combination of an arc and a polygon.

[0073] Among them, the arc shape can include a circle or an ellipse, and the polygon can include a quadrilateral, a pentagon, a hexagon, or an octagon, etc. The combination of arc shape and polygon refers to the shape formed by splicing arc shape and polygon or the shape formed by removing part of the area from arc shape and polygon.

[0074] In the embodiments of this application, such as Figure 4 or Figure 5 As shown, by setting an adapter line 13 that intersects with the first line segment 11 and the second line segment 12, and setting the line width d1 of the adapter line 13 to be greater than the line widths (d2 and d3) of the first line segment 11 and the second line segment 12, and setting at least one connecting via Via on the adapter line 13, on the one hand, since the extension directions of the first line segment 11 and the second line segment 12 are consistent, and the extension directions of the adapter line 13 intersect with the first line segment 11 and the second line segment 12 respectively, setting the connecting via Via on the adapter line 13 does not increase the size and design space of the first line segment 11 and the second line segment 12 along their width direction, which can ensure a narrower width of the peripheral area BB, which is beneficial to the manufacture of narrow bezel display products. On the other hand, since the line width of the adapter cable 13 is greater than that of the first segment 11 and the second segment 12, the connection vias provided on the adapter cable 13 have more flexible design space and design size, thereby avoiding process defects caused by the small size or limited design position of the connection vias (such as material residue when opening holes); furthermore, through the jumper design between different film layers, the length difference between different first signal lines 1 is small. Due to the high size flexibility of the connection vias, the contact resistance difference between the connection vias of different first signal lines 1 is small, thereby making the resistance difference between the first signal lines 1 small, which can achieve high-precision touch control.

[0075] In some display substrates provided in the embodiments of this application, at least some of the connecting vias have a maximum planar dimension greater than the line width of the first line segment 11 or the second line segment 12.

[0076] It should be noted that the maximum planar dimension of the connection via refers to the maximum width of the connection via in the direction parallel to the substrate. For example, when the connection via is a polygon, its maximum width can be the diagonal of the polygon or the side length of the longer side of the polygon.

[0077] In some display substrates provided in the embodiments of this application, combined with Figure 4 and Figure 7AAs shown, at least part of the maximum width d5 ​​of the connecting via is greater than the line width d3 of the first line segment 11 or the line width d2 of the second line segment 12.

[0078] In this case, of course, there may also be some planar dimensions (e.g., minimum width) of the connecting via Via that are less than or equal to the line width d3 of the first line segment 11; there may also be some planar dimensions (e.g., minimum width) of the connecting via Via that are less than or equal to the line width d2 of the second line segment 12.

[0079] "At least partially" includes partially connected vias or fully connected vias. For example, the maximum planar dimension (e.g., maximum width d5) of a partially connected via is greater than the line width of the first segment 11 or the second segment 12; or, for example, the maximum planar dimension (e.g., maximum width d5) of a fully connected via is greater than the line width of the first segment 11 or the second segment 12.

[0080] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, the minimum width d6 of at least part of the connecting via Via is greater than the line width d3 of part of the first line segment 11, and greater than the line width d2 of part of the second line segment 12.

[0081] It should be noted that the minimum width of a connection via refers to the minimum width of the connection via along a direction parallel to the substrate. For example, when the connection via is polygonal, its minimum width can be the length of the shorter diagonal or the side length of the shorter side of the polygon. For example, as... Figure 7A As shown, when the connecting via is rectangular, its minimum width can be the length d6 of the rectangle's width.

[0082] In an exemplary embodiment, the planar dimensions of the connection via Via on the adapter cable 13 are greater than or equal to 5μm*10μm. For example, the planar dimensions of the connection via Via can be 9μm*12μm.

[0083] It should be noted that the minimum distance between the edge of the adapter cable 13 and the edge of the connection via Via must be greater than or equal to 2.5 μm, so as to satisfy the relationship that the adapter cable 13 surrounds the connection via Via, and to enable the connection via Via to be properly opened on the adapter cable 13 during the manufacturing process without damaging the adapter cable 13.

[0084] In an exemplary embodiment, the line width d3 of the first line segment 11 and the line width d2 of the second line segment 12 can both be in the range of 3μm to 4μm. For example, the line width d3 of the first line segment 11 and the line width d2 of the second line segment 12 can both be 3.5μm.

[0085] In the embodiments of this application, such as Figure 4As shown, by setting the line width d1 of the adapter line 13 to be greater than the line widths (d2 and d3) of the first line segment 11 and the second line segment 12, at least one connecting via is set on the adapter line 13. In this way, the design size of the connecting via can be increased without increasing the line width of the first line segment 11 and the second line segment 12 or the width of the lower bezel of the display substrate. This reduces the manufacturing difficulty of the connecting via and avoids problems such as poor opening and material residue caused by the small size of the connecting via.

[0086] In some display substrates provided in the embodiments of this application, such as Figure 4 As shown, the horizontal distance d4 between two adjacent connecting vias is greater than the line width d3 of the first line segment 11 or the line width d2 of the second line segment 12.

[0087] The statement that the horizontal distance d4 between two adjacent connecting vias is greater than the line width d3 of the first line segment 11 or the line width d2 of the second line segment 12 means, for example, that the horizontal distance d4 between two adjacent connecting vias is greater than the line width d3 of the first line segment 11; or, for example, that the horizontal distance d4 between two adjacent connecting vias is greater than the line width d2 of the second line segment 12; or, for example, that the horizontal distance d4 between two adjacent connecting vias is greater than the line width d3 of the first line segment 11 and the horizontal distance d4 between two adjacent connecting vias is greater than the line width d2 of the second line segment 12.

[0088] For example, the minimum distance d4 between two adjacent connecting vias Via is greater than or equal to 15 μm.

[0089] In some examples, in at least a portion of the display substrate, the minimum distance d4 between two adjacent connecting vias Via can be greater than or equal to the line width d1 of the adapter cable 13.

[0090] In the embodiments of this application, by setting the horizontal distance d4 between two adjacent connecting vias to be greater than the line width d3 of the first line segment 11 or the line width d2 of the second line segment 12, sufficient space is reserved between the two adjacent connecting vias. Since the size of the connecting vias is relatively large, it can avoid the stress change during the etching process from causing cracks in individual conductive structures in the area between the two adjacent connecting vias, thereby improving the manufacturing yield of the display substrate.

[0091] In some display substrates provided in the embodiments of this application, such as Figure 6 As shown, the adapter cable 13 is installed on the same layer as the first line segment 11; and / or, the adapter cable 13 is installed on the same layer as the second line segment 12.

[0092] In some display substrates, the adapter cable 13 can be disposed on the same layer as the first line segment 11;

[0093] In some other display substrates, the adapter cable 13 can be disposed on the same layer as the second line segment 12;

[0094] In some display substrates, such as Figure 6 As shown, some of the adapter cables 13 can be installed on the same layer as the first line segment 11, and some of the adapter cables 13 can be installed on the same layer as the second line segment 12.

[0095] In some display substrates provided in the embodiments of this application, such as Figures 4 to 7A The orthographic projections of any two adjacent adapter lines 13 onto the substrate 100 of the display substrate do not overlap.

[0096] For example, such as Figures 4 to 7A There is a gap between the orthographic projections of any two adjacent adapter lines 13 onto the substrate 100 of the display substrate.

[0097] In some areas, two adjacent adapter wires 13 are placed on the same conductive layer. They must not overlap and a gap must be provided between them, otherwise a short circuit will occur.

[0098] In some regions, adjacent transition lines 13 are disposed on different conductive layers. In this case, although an insulating layer is disposed between the two film layers, the distance is relatively close. Therefore, a gap can be provided between the orthographic projections of adjacent transition lines 13 on the substrate 100 of the display substrate; or, the edges of the orthographic projections of adjacent transition lines 13 on the substrate 100 of the display substrate can be disposed flush. In this way, parasitic capacitance can be minimized, thereby avoiding signal interference between the two first signal lines 1.

[0099] In an exemplary embodiment, in the area where the groove 2 or the partition dam 3 is located, the orthographic projections of two adjacent first line segments 11 and second line segments 12 on the substrate 100 of the display substrate do not overlap. For example, if two adjacent first line segments 11 and second line segments 12 are disposed on different conductive layers, there is a gap between the orthographic projections of two adjacent first line segments 11 and second line segments 12 on the substrate 100 of the display substrate; or, the edges of two adjacent first line segments 11 and second line segments 12 are flush. In this way, on the one hand, parasitic capacitance can be minimized, thereby avoiding signal interference between the two first signal lines 1; on the other hand, residual or short-circuit problems that would occur if overlapping first line segments 11 and second line segments 12 were fabricated on the complex terrain where the groove 2 or the partition dam 3 is located are avoided.

[0100] For example, when there is a gap between the orthographic projections of two adjacent first line segments 11 and second line segments 12 on the substrate 100 of the display substrate, the gap width can be in the range of 1 μm to 1.8 μm.

[0101] In some display substrates provided in the embodiments of this application, such as Figures 4-6 As shown, the peripheral region BB includes an organic layer disposed on the substrate 100 (for example, the organic layer includes at least one of PLN1 layer, PLN2 layer, and PDL layer). The organic layer includes at least one groove 2. The orthographic projection of a portion of the first signal line 1 on the substrate 100 overlaps with the orthographic projection of the area enclosed by the outer contour of the groove 2 on the substrate 100.

[0102] In some display substrates, combined Figure 1B As shown, at least one annular groove 2 can be provided around the display area AA. The annular groove 2 can prevent organic materials (such as photoresist, light-emitting materials, inkjet printing ink or other materials with high fluidity before curing) in the display area AA from flowing into the area where chips or other components are set in the peripheral area BB, thereby avoiding poor bonding of components or light leakage at the edge of the display area.

[0103] In an exemplary embodiment, such as Figure 1B As shown, two annular grooves 2 can be set around the display area AA.

[0104] In an exemplary embodiment, the organic layer can be a monolayer film, for example, combined with... Figure 8 As shown, the organic layer can be one of the first flattening layer 110 (PLN1), the second flattening layer 112 (PLN2), and the pixel delimiting layer 114 (PDL).

[0105] Of course, in some other embodiments, the organic layer can be a support layer PS.

[0106] In an exemplary embodiment, the organic layer may be a stacked structure comprising at least two sub-layers. For example, the organic layer may be composed of at least two of the following: a first planarization layer 110 (PLN1), a second planarization layer 112 (PLN2), and a pixel delimiting layer 114 (PDL); or, the organic layer may be composed of at least two of the following: a first planarization layer 110 (PLN1), a second planarization layer 112 (PLN2), a pixel delimiting layer 114, or a support layer PS.

[0107] in, Figure 8 This is a schematic diagram of the cross-sectional structure of the display substrate in the display area AA. At least some of the film layers in the display area AA and the peripheral area BB are the same.

[0108] In some display substrates provided in the embodiments of this application, such as Figures 4-6As shown, the orthographic projection of part of the adapter line 13 on the substrate 100 overlaps with the orthographic projection of the area enclosed by the outer contour of the groove 2 on the substrate 100, and the extension direction of the groove 2 intersects with the extension direction of the adapter line 13.

[0109] "Intersecting" can include perpendicular or oblique intersections.

[0110] For example, the extension direction of the groove 2 located on the lower side of the display area AA can be horizontal, and the extension direction of the adapter cable 13 can be vertical.

[0111] In practical applications, the extension direction of adapter cable 13 can be such that its peripheral area BB points towards the display area AA.

[0112] In some display substrates provided in the embodiments of this application, such as Figures 4-6 As shown, the orthographic projection of part of the connecting via on the substrate 100 falls within the area enclosed by the outer contour of the groove 2 on the substrate 100, while the orthographic projection of part of the connecting via on the substrate 100 falls outside the area enclosed by the outer contour of the groove 2 on the substrate 100.

[0113] In some display substrates provided in the embodiments of this application, such as Figure 4 As shown, there is at least one connecting via Via, the orthographic projection of which overlaps with the orthographic projection of the area enclosed by the outer contour of the groove 2 on the substrate 100.

[0114] For example, such as Figure 4 As shown, when the orthographic projection of a via on the substrate 100 overlaps with the area enclosed by the outer contour of the groove 2 on the substrate 100, part of the via is located inside the groove 2 and part is located outside the groove 2. In this case, the via may appear to be higher on one side than the other. However, since the via is located on the adapter line 13, and the line width of the adapter line 13 is larger than the line width of the first line segment 11 or the second line segment 12, the via at this position can be etched cleanly without any residue during the actual fabrication process. This greatly improves the problem of metal material residue that occurs when the via is located near the edge of the groove 2 in related technologies. In this way, the fabrication yield of the display substrate is improved while ensuring a narrow bezel.

[0115] In some display substrates provided in the embodiments of this application, such as Figure 7AAs shown, the organic layer includes at least two grooves 2, with a partition dam 3 disposed between the two grooves 2. A portion of the adapter wire 13 is disposed on the side of the partition dam 3 away from the substrate 100, and the adapter wire 13 located on the side of the partition dam 3 away from the substrate 100 (to avoid ambiguity)... Figure 7A The adapter cable 13 is not marked in the text. Figure 7A The length of the vertically extending traces with connecting vias is greater than the length of the adapter wire 13 located in the groove 2.

[0116] Among them, Figure 7A In the middle, the adapter wire 13 located on the side of the partition dam 3 away from the substrate 100 is wrapped in the area A marked by the dashed rectangle.

[0117] In an exemplary embodiment, such as Figure 1B As shown, two annular grooves 2 can be set around the display area AA, and a partition dam 3 can be set between the two grooves 2.

[0118] Of course, three annular grooves 2 can also be set around the display area AA, and two rings of partition dams 3 can be set between the three grooves 2.

[0119] It should be noted that when there are two rings of partition dams 3 in the display substrate, the heights of the two rings of partition dams 3 are not necessarily the same.

[0120] In some embodiments, the two rings of partition dam 3 may be set to have the same height. In other embodiments, the height of the outer ring of partition dam 3 may be greater than the height of the inner ring of partition dam 3.

[0121] For example, the dam 3 may be formed by at least one of the first flattening layer 110 (PLN1), the second flattening layer 112 (PLN2), and the pixel defining layer 114 (PDL); when the height of the outer ring dam 3 is greater than the height of the inner ring dam 3, the outer ring dam 3 may be formed by at least two of the first flattening layer 110 (PLN1), the second flattening layer 112 (PLN2), and the pixel defining layer 114 (PDL).

[0122] For example, the dam 3 may be formed by at least one of the first planarization layer 110 (PLN1), the second planarization layer 112 (PLN2), the pixel defining layer 114 (PDL), and the support layer PS; when the height of the outer ring dam 3 is greater than the height of the inner ring dam 3, the outer ring dam 3 may be formed by at least two of the first planarization layer 110 (PLN1), the second planarization layer 112 (PLN2), the pixel defining layer 114 (PDL), and the support layer PS.

[0123] In an exemplary embodiment, the length of the adapter cable 13 disposed within the groove 2 may be approximately equal to the length of the adapter cable 13 disposed outside the groove 2 (excluding the partition dam 3). It can be understood that in the region where the groove 2 and the partition dam 3 are disposed, the length of the adapter cable 13 overlapping with the partition dam 3 is greater than the length of the adapter cable 13 in other regions.

[0124] In some embodiments, the lengths of each transition line 13 that overlaps with the barrier 3 are all equal.

[0125] In some embodiments, such as Figure 7A As shown, the region A (marked by the rectangular dashed box) where the connecting via Via and the dam 3 overlap includes a first region and a second region located on both sides of the first region. The first region ( Figure 7A The length of adapter cable 13 in the area marked by the middle circle is greater than the length of adapter cable 13 in the second area.

[0126] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, the orthographic projection of a portion of the connecting via Via on the substrate 100 overlaps with the orthographic projection of the barrier dam 3 on the substrate 100; the planar dimension of the overlapping connecting via Via in the barrier dam 3 is greater than or equal to the planar dimension of the overlapping connecting via Via in the area enclosed by the outer contour of the groove 2.

[0127] For example, the planar dimensions here may include dimensions such as area, side length, width, and diagonal length.

[0128] For example, in the case of overlapping connecting vias Via in the partition dam 3, there may be a portion of the connecting via Via whose planar dimensions are larger than the planar dimensions of the connecting vias Via that overlap with the area enclosed by the outer contour of the groove 2.

[0129] For example, in the case of overlapping connecting vias Via in the partition dam 3, there may be a portion of the connecting via Via whose planar dimensions are equal to the planar dimensions of the connecting via Via that overlap with the area enclosed by the outer contour of the groove 2.

[0130] For example, in the overlapping connecting vias Via of the partition dam 3, the planar dimensions of all connecting vias Via are larger than the planar dimensions of the connecting vias Via that overlap with the area enclosed by the outer contour of the groove 2.

[0131] In some display substrates provided in the embodiments of this application, such as Figure 7AAs shown, the orthographic projection of the partial connecting via Via on the substrate 100 overlaps with the orthographic projection of the partition dam 3 on the substrate 100; for example, in region A, the partition dam 3 has overlapping connecting via Via, and at least part of the connecting via Via has a length (e.g., vertical length) d5 along the direction perpendicular to the extension of the partition dam 3 that is greater than or equal to the length d7 along the same direction of the overlapping connecting via Via in the region enclosed by the outer contour of the groove 2.

[0132] In an exemplary embodiment, the orthographic projection of a partial connecting via Via on the substrate 100 overlaps with the orthographic projection of the partition dam 3 on the substrate 100. Among the overlapping connecting via Via, the length d5 ​​of the partial connecting via Via along the direction perpendicular to the extension of the partition dam 3 (e.g., the length in the vertical direction) is greater than or equal to the length d7 of the overlapping connecting via Via along the same direction in the area enclosed by the outer contour of the groove 2.

[0133] In an exemplary embodiment, the orthographic projection of some connecting vias Via on the substrate 100 overlaps with the orthographic projection of the partition dam 3 on the substrate 100. The length d5 ​​of all overlapping connecting vias Via along the direction perpendicular to the extension of the partition dam 3 (e.g., the length in the vertical direction) is greater than or equal to the length d7 of overlapping connecting vias Via along the same direction in the area enclosed by the outer contour of the groove 2.

[0134] It should be noted that since the partition dam 3 is made of organic material, when forming the groove 2 and the partition dam 3, due to the leveling property of the organic material, the surface of the partition dam 3 away from the substrate 100 exhibits an arc shape that is high in the middle and low on both sides. At this time, a connecting via is formed in the adapter line 13 on the partition dam 3. Due to the special situation of the bottom terrain, the process of forming the connecting via is difficult, and it is easy to have poor hole opening or be unable to open the hole. By setting the planar size of the overlapping connecting vias of the partition dam 3 (e.g., the length along the direction perpendicular to the extension of the partition dam 3) to be greater than or equal to the planar size of the overlapping connecting vias of the area enclosed by the outer contour of the groove 2 (the length along the same direction), the preparation yield and process stability of the overlapping connecting vias of the partition dam 3 can be greatly improved, thereby improving the quality of the display substrate.

[0135] In some display substrates provided in the embodiments of this application, such as Figure 7AAs shown, the region A where the connecting via Via overlaps with the barrier dam 3 includes a first region Area1 (the region marked with a circle) and a second region Area2 located on both sides of the first region Area1 (the region marked with a circle). The planar dimension of the connecting via Via in the first region Area1 (the region marked with a circle) is larger than the planar dimension of the connecting via Via in the second region Area2, and the dimension of the connecting via Via in the first region Area1 (the region marked with a circle) along the width direction of the barrier dam 3 (e.g., the length in the vertical direction) is smaller than the width of the barrier dam 3.

[0136] The planar dimensions of the aforementioned connecting via can include dimensions such as area, side length, width, and diagonal length.

[0137] For example, the width of the groove 2 ranges from 20μm to 30μm.

[0138] For example, the width of the barrier 3 ranges from 20μm to 30μm.

[0139] For example, the width of the groove 2 can be approximately equal to the width of the partition dam 3.

[0140] For example, taking the connecting via as a rectangle, the first area Area1 ( Figure 7A The dimensions of the connecting vias in the circled area can be 5*15~25μm, that is, the width remains unchanged and the length ranges from 15 to 25μm.

[0141] For example, such as Figure 7A As shown, taking the connecting via Via as a rectangle as an example, the size of the connecting via Via in the groove 2 can be 5*10μm.

[0142] For example, such as Figure 7A As shown, taking the connecting via as a rectangle as an example, the size of the connecting via in the second area Area2 can be the same as the size of the connecting via in the groove 2.

[0143] In the embodiments of this application, since the partition dam 3 is made of organic material, when forming the groove 2 and the partition dam 3, due to the leveling properties of the organic material, the surface of the partition dam 3 away from the substrate 100 exhibits an arc shape that is high in the middle and low on both sides. At this time, a connecting via Via is formed in the adapter wire 13 on the partition dam 3. Due to the special topography of the bottom, such as Figure 7AAs shown, the fabrication difficulty of the connecting vias in the first area Area1 (circled area) is greater than that of the connecting vias in the second area Area2. Therefore, the planar size of the connecting vias in the first area Area1 (circled area) is set to be larger than that of the connecting vias in the second area Area2. This greatly reduces the fabrication process difficulty. In addition, it improves the fabrication yield and process stability of the connecting vias with overlapping partition dams 3, thereby improving the quality of the display substrate.

[0144] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, the connecting via in the second area Area2 is located at 1 / 3 of the width of the barrier dam 3.

[0145] In the embodiments of this application, since the surface of the barrier dam 3 away from the substrate 100 presents an arc shape that is high in the middle and low on both sides, by setting the connection vias Via in the second region Area 2 at 1 / 3 of the width of the barrier dam 3, the bottom terrain of this part of the connection vias Via is relatively flat, thereby further reducing the difficulty of the manufacturing process, improving the manufacturing yield of the connection vias Via, and thus improving the quality of the display substrate.

[0146] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, a portion of the first line segment 11 and / or a portion of the second line segment 12 are disposed on the side of the barrier dam 3 away from the substrate 100, and are electrically connected to the Via connection via in the second region Area 2 (the region A marked by the rectangular dashed box and the region outside the circle); the first line segment 11 and the second line segment 12 electrically connected to the Via connection via in the first region Area 1 (the region marked by the circle) are respectively disposed in the grooves 2 on both sides of the barrier dam 3.

[0147] The partial arrangement of the first segment 11 and / or the partial arrangement of the second segment 12 on the side of the partition dam 3 away from the substrate 100 includes the following cases:

[0148] First, a portion of the first line segment 11 is located on the side of the partition dam 3 away from the substrate 100;

[0149] Second, part of the second line segment 12 is set on the side of the partition dam 3 away from the substrate 100;

[0150] Third, a portion of the first line segment 11 is disposed on the side of the partition dam 3 away from the substrate 100, and a portion of the second line segment 12 is disposed on the side of the partition dam 3 away from the substrate 100.

[0151] In practical applications, in order to reduce the difficulty of design and fabrication processes, the line segments on the side of the barrier dam 3 away from the substrate 100 can all be the first line segment 11; or, the line segments on the side of the barrier dam 3 away from the substrate 100 can all be the second line segment 12.

[0152] The appendix provided in the embodiments of this application Figure 7A In the example, a portion of the first line segment 11 is set on the side of the partition dam 3 away from the substrate 100. That is, the line segments on the side of the partition dam 3 away from the substrate 100 are all the first line segment 11.

[0153] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, in the overlapping area A of the partition dam 3, the extension direction of the connecting through hole Via intersects with the extension direction of the connecting through hole Via in the overlapping area of ​​the groove 2.

[0154] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, in the overlapping region A of the partition dam 3, the extending direction of the connecting via Via intersects (e.g., is perpendicular) with the extending direction of the partition dam 3, and in the overlapping region of the groove 2, the extending direction of the connecting via Via is consistent with the extending direction of the groove 2.

[0155] It should be noted that, as Figure 7A As shown, in the area where the groove 2 is set, due to the grooving process, along the direction extending from the groove 2 (e.g.) Figure 7A In the horizontal direction, the flatness and uniformity of the bottom of groove 2 are higher than those in the direction perpendicular to the extension of groove 2 (e.g., in the horizontal direction). Figure 7A In the vertical direction of the groove 2, by setting the extension direction of the connecting via Via in the overlapping area of ​​the groove 2 to be consistent with the extension direction of the groove 2, it is very beneficial to the design and fabrication of the connecting via Via in this area, which helps to improve the dimensional uniformity and fabrication process stability of the connecting via Via, thereby making the contact resistance difference at each connecting via Via position smaller and reducing the resistance difference between different first signal lines.

[0156] However, as Figure 7A As shown, in the area where the partition dam 3 is located, since the surface of the partition dam 3 away from the substrate 100 has an arc shape that is high in the middle and low on both sides, in order to avoid poor hole opening, the extension direction of the connecting via Via in the overlapping area A of the partition dam 3 intersects with the extension direction of the partition dam 3. This allows for more design space to set larger connecting via Via, thereby reducing the difficulty of the manufacturing process of the connecting via Via in this area, reducing the probability of metal material residue when opening holes, and thus improving the quality of the display substrate.

[0157] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, the number of first signal lines 1 arranged on the partition 3 along the width direction of the partition 3 is less than the number of first signal lines 1 arranged in the groove 2 along the width direction of the groove 2.

[0158] In an exemplary embodiment, when the width of the partition 3 is the same as the width of the groove 2, the number of first signal lines 1 disposed on the partition 3 along the width direction of the partition 3 can be less than the number of first signal lines 1 disposed in the groove 2 along the width direction of the groove 2.

[0159] For example, such as Figure 7A As shown, the number of first signal lines 1 arranged on the partition 3 along the width direction of the partition 3 is 1; however, the number of first signal lines 1 arranged in the groove 2 along the width direction of the groove 2 is at least 5 or at least 6.

[0160] In some embodiments, the width of the groove 2 may be greater than the width of the partition dam 3.

[0161] In some embodiments, multiple segments of the first signal line 1 may be provided on the middle 1 / 3 region of the upper surface of the barrier 3.

[0162] In some embodiments, multiple segments of the first signal line 1, such as multiple first segments 11, can be provided at the central axis position on the upper surface of the barrier 3; or, multiple second segments 12; of course, multiple first segments 11 and multiple second segments 12 can also be provided. For example, multiple segments are all located at the central axis position on the upper surface of the barrier 3, and multiple segments are collinear.

[0163] In an exemplary embodiment, since the surface of the barrier dam 3 away from the substrate 100 has an arc shape that is high in the middle and low on both sides, in order to avoid cracks or breaks during the fabrication of the wiring, the number of first signal lines 1 arranged on the barrier dam 3 along the width direction of the barrier dam 3 is less than the number of first signal lines 1 arranged in the groove 2 along the width direction of the groove 2, thereby reducing the difficulty of fabricating the first signal lines 1 on the barrier dam 3, improving the product yield, and improving the quality of the display substrate.

[0164] In some display substrates provided in the embodiments of this application, such as Figure 7A As shown, the line width d1 of the adapter 13 is greater than or equal to twice the line width d3 of the first segment 11 or the line width d2 of the second segment 12.

[0165] This application proposes to place jumper holes (connection vias) on the adapter cable 13 when the bottom bezel is alternately routed, and to set sufficient gaps between two adjacent adapter cables 13. Without increasing the bezel, this reduces the risk of residual conductive layer material (e.g., residual material of conductive layer TMA / conductive layer TMB) when the first signal line 1 crosses the complex groove 2 of the bottom bezel, thus avoiding the risk of short circuits between the first signal lines 1. In addition, the jumper design makes the resistance difference between the first signal lines 1 smaller, enabling high-precision touch control. Furthermore, it can greatly narrow the bezel, making it suitable for narrow bezel display products.

[0166] Figures 7B to 7D Three schematic diagrams of different cross-sectional structures of connecting through holes, either installed on the partition dam 3 or within the groove 2, are provided. Figure 7B for Figure 7A A schematic diagram of the cross-sectional structure along the M3M4 direction; Figure 7C for Figure 7A A schematic diagram of the cross-sectional structure along the M5M6 direction; Figure 7D for Figure 7A A schematic diagram of the cross-sectional structure along the M7M8 direction.

[0167] Since the first segment 11 and the second segment 12 are configured in different layers, an insulating layer, such as a touch insulating layer 121, is provided between the film layers of the first segment 11 and the second segment 12.

[0168] Combination Figure 7A and Figure 7B As shown, a first line segment 11 is provided on the surface of the barrier dam 3 away from the substrate 100. A touch insulating layer 121 (TLD) is also provided between the first line segment 11 and the barrier dam 3. The first line segment 11 is located in the middle area of ​​the surface of the barrier dam 3 away from the substrate 100. The adapter line 13 is provided at the junction of the groove 2 and the barrier dam 3. The connecting via is provided on the adapter line 13.

[0169] Combination Figure 7A and Figure 7CAs shown, a first line segment 11 and a converter line 13 directly connected to the first line segment 11 are provided on the surface of the barrier dam 3 away from the substrate 100. The converter line 13 is provided on the surface of the barrier dam 3 away from the substrate 100. The first line segment 11 is located in the middle region of the surface of the barrier dam 3 away from the substrate 100. One end of the converter line 13 is connected to the first line segment 11 on the barrier dam 3, and the other end of the converter line 13 is connected to the second line segment 12 on the groove 2. A portion of the converter line 13 is provided on the barrier dam 3, and a portion of the converter line 13 is provided in the groove 2. A connecting via is provided on the converter line 13, and the connecting via is located in the edge region of the surface of the barrier dam 3 away from the substrate 100.

[0170] In combination Figure 7A and Figure 7D As shown, the adapter line 13 is disposed on the surface of the barrier dam 3 on the side away from the substrate 100, and the vertical length of the adapter line 13 is close to the width of the barrier dam 3, and the vertical length of the adapter line 13 is slightly greater than the width of the barrier dam 3. A connecting via Via is disposed on the adapter line 13, and the connecting via Via is located in the middle region of the surface of the barrier dam 3 on the side away from the substrate 100. The vertical length of the connecting via Via is greater than half the width of the barrier dam 3, and the vertical length of the connecting via Via is less than the width of the barrier dam 3.

[0171] It should be noted that, in Figures 7B to 7D In the middle, the partition dam 3 and the groove 2 are disposed on the base 200, and the base 200 may include, for example, Figure 8 The substrate 100 shown includes at least one of the following film layers located on the substrate 100: a first planarization layer 110 (PLN1), a second planarization layer 112 (PLN2), a pixel defining layer 114 (PDL), a support layer PS, a first inorganic layer 117 (CVD1), and a second inorganic layer 119 (CVD2). At least a portion of the film layers included in the barrier dam 3 are part of the substrate 200; for example, the barrier dam 3 may be formed from at least one of the first planarization layer 110 (PLN1), the second planarization layer 112 (PLN2), the pixel defining layer 114 (PDL), and the support layer PS. Additionally, a touch insulating layer 121 is provided on the barrier dam 3, which is used to isolate the first line segment 11 and the second line segment 12 that are disposed in different layers.

[0172] Figure 8A schematic cross-sectional view of a portion of a touch display substrate located in the display area AA is provided. The display area of ​​the display substrate includes: a substrate 100, a first buffer layer 101, a semiconductor layer 102, a gate insulating layer 103, a first gate layer 104 (including a gate and a first electrode Cst-1 of a storage capacitor), a first dielectric layer 105, a second gate layer 106 (including a second electrode Cst-2 of a storage capacitor), a second dielectric layer 107, a first source / drain conductive layer 108 (SD1, including the source and drain of a transistor), and a passivation layer 109. The system comprises a PVX layer, a first planarization layer 110 (PLN1), a second source / drain conductive layer 111 (SD2), a second planarization layer 112 (PLN2), an anode 113, a pixel delimiting layer 114 (PDL), a light-emitting functional layer 115 (EL), a cathode 116 (Cathode), a first inorganic encapsulation layer 117 (CVD1), an organic encapsulation layer 118 (IJP), a second inorganic encapsulation layer 119 (CVD2), a second buffer layer 120 (Buffer), a first touch metal layer, a touch insulating layer 121 (TLD), a second touch metal layer, and a planarization layer 122 (OC). The first and second touch metal layers form the first touch signal line TX and the second touch signal line RX. Both the first touch signal line TX and the second touch signal line RX include a first segment 11 and a second segment 12, and a connecting wire 13 connecting the first segment 11 and the second segment 12. One of the first segment 11 and the second segment 12 is located in the first touch metal layer, and the other is located in the second touch metal layer.

[0173] Figure 8 The dashed ellipse in the diagram marks a first touch signal line TX or a second touch signal line RX, which is formed by two metal layers and a connecting via between the two metal layers, and is used to realize the touch function of the display substrate.

[0174] It should be noted that the above-mentioned display substrate may also include other structures and components. This specification only describes the structures and components related to the inventive point. Other structures and components can be referred to the descriptions in related technologies.

[0175] Embodiments of this application provide a display panel, including a display substrate as described in any of the preceding descriptions.

[0176] In an exemplary embodiment, the display panel can be a light-emitting diode (LED), organic light-emitting diode (OLED), micro LED (micro light-emitting diode), or mini LED (mini light-emitting diode) display panel.

[0177] The aforementioned display panel can be a silicon-based display panel or a glass-based display panel. A silicon-based display panel refers to a display panel whose driving circuit is disposed on a silicon substrate and fabricated using MOS technology. A glass-based display panel refers to a display panel whose driving circuit is disposed on a glass substrate and fabricated using TFT technology.

[0178] For example, the above-mentioned display panel can be a Touch and Display Driver Integration (TDDI) display panel.

[0179] The size of the aforementioned display panel is not limited. It can be used in large or extra-large (e.g., 86 inches) UHD (Ultra High Definition) or HD (High Definition) display devices, or it can be used in small (e.g., 23.6 inches) UHD or HD display devices.

[0180] In an exemplary embodiment, the display panel of this application can also be used in virtual reality devices or augmented display devices, etc. The display panel may include, but is not limited to: mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, or any product or component with display function.

[0181] In the display panel provided in the embodiments of this application, by setting an adapter line 13 that intersects with the first line segment 11 and the second line segment 12, and setting the line width d1 of the adapter line 13 to be greater than the line widths (d2 and d3) of the first line segment 11 and the second line segment 12, and setting at least one connection via Via on the adapter line 13, on the one hand, since the extension directions of the first line segment 11 and the second line segment 12 are consistent, and the extension directions of the adapter line 13 intersect with the first line segment 11 and the second line segment 12 respectively, setting the connection via Via on the adapter line 13 does not increase the size and design space of the first line segment 11 and the second line segment 12 along their width direction, which can ensure a narrower width of the peripheral area BB, which is beneficial for narrow bezels. The fabrication of the display product; on the other hand, since the line width of the adapter cable 13 is greater than that of the first line segment 11 and the second line segment 12, the connection vias Via provided on the adapter cable 13 have more flexible design space and design size, thereby avoiding process defects caused by the small size or limited design position of the connection vias Via (such as material residue when opening the hole); furthermore, through the jumper design between different film layers, the length difference between different first signal lines 1 is small. Due to the high size flexibility of the connection vias Via, the contact resistance difference between the connection vias Via between different first signal lines 1 is small, thereby making the resistance difference between the first signal lines 1 small, which can achieve high-precision touch control.

[0182] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display substrate, wherein, Includes the display area and a surrounding area located on one side of the display area. The surrounding area includes multiple first signal lines, each first signal line including a first segment and a second segment disposed in different layers, and a connector connecting the first segment and the second segment; The first line segment and the second line segment extend in the same direction, and the extension direction of the adapter line intersects with the first line segment and the second line segment respectively; The adapter cable has a wire width greater than that of the first and second wire segments, and the adapter cable is provided with at least one connection via for electrically connecting the first and second wire segments.

2. The display substrate of claim 1, wherein, At least some of the connecting vias have a maximum width greater than the line width of the first line segment or the second line segment.

3. The display substrate of claim 1, wherein, At least a portion of the minimum width of the connecting via is greater than the line width of a portion of the first line segment and greater than the line width of a portion of the second line segment.

4. The display substrate of claim 1, wherein, The horizontal distance between two adjacent connecting vias is greater than the line width of the first line segment or the line width of the second line segment.

5. The display substrate of claim 1, wherein, The adapter cable is disposed on the same layer as the first line segment; and / or, the adapter cable is disposed on the same layer as the second line segment.

6. The display substrate of claim 5, wherein, The orthographic projections of any two adjacent adapter lines on the substrate of the display substrate do not overlap.

7. The display substrate of claim 6, wherein, The peripheral region includes an organic layer disposed on the substrate, the organic layer including at least one groove, and the orthographic projection of a portion of the first signal line on the substrate overlaps with the orthographic projection of the area enclosed by the outer contour of the groove on the substrate.

8. The display substrate of claim 7, wherein, The orthographic projection of part of the adapter line on the substrate overlaps with the orthographic projection of the area enclosed by the outer contour of the groove on the substrate, and the extension direction of the groove intersects with the extension direction of the adapter line.

9. The display substrate of claim 8, wherein, The orthographic projection of some of the connecting vias on the substrate falls within the area enclosed by the outer contour of the groove on the substrate, while the orthographic projection of some of the connecting vias on the substrate falls outside the area enclosed by the outer contour of the groove on the substrate.

10. The display substrate of claim 9, wherein, There is at least one of the connection vias, the orthographic projection of which overlaps with the orthographic projection of the area enclosed by the outer contour of the groove on the substrate.

11. The display substrate of claim 7, wherein, The organic layer includes at least two grooves, a partition dam is provided between the two grooves, a portion of the adapter wire is provided on the side of the partition dam away from the substrate, and the length of the adapter wire on the side of the partition dam away from the substrate is greater than the length of the adapter wire located in the groove.

12. The display substrate according to claim 11, wherein, The orthographic projection of a portion of the connecting via on the substrate overlaps with the orthographic projection of the barrier dam on the substrate; Among the overlapping connecting through holes of the partition dam, at least a portion of the connecting through holes have a length along the direction perpendicular to the extension of the partition dam that is greater than or equal to the length of the outer contour of the groove in the area where the overlapping connecting through holes have a length along the same direction.

13. The display substrate of claim 12, wherein, The area where the connecting via overlaps with the barrier dam includes a first area and a second area located on both sides of the first area; The length of the connecting via in the first region along the direction perpendicular to the extension of the barrier dam is greater than the length of the connecting via in the second region along the direction perpendicular to the extension of the barrier dam, and the dimension of the connecting via in the first region along the width direction of the barrier dam is smaller than the width of the barrier dam.

14. The display substrate of claim 13, wherein, The connecting via in the second region is located at 1 / 3 of the width of the barrier dam.

15. The display substrate of claim 13, wherein, A portion of the first line segment and / or a portion of the second line segment are disposed on the side of the barrier dam away from the substrate and are electrically connected to the connection via in the second region; The first and second wire segments of the connecting via electrical connection in the first region are respectively disposed in the grooves on both sides of the barrier dam.

16. The display substrate according to claim 12, wherein, In the overlapping areas of the partition dam, the extending direction of the connecting through hole intersects with the extending direction of the connecting through hole in the overlapping areas of the groove.

17. The display substrate according to claim 16, wherein, In the overlapping area of ​​the partition dams, the extending direction of the connecting through hole intersects with the extending direction of the partition dam, and in the overlapping area of ​​the grooves, the extending direction of the connecting through hole is consistent with the extending direction of the groove.

18. The display substrate of claim 11, wherein, The number of first signal lines arranged on the dam along the width direction of the dam is less than the number of first signal lines arranged in the groove along the width direction of the groove.

19. The display substrate of claim 1, wherein, The width of the adapter cable is greater than or equal to twice the width of the first or second segment.

20. A display panel, wherein, Includes the display substrate as described in any one of claims 1 to 19.

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