AFDX protocol module based on XMC bus and avionics system

Abstract

The utility model discloses an AFDX protocol module based on an XMC bus and an avionics system, the AFDX protocol module based on the XMC bus comprises a network channel and a processor, the input end of the processor is connected with the network channel, and the processor is also connected with a memory through the XMC bus. According to the utility model, AFDX data are received through a network channel; the processor is connected with the memory through the XMC bus, the processor carries out integrity detection and redundancy judgment data processing on AFDX data and outputs the corresponding AFDX data to the memory, the flexibility of the XMC bus and the high reliability and the real-time performance of an AFDX protocol are combined, the real-time performance, the reliability and the flexibility of data transmission are improved, and the data transmission efficiency is improved. Therefore, the data transmission requirement of an avionics system is met.

Description

Technical Field

[0001] This utility model relates to the field of avionics network technology, and in particular to an AFDX protocol module and avionics system based on the XMC bus. Background Technology

[0002] With the rapid development of avionics systems, the AFDX (Avionics Full Duplex Switched Ethernet) network protocol has been widely used in modern avionics systems. However, current avionics systems have increasingly higher requirements for data transmission, and the existing AFDX protocol modules have low flexibility, making it difficult to meet the stringent requirements of avionics systems for data transmission. Utility Model Content

[0003] The purpose of this invention is to design an AFDX protocol module based on the XMC bus to solve the above problems.

[0004] This utility model achieves the above objectives through the following technical solutions:

[0005] The AFDX protocol module based on the XMC bus includes:

[0006] The network channel is used to receive AFDX data;

[0007] The processor has its input terminal connected to the network channel and is connected to the memory via the XMC bus. The processor is used to process the AFDX data and output the corresponding AFDX data to the memory.

[0008] This invention also proposes an avionics system, which includes the aforementioned AFDX protocol module based on the XMC bus.

[0009] The beneficial effects of this utility model are as follows:

[0010] The AFDX protocol module based on the XMC bus receives AFDX data through a network channel; the processor is connected to the memory through the XMC bus, performs integrity detection and redundancy judgment on the AFDX data, and outputs the corresponding AFDX data to the memory. Combining the flexibility of the XMC bus with the high reliability and real-time performance of the AFDX protocol, the real-time performance, reliability and flexibility of data transmission are improved to meet the data transmission requirements of avionics systems. Attached Figure Description

[0011] Figure 1 This is an overall block diagram of the AFDX protocol module based on the XMC bus of this utility model;

[0012] Figure 2 This is a schematic diagram of the virtual link of the AFDX protocol module based on the XMC bus of this utility model.

[0013] Figure 3 This is a schematic diagram of the frame structure of the AFDX protocol module based on the XMC bus of this utility model.

[0014] Figure 4 This is a schematic diagram of the BAG and jitter modules of the AFDX protocol module based on the XMC bus of this utility model.

[0015] Figure 5 This is a schematic diagram of another module of the AFDX protocol module based on the XMC bus of this utility model, namely BAG and jitter.

[0016] In the diagram: 10 - Network channel, 20 - Processor, 30 - XMC bus, 40 - Power supply circuit, 50 - Memory. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In the description of this utility model, it should be understood that the terms "upper", "lower", "inner", "outer", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the utility model product is usually placed in during use, or the orientation or positional relationship that is commonly understood by those skilled in the art. They are only used to facilitate the description of this utility model and to simplify the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0021] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0022] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0023] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0024] like Figure 1-5 As shown, the AFDX protocol module based on the XMC bus includes:

[0025] Network channel 10 is used to receive AFDX data;

[0026] The processor 20 has its input terminal connected to the network channel 10 and is connected to the memory 50 via the XMC bus 30. The processor 20 is used to process the AFDX data and output the corresponding AFDX data to the memory 50.

[0027] In one embodiment, the processor 20 is an FPGA, which is used to perform integrity detection and redundancy judgment data processing on the AFDX data.

[0028] In one embodiment, the AFDX protocol module based on the XMC bus further includes a power supply circuit 40, which provides operating power to the processor 20.

[0029] In one embodiment, there are two network channels 10, each of which includes a NetA network port and a NetB network port, which are used to send and receive the AFDX data.

[0030] In this embodiment, the XMC (eXtensible Microcontroller Bus Interface) bus is a high-performance microcontroller bus interface that provides an efficient and flexible data channel for the external memory 50. It combines the flexibility of the XMC bus 30 with the high reliability and real-time performance of the AFDX protocol to meet the data transmission requirements of avionics systems.

[0031] In this embodiment, the power supply circuit 40 can be implemented using an external power supply or a battery power supply to provide operating power for the processor 20; the processor 20 can be implemented using an FPGA (Field-Programmable Gate Array); after receiving AFDX data, the FPGA selects the required AFDX data through integrity detection and redundancy judgment, and stores the required AFDX data in the memory 50. In addition to redundant reception, it also supports receiving only NetA, receiving only NetB, and receiving data from both NetA and NetB simultaneously. Similarly, the transmission of the AFDX protocol module based on the XMC bus also supports three modes: transmitting only NetA, transmitting only NetB, and transmitting data from both NetA and NetB simultaneously.

[0032] In this embodiment, the AFDX protocol module based on the XMC bus supports two AFDX network channels 10. Each network channel 10 consists of two network ports, namely two independent NetA network ports and NetB network ports. Each network channel 10 can operate as a simulated ES (End System), capable of transmitting and receiving AFDX data. It is understood that each AFDX end system ES provides two independent networks, NetA and NetB. Unlike typical dual-redundancy operation, both NetA and NetB network ports will transmit and receive data during operation.

[0033] like Figure 2As shown, a Virtual Link (VL) defines the source and destination addresses of a data frame; a single Elasticsearch Element (ES) can only transmit on one VL; that is, if ES7 transmits on VL12, other ESs cannot transmit on VL12. A VL can be received by multiple ESs; VL12 can be received by ES9, ES15, and ES18. The routing information contained in the AFDX switch makes this possible. In this embodiment, each channel of the AFDX protocol module based on the XMC bus supports the creation of up to 128 VLs for both reception and transmission, and the parameters and modes of each VL can be set independently.

[0034] In practical applications, each SubVL (Sub Virtual Link) can define up to four sublinks; data transmission within each VL uses a sublink round-robin method. A single VL can be used to send multiple types of data, with the data type defined at the sublink level. Each sublink is defined by unequal UDP (Open Systems Interconnection) source and destination port numbers and is assigned a sublink type. The AFDX specification defines three types of sublinks: Sample data, Queuing data, and SAP data. Each type of SubVL transmits different types of data. Sample data has a fixed format and is usually retransmitted, such as altitude, latitude, and longitude. Queuing data has no fixed format, and the data transmitted may differ each time, such as databases and videos. SAP data is compatible with non-avionics electronic networks.

[0035] like Figure 3 As shown, AFDX data frames conform to the IEEE 802.3 standard (Ethernet). Each AFDX data frame contains a destination address and a source address determined by the virtual link. Compared to standard Ethernet frames, each AFDX frame has a sequence number (SN) byte at the end of the frame (before the frame check sequence) indicating the sequence of the frame. Each VL has its own independent SN, with SN values ​​cycling from 1 to 255, and 0 indicating a reset. The frame length of AFDX ranges from 64 to 1518 bytes, and the corresponding payload ranges from 1 to 1471 bytes.

[0036] In practical applications, BAG (Bandwidth Allocation Gap) constrains the interval (in milliseconds) between every two Ethernet frames within the same VL. For example, if a VLID=1 is defined with BAG=32, then the data packet transmission rate within the link with VLID=1 cannot be faster than 32ms. In AFDX networks, each VL must have a defined BAG value, which must be between 1 and 128 milliseconds and raised to the power of 2. Allowed BAG values ​​are shown in the table below.

[0037]

[0038] like Figure 4 and Figure 5 As shown, in an AFDX network, each VL (Volume Level) needs to be assigned a jitter parameter in addition to the BAG parameter. Jitter is the data transmission delay range, measured in microseconds (µs). Generally, the jitter should be within the following range:

[0039]

[0040] In the formula, Nbw represents bandwidth (100Mbps), Lmax represents frame length. In the output of the terminal system, the flow rate of each specific VL is planned and controlled by the system integrator. The flow rate of the VL is related to BAG, jitter and Lmax.

[0041] In this embodiment, the AFDX protocol module based on the XMC bus supports two reception modes: VL mode reception and bus listening. VL mode reception receives data from a specified VL. Before reception, the specified VL must be created and relevant parameters set. Reception is performed according to the parameters set during creation, receiving only data that meets the conditions and filtering out data that does not. Bus listening mode receives data from all existing VLs within the channel. Before sending data, the AFDX protocol module based on the XMC bus needs to establish a defined VL and load the data. After startup, it sends data according to the relevant parameters set during VL creation. The transmission of each VL follows the set BAG and SKEW parameters, and the transmission within a VL follows a cyclic sub-link mode.

[0042] This utility model's AFDX protocol module based on the XMC bus receives AFDX data through network channel 10; processor 20 is connected to memory 50 through XMC bus 30. Processor 20 performs integrity detection and redundancy judgment data processing on AFDX data and outputs the corresponding AFDX data to the memory 50. Combining the flexibility of XMC bus 30 with the high reliability and real-time performance of the AFDX protocol, the real-time performance, reliability, and flexibility of data transmission are improved to meet the data transmission requirements of avionics systems.

[0043] This utility model also proposes an avionics system, which includes the above-mentioned AFDX protocol module based on the XMC bus; the specific structure of the AFDX protocol module based on the XMC bus is as described in the above embodiments. Since this avionics system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0044] The AFDX protocol module based on the XMC bus in this invention utilizes the XMC bus 30 to support multiple data widths and operating modes to achieve efficient data transmission; and follows the AFDX protocol, using redundant design and priority scheduling mechanism to ensure data reliability and real-time performance; it adopts a modular design, making it easy to integrate into avionics systems.

[0045] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. An AFDX protocol module based on the XMC bus, characterized in that, The AFDX protocol module based on the XMC bus includes: The network channel is used to receive AFDX data; The processor has its input terminal connected to the network channel and is connected to the memory via the XMC bus. The processor is used to process the AFDX data and output the corresponding AFDX data to the memory.

2. The AFDX protocol module based on the XMC bus according to claim 1, characterized in that, The processor is an FPGA, which is used to perform integrity detection and redundancy judgment data processing on the AFDX data.

3. The AFDX protocol module based on the XMC bus according to claim 1, characterized in that, The AFDX protocol module based on the XMC bus also includes a power supply circuit, which provides operating power to the processor.

4. The AFDX protocol module based on the XMC bus according to claim 1, characterized in that, The number of network channels is two, and each network channel includes a NetA network port and a NetB network port, which are used to send and receive the AFDX data.

5. An avionics system, characterized in that, The avionics system includes the AFDX protocol module based on the XMC bus as described in any one of claims 1-4.

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