Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and a photovoltaic module, the solar cell comprises a cell body, the cell body is provided with a plurality of fine gate electrodes arranged at intervals along a first direction and a plurality of main gate electrodes arranged at intervals along a second direction; wherein the conductive types of the two adjacent fine gate electrodes are opposite, and the conductive types of the two adjacent main gate electrodes are opposite; the fine gate electrodes and the main gate electrodes which are opposite in conduction type have first intersections, the fine gate electrodes are disconnected at the intersections to form a plurality of sub-electrodes which are discontinuously arranged, and first gaps are formed between the end parts of the sub-electrodes and the main gate electrodes; a conductive layer is arranged between the fine gate electrode and the cell body, and the fine gate electrode is electrically connected with the cell body through the conductive layer. Therefore, the main gate electrode and the fine gate electrode can be simultaneously processed by adopting a one-time processing and forming mode, so that the process flow can be simplified, and the production cost can be reduced.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic technology, specifically relating to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells are devices that directly convert light energy into electrical energy. With the continuous development of photovoltaic technology, back-contact solar cells, because their electrodes are all located on the back of the cell, can avoid the grid lines blocking the front of the cell, thereby improving the conversion efficiency of solar cells and gaining widespread application and attention.

[0003] In back-contact solar cells of related technologies, the electrodes include a fine grid and a main grid. The fine grid collects charge carriers generated by the cell body. Traditional high-temperature metallization processes involve sintering high-temperature silver paste onto a dielectric layer such as silicon nitride, allowing the paste to penetrate the silicon nitride interface and form a good metal contact with the underlying semiconductor layer. The main grid collects charge carriers from the fine grid and provides tension for the solder ribbon; it does not require burning through the silicon nitride interface. Therefore, during electrode fabrication, the fine grid is first printed and sintered in the first and second conductive regions on the back of the solar cell, and then the main grid is printed and dried. However, the solar cell structure using this technology has a complex process flow and high production costs for the high-temperature silver paste. Summary of the Invention

[0004] This application aims to provide a solar cell and photovoltaic module that can solve the problems of complex structure, complex process, and high production cost of solar cells using related technologies.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows:

[0006] In a first aspect, embodiments of this application propose a solar cell, comprising: a cell body having intersecting first and second directions; the cell body having a plurality of fine grid electrodes spaced apart along the first direction and a plurality of main grid electrodes spaced apart along the second direction; wherein, the conductivity types of two adjacent fine grid electrodes are opposite, and the conductivity types of two adjacent main grid electrodes are opposite.

[0007] The fine grid electrode and the main grid electrode, which have opposite conductivity types, have a first junction. The fine grid electrode is disconnected at the first junction to form a plurality of discontinuously arranged sub-electrodes. A first gap is provided between the end of the sub-electrode and the main grid electrode. A conductive layer is provided between the fine grid electrode and the battery body. The fine grid electrode is electrically connected to the battery body through the conductive layer.

[0008] Optionally, the battery body includes a silicon substrate and a doped semiconductor layer formed on the silicon substrate;

[0009] The conductive layer is covered on the doped semiconductor layer, and both the main gate electrode and the fine gate electrode are disposed on the conductive layer;

[0010] Alternatively, a dielectric layer may be further covered on the doped semiconductor layer, and a plurality of vias may be provided in the dielectric layer to expose the doped semiconductor layer in corresponding areas. The conductive layer may be provided in the vias; the fine gate electrode extends at least partially into the vias and forms an electrical connection with the doped semiconductor layer through the conductive layer.

[0011] Optionally, the conductive layer may include a transparent conductive layer or a base metal layer.

[0012] Optionally, the fine gate electrode and the main gate electrode, which have the same conductivity type, have a second junction, and the fine gate electrode and the main gate electrode form an integral structure at the second junction, wherein the thickness of the integral structure is greater than or equal to the thickness of the fine gate electrode.

[0013] Optionally, an insulating layer is provided between the main grid electrode and the battery body at the first junction, and a second gap exists between the end of the sub-electrode and the corresponding insulating layer.

[0014] Optionally, the width of the second gap along the second direction is W2, which satisfies: W2≥15μm.

[0015] Optionally, a conductive connection layer is further provided on the battery body at the first junction, and two adjacent sub-electrodes are electrically connected through the conductive connection layer. The insulating layer is disposed between the conductive connection layer and the main grid electrode. The sub-electrode includes a main body portion and an overlapping portion that are connected to each other. The main body portion is electrically connected to the battery body, and the overlapping portion extends to the conductive connection layer and forms an electrical connection with the conductive connection layer.

[0016] Optionally, the overlapping portion extends to cover the side of the conductive connection layer opposite to the battery body, so as to form an overlap with the conductive connection layer.

[0017] Optionally, the conductive connection layer has an opening along the edge of the second direction, and the overlapping portion is at least partially embedded in the opening.

[0018] Optionally, the thickness of the overlapping portion is h2, and the thickness of the main body portion is h1, satisfying: 0.8≤h2 / h1≤1.

[0019] Optionally, the thickness h1 of the main body portion ranges from 5 μm to 35 μm.

[0020] Optionally, the length of the overlapping portion along the second direction is W1, satisfying: W1≥25μm.

[0021] Optionally, along the second direction, the length L1 of the conductive connection layer and the length L2 of the insulating layer satisfy: 0.5≤L2 / L1≤0.9, and / or, L1-L2≥80μm.

[0022] Optionally, the solar cell satisfies at least one of the following conditions:

[0023] A. The length of the insulating layer along the second direction is L2, and the width of the main gate electrode along the second direction is L3, satisfying: 0.3≤L3 / L2<1;

[0024] B. The thickness range of the conductive connection layer is 1μm-10μm;

[0025] C. The thickness range of the insulating layer is 1μm-30μm;

[0026] D. The orthographic projection shape of the conductive connection layer on the battery body is one or a combination of two or more of the following: circular, elliptical, and polygonal.

[0027] Optionally, the solar cell satisfies at least one of the following conditions:

[0028] E. The thickness range of the main gate electrode is 3μm-35μm;

[0029] F. The fine gate electrode and the main gate electrode are made of the same material, including copper;

[0030] G. The width of the first gap along the second direction is W3, which satisfies: 0.01mm≤W3≤3mm.

[0031] Secondly, embodiments of this application propose a photovoltaic module including multiple battery strings, each battery string including multiple solar cells and multiple interconnecting elements, the interconnecting elements being used to connect the multiple solar cells in series; wherein, the solar cells are the solar cells described in the first aspect.

[0032] In the embodiments of this application, by disconnecting the fine grid electrode at the junction with the main grid electrode (which has the opposite conductivity type) and maintaining a first gap between the end of the sub-electrode and the main grid electrode, mutual interference between the fine grid electrode and the main grid electrode layout structure with opposite conductivity types on the battery body can be avoided. Simultaneously, by providing a conductive layer between the fine grid electrode and the battery body, electrical connection between the fine grid electrode and the battery body is achieved. This facilitates the simultaneous fabrication of the main grid electrode and the fine grid electrode using a low-temperature slurry in a single process, thereby simplifying the process flow and reducing production costs.

[0033] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below, wherein:

[0035] Figure 1 This is a schematic diagram of a first type of solar cell according to an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of a second type of solar cell according to an embodiment of this application;

[0037] Figure 3 It is along Figure 1 A structural cross-sectional view of line AA in the middle;

[0038] Figure 4 It is along Figure 1 One of the other structural cross-sectional views of the AA line;

[0039] Figure 5 It is along Figure 1 Another structural cross-sectional view of line AA in the middle;

[0040] Figure 6 It is along Figure 2 Sectional view of the middle BB line;

[0041] Figure 7 This is a schematic diagram of another connection structure between the sub-electrode and the conductive connection layer according to an embodiment of this application;

[0042] Figure 8 This is a schematic diagram of another connection structure between the sub-electrode and the conductive connection layer according to an embodiment of this application;

[0043] Figure 9 This is a schematic diagram of the connection structure of the main gate electrode and the fine gate electrode of the same conductivity type at the second junction according to an embodiment of this application.

[0044] Figure label:

[0045] 10: Battery body; 11: Silicon substrate; 12: Doped semiconductor layer; 101: First conductive transport layer; 102: Second conductive transport layer; 103: Isolation region; 13: Conductive layer; 14: Dielectric layer; 141: Through-hole; 20: Fine grid electrode; 21: Sub-electrode; 211: Main body; 212: Overlapping part; 201: First fine grid; 202: Second fine grid; M1: First gap; M2: Second gap; 30: Main grid electrode; 301: First main grid; 302: Second main grid; 40: Conductive connection layer; 401: Opening; 50: Insulating layer; X: First direction; Y: Second direction. Detailed Implementation

[0046] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0047] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0048] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0050] The solar cells and photovoltaic modules provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0051] Existing solar cells typically include a silicon substrate, a doped semiconductor layer, a dielectric layer, and electrodes. The doped semiconductor layer is formed on the light-facing and / or back-facing side of the silicon substrate. The dielectric layer is formed on the side of the doped semiconductor layer away from the silicon substrate as a surface passivation layer and / or an anti-reflection layer. The surface passivation layer is used to passivate surface defects on the side of the doped semiconductor layer away from the silicon substrate, reducing the carrier recombination efficiency of the doped semiconductor layer; the anti-reflection layer is used to reduce the reflection of incident light, improving the light absorption rate of the silicon substrate.

[0052] The electrodes are disposed on the dielectric layer and include fine grid electrodes and main grid electrodes. The fine grid electrodes collect charge carriers generated by the silicon substrate, while the main grid collects charge carriers from the fine grid electrodes and provides tension for the solder ribbon when multiple cells are connected in series. In traditional solar cells, the fine grid electrodes are made using a high-temperature metallization process. This involves printing high-temperature silver paste onto the dielectric layer and then sintering it to allow the paste to penetrate the dielectric layer and form a good ohmic connection with the underlying doped semiconductor layer. The main grid electrodes, however, do not need to penetrate the dielectric layer interface. Due to the different functions of the fine grid electrodes and the main grid electrodes, the paste compositions differ. Therefore, during electrode fabrication, high-temperature paste is first printed and then sintered at high temperature to prepare the fine grid electrodes. During sintering, the high-temperature paste burns through the dielectric layer to contact the doped semiconductor layer, thus forming the fine grid electrodes. Then, the main grid paste is printed and cured to obtain the main grid electrodes. Due to the structural limitations of solar cells, the fine grid electrodes and the main grid electrodes need to be processed separately, resulting in a complex processing flow and high production costs for high-temperature silver paste.

[0053] like Figures 1 to 3As shown, a solar cell according to some embodiments of this application includes a cell body 10, which has intersecting first direction X and second direction Y. The cell body 10 is provided with a plurality of fine grid electrodes 20 spaced apart along the first direction X and a plurality of main grid electrodes 30 spaced apart along the second direction Y. Adjacent fine grid electrodes 20 have opposite conductivity types, and adjacent main grid electrodes 30 have opposite conductivity types. The fine grid electrodes 20 with opposite conductivity types and the main grid electrodes 30 have a first junction, where the fine grid electrodes 20 are disconnected to form a plurality of discontinuously arranged sub-electrodes 21. A first gap is provided between the end of the sub-electrode 21 and the main grid electrode 30. A conductive layer is provided between the fine grid electrodes 20 and the cell body 10, and the fine grid electrodes 20 are electrically connected to the cell body 10 through the conductive layer.

[0054] In this embodiment, by disconnecting the fine grid electrode 20 at the junction with the main grid electrode 30 (which has the opposite conductivity type) and maintaining a first gap between the end of the sub-electrode 21 and the main grid electrode 30, mutual interference between the layout structures of the fine grid electrode 20 and the main grid electrode 30 (which have opposite conductivity types) on the battery body can be avoided. Simultaneously, by providing a conductive layer between the fine grid electrode 20 and the battery body 10, electrical connection between the fine grid electrode 20 and the battery body 10 is achieved. This facilitates the simultaneous fabrication of the main grid electrode 30 and the fine grid electrode 20 using a low-temperature slurry in a single process, thereby simplifying the process flow and reducing production costs.

[0055] Understandably, existing solar cells, due to structural limitations, require a step-by-step processing method to fabricate the fine grid electrode 20 and the main grid electrode 30. However, this step-by-step processing method involves heating and curing the paste used to process both the fine grid electrode 20 and the main grid electrode 30, especially when the paste contains easily oxidizable metal particles (such as copper particles). To prevent oxidation of the electrode surface during heating and curing, a protective gas must be introduced, making the process complex and cumbersome, affecting processing efficiency and increasing production costs. Furthermore, besides the cost of the silicon substrate itself, the manufacturing cost of the electrodes is very high in the overall manufacturing cost of solar cells, and using high-temperature silver paste as the electrode material further increases production costs.

[0056] Furthermore, during the step-by-step electrode processing, since the fine grid electrode 20 has already solidified during the processing of the main grid electrode 30, the different phase states of the paste-like main grid electrode 30 and the solid fine grid electrode 20 at the points where the main grid electrode 30 and the fine grid electrode 20 need to be connected can affect the connection strength between them. This results in poor connection performance and high lap resistance at the connection points of the main grid electrode 30 and the fine grid electrode 20, which have the same conductivity type. Moreover, on the surface of the battery body 10, there is a significant height difference between the intersection of the main grid electrode 30 and the fine grid electrode 20 and other locations. This can lead to uneven stress on the battery body 10 during subsequent processing, resulting in problems such as microcracks or breakage.

[0057] The solar cell structure described in this application allows for a one-time fabrication process, simultaneously producing the main grid electrode 30 and the fine grid electrode 20. The fine grid electrode 20 is disconnected at the first junction with the main grid electrode 30 of the opposite conductivity type. This ensures that the main grid electrode 30 and the fine grid electrode 20 of the opposite conductivity type are isolated from each other at the junction, while improving the connection performance of the main grid electrode 30 and the fine grid electrode 20 of the same conductivity type. At the same time, it simplifies the processing technology and reduces production costs.

[0058] Specifically, such as Figure 9 As shown, the fine gate electrode 20 and the main gate electrode 30, which have the same conductivity type, have a second junction. Since the main gate electrode 30 and the fine gate electrode 20 are processed simultaneously, the fine gate electrode 20 and the main gate electrode 30 form an integral structure at the second junction. The thickness of the integral structure at the second junction is set to be greater than or equal to the thickness of the fine gate electrode 20, thereby ensuring the connection strength and conductivity of the main gate electrode 30 and the fine gate electrode 20, which have the same conductivity type, at the junction.

[0059] At the first junction of the main grid electrode 30 and the fine grid electrode 20 with opposite conductivity, the fine grid electrode 20 adopts a disconnected structure, which can reduce the height of the electrode structure at the first junction, thereby reducing the height difference on the surface of the battery body 10 at different positions and reducing the risk of local microcracks or damage to the battery body 10.

[0060] In some embodiments, the solar cell in this application can be a back contact cell, and the electrodes of the back contact cell are all disposed on the back side. The back contact cell includes, but is not limited to: back contact heterojunction solar cell (HBC cell), back contact tunnel oxide passivated contact cell (TBC cell), composite passivated back contact cell (HPBC cell), back contact hybrid cell (HTBC cell), etc.

[0061] Optionally, such as Figure 3 and Figure 6As shown, the width of the first gap M1 along the second direction Y is W3, satisfying: 0.01mm ≤ W3 ≤ 3mm. For example, the width W3 of the first gap can be set to 0.01mm, 0.05mm, 0.08mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, etc. By setting the first gap between 0.01mm and 3mm, it is possible to avoid the first gap being too small, which could easily cause overlap between the main grid electrode and the fine grid electrode of opposite conductivity types, and also to avoid the performance loss of the battery caused by the gap being too large. It is understood that in specific applications, the size of the first gap depends on the organic expansion of the electrode paste to both sides and the process error, and can be flexibly set according to the actual situation, without limitation here.

[0062] Specifically, such as Figure 1 and Figure 3 As shown, the battery body 10 includes a silicon substrate 11 and a doped semiconductor layer 12. The doped semiconductor layer 12 is disposed on the surface of the silicon substrate 11 to transport holes and electrons generated by the photoelectric effect of the silicon substrate 11. The doped semiconductor layer 12 includes a first conductive transport layer 101 and a second conductive transport layer 102 alternately arranged along a first direction X. The first conductive transport layer 101 and the second conductive transport layer 102 have opposite conductivity types; one is an N-type transport layer and the other is a P-type transport layer. The specific N-type and P-type transport layers are not specifically limited. The specific materials of the N-type and P-type transport layers are not limited. For example, the first conductive transport layer 101 can be an N-type doped polycrystalline silicon layer, with a tunneling oxide layer (not shown in the figure) between the silicon substrate 11 and the N-type doped polycrystalline silicon layer. The second conductive transport layer 102 can be a P-type doped amorphous silicon layer, with an intrinsic amorphous silicon layer (not shown in the figure) between the silicon substrate 11 and the P-type doped amorphous silicon layer. This battery structure is a back-contact hybrid battery (HTBC battery). An isolation region 103 is provided between adjacent first conductive transport layer 101 and second conductive transport layer 102. The isolation region 103 is used to achieve electrical isolation between the first conductive transport layer 101 and the second conductive transport layer 102 to avoid short circuits.

[0063] Furthermore, such as Figure 1 and Figure 3As shown, conductive layers 13 are provided on both the first conductive transport layer 101 and the second conductive transport layer 102. For example, the conductive layer 13 is a transparent conductive oxide (TCO) layer. The conductive layer 13 is disconnected at the isolation region 103 to achieve electrical isolation. The transparent conductive layer can reduce the contact resistance between the carrier transport layer and the metal electrode and increase the lateral transport capability. The fine grid electrode 20 and the main grid electrode 30 can be simultaneously formed on the transparent conductive layer by means of screen printing or other methods. The fine grid electrode 20 is electrically connected to the doped semiconductor layer 12 through the transparent conductive layer to collect the carriers generated by the silicon substrate 11. Using this battery structure can simplify the process flow and reduce production costs. In addition, when using a non-burn-through paste such as copper paste, the transparent conductive layer can also act as a barrier layer to prevent copper ions in the copper paste from diffusing into the battery, thereby improving the efficiency of the solar cell and further reducing costs.

[0064] According to embodiments of this application, the material of the transparent conductive layer can be at least one selected from indium tin oxide (ITO), tungsten-doped tin oxide (VTTO), indium tungsten oxide (IWO), indium molybdenum oxide (IMO), and tin oxide fluoride (TOF). The transparent conductive layer can be prepared by methods such as magnetron sputtering, and the specific preparation method is not limited.

[0065] In other embodiments, such as Figure 2 and Figure 6 As shown, the battery body 10 includes a silicon substrate 11 and a doped semiconductor layer 12 formed on the silicon substrate 11. The doped semiconductor layer 12 may include a first conductive transport layer 101 and a second conductive transport layer 102 with opposite conductivity types. The first conductive transport layer 101 and the second conductive transport layer 102 may be interdigitated. An isolation region 103 is provided between the first conductive transport layer 101 and the second conductive transport layer 102. The surface of the silicon substrate 11 at the location corresponding to the isolation region 103 may have a textured or polished structure; this is not limited. For example, the surface of the silicon substrate 11 at the location corresponding to the isolation region 103 may have a textured structure to increase the light-trapping effect. The first conductive transport layer 101 and the second conductive transport layer 102 have different conductivity types; one is an N-type transport layer and the other is a P-type transport layer. Which one is specifically the N-type transport layer and which one is the P-type transport layer is not specifically limited. The specific materials of the N-type transport layer and the P-type transport layer are not limited. For example, the first conductive transport layer 101 can be an N-type doped polycrystalline silicon layer, and a tunneling oxide layer (not shown in the figure) is also provided between the silicon substrate 11 and the N-type doped polycrystalline silicon layer. The second conductive transport layer 102 can be a P-type doped polycrystalline silicon layer, and a tunneling oxide layer (not shown in the figure) is also provided between the silicon substrate 11 and the P-type doped polycrystalline silicon layer. This battery structure is a back contact tunneling oxide passivated contact battery (TBC battery).

[0066] Furthermore, such as Figure 6 As shown, a dielectric layer 14 is provided on the side of the first conductive transport layer 101 and the second conductive transport layer 102 away from the silicon substrate 11. The dielectric layer 14 has a plurality of through holes 141 to expose the doped semiconductor layer 12 in the corresponding area. A conductive layer 13 is provided in the through holes 141. The fine gate electrode 20 extends at least partially into the through holes 141 and forms an electrical connection with the doped semiconductor layer 12 through the conductive layer 13.

[0067] In this application, the surface of the doped semiconductor layer 12 can be passivated by providing a dielectric layer 14, thereby reducing the carrier recombination rate. Since the dielectric layer 14 is a non-conductive film, a through-hole 141 extending along the thickness direction of the battery body 10 is formed in the dielectric layer 14, exposing at least a portion of the doped semiconductor layer 12 at the through-hole 141. A conductive layer 13 is then formed within the through-hole 141 of the dielectric layer 14 by electroplating or chemical plating, and the conductive layer 13 contacts the doped semiconductor layer 12. Then, a non-burn-through fine gate electrode 20 is formed above the conductive layer 13 by screen printing or other methods, so that the fine gate electrode 20 is at least partially embedded in the through-hole 141 and contacts the conductive layer 13, allowing the fine gate electrode 20 to penetrate the dielectric layer 14 and form an electrical connection with the doped semiconductor layer 12. The battery structure of this application facilitates the formation of fine grid electrodes 20 through a low-temperature metallization process, reducing the metallization process cost. The conductive layer 13 in the through-hole 141 can serve as a barrier layer to prevent metal from the non-burn-through electrode from penetrating into the silicon substrate 11, thereby reducing carrier recombination and improving collection efficiency.

[0068] In other embodiments, the conductive layer 13 may contain a metal element selected from at least one of the following: titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), cobalt (Co), molybdenum (Mo), tin (Sn), lead (Pb), palladium (Pd), copper (Cu), niobium (Nb), ruthenium (Ru), indium (In), zinc (Zn), tantalum (Ta), and vanadium (V). Using the above materials to form the conductive layer 13 allows it to better meet performance requirements such as resistance and barrier properties against metal elements like copper in the non-burn-through electrode, while reducing production costs. In particular, the material of the conductive layer 13 can be nickel and / or zinc. Both nickel and zinc have good contact properties and do not significantly penetrate the silicon substrate, resulting in less recombination. The nickel and zinc in the conductive layer 13 can effectively block base metals such as copper in the non-burn-through paste on the side facing away from the silicon substrate, preventing the penetration of metals such as copper from the non-burn-through fine gate electrode 20 into the silicon substrate, reducing recombination and costs.

[0069] In some examples, the dielectric layer 14 may include a passivation layer, or other possible films such as an antireflection layer, or a stacked passivation layer and an antireflection layer. The dielectric layer 14 can be a single-layer structure or a multi-layer structure. The structure of the dielectric layer 14 is not specifically limited in the embodiments of this application and can be configured according to the needs of the solar cell. For example, for a TBC cell, the dielectric layer 14 on its back surface may include a stacked passivation layer and an antireflection layer.

[0070] The dielectric layer 14 is made of an insulating material, which may include at least one of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide. For example, if the dielectric layer 14 is made of silicon nitride, silicon nitride has a high resistivity. Therefore, when the dielectric layer 14 is made of silicon nitride, it is beneficial to improve the insulating performance of the dielectric layer 14 and has a good passivation effect. Thus, the dielectric layer 14 made of silicon nitride passivates the surface of the doped semiconductor layer 12, which is beneficial to reducing the carrier recombination rate. In addition, since silicon nitride also has a good anti-reflection effect, it can improve the photoelectric conversion efficiency of the solar cell.

[0071] For the via 141 provided in the dielectric layer 14, since the fine gate electrode 20 needs to pass through the dielectric layer 14 and be electrically connected to the doped semiconductor layer 12 through the via 141, the distribution and size of the via 141 in the dielectric layer 14 can be determined according to the connection structure between the electrode and the doped semiconductor layer 12 in the actual application scenario. For example, the via 141 may be circular, square or elliptical or other shapes, which are not limited here.

[0072] The solar cell of this application can achieve the forming of fine grid electrode 20 under low temperature conditions (below 300°C, such as around 200°C), without the need for high-temperature furnace sintering, and the heat-affected zone introduced into the solar cell is very small, which simplifies the process and further reduces the manufacturing cost of solar cells.

[0073] In another embodiment, such as Figure 2 As shown, the first conductive transport layer 101 and the second conductive transport layer 102 are arranged in an interdigitated pattern. A conductive layer 13 covers the first conductive transport layer 101 and the second conductive transport layer 102. For example, the conductive layer 13 is a transparent conductive layer, which is disconnected at the isolation region 103. A fine gate electrode 20 and a main gate electrode 30 can be simultaneously formed on the transparent conductive layer using methods such as screen printing. The fine gate electrode 20 is electrically connected to the doped semiconductor layer 12 through the transparent conductive layer to collect charge carriers generated by the silicon substrate 11. Compared to a dielectric layer 14 covering the doped semiconductor layer 12, which has multiple vias, the transparent conductive layer is conductive and does not require openings, further simplifying the process. Furthermore, the transparent conductive layer can improve the lateral transport capability of charge carriers, thereby increasing battery efficiency.

[0074] Specifically, the fine gate electrode 20 includes a first fine gate 201 disposed on the first conductive transport layer 101 and a second fine gate 202 disposed on the second conductive transport layer 102; the main gate electrode 30 includes a first main gate 301 and a second main gate 302, the first main gate 301 and the second main gate 302 are alternately arranged along the second direction Y, the first main gate 301 extends along the first direction X and is electrically connected to a plurality of first fine gates 201, and the second main gate 302 extends along the first direction X and is electrically connected to a plurality of second fine gates 202.

[0075] The first intersection refers to the position where the first fine gate 201 intersects with the second main gate 302, and the position where the second fine gate 202 intersects with the first main gate 301. The second intersection refers to the position where the first fine gate 201 intersects with the first main gate 301, and the position where the second fine gate 202 intersects with the second main gate 302. Furthermore, the first fine gate 201 is disconnected at the position where it intersects with the second main gate 302, and the second fine gate 202 is disconnected at the position where it intersects with the first main gate 301.

[0076] Optionally, such as Figure 1 and Figure 3 As shown, an insulating layer 50 is provided between the main grid electrode 30 and the battery body 10 at the first junction, and a second gap M2 exists between the end of the sub-electrode 21 and the corresponding insulating layer 50. Specifically, an insulating layer 50 is provided between the battery body 10 and the second main grid 302. The insulating layer 50 does not contact the first fine grid 201, so as to insulate the first conductive transmission layer 101 and the second main grid 302 through the insulating layer 50. At the same time, the second gap M2 exists between the end of the sub-electrode 21 and the corresponding insulating layer 50. On the one hand, it can save insulating adhesive while satisfying the insulation isolation. On the other hand, this gap can prevent the insulating layer 50 from covering the end of the sub-electrode 21, thus preventing the simultaneous printing of the main grid electrode 30 and the fine grid electrode 20.

[0077] It is understandable that, such as Figure 1As shown, since the first conductive transport layer 101 and the second conductive transport layer 102 are alternately distributed along the X direction, the second main gate 302 is used to collect the charge carriers of the second fine gate 202, and the second fine gate 202 is used to collect the charge carriers of the second conductive transport layer 102. However, since the second main gate 302 extends along the first direction X, it will simultaneously cross the first conductive transport layer 101 and the second conductive transport layer 102. Therefore, an insulating layer 50 needs to be provided between the second main gate 302 and the first conductive transport layer 101 to avoid short circuit problems caused by the second main gate 302 being connected to doped semiconductor layers of different polarities. Accordingly, an insulating layer 50 is provided between the battery body 10 and the first main gate 301. The insulating layer 50 does not contact the second fine gate 202, so as to insulate and isolate the second conductive transport layer 102 from the first main gate 301 through the insulating layer 50.

[0078] It should be noted that the insulating layer 50 disposed between the battery body 10 and the second main grid 302 can have the same structure and material as the insulating layer 50 disposed between the battery body 10 and the first main grid 301, and this is not limited here. Optionally, such as Figure 1 As shown, the insulating layer 50 in the first conductive transport layer 101 and / or the second conductive transport layer 102 includes a plurality of insulating layers 50, which are spaced apart along the second direction Y.

[0079] In some embodiments, such as Figure 1 As shown, the insulating layer 50 extends along the first direction X, and the insulating layer 50 can completely cover the doped semiconductor layer 12 in the corresponding region in the first direction X. That is, the width of the insulating layer 50 on the first conductive transport layer 101 in the first direction X is greater than or equal to the width of the corresponding first conductive transport layer 101 in the first direction X, and the width of the insulating layer 50 on the second conductive transport layer 102 in the first direction X is greater than or equal to the width of the corresponding second conductive transport layer 102 in the first direction X. In this way, the insulating layer 50 can serve as an insulating layer between the doped semiconductor layer 12 and the main gate electrode 30 with the opposite conductivity type.

[0080] For example, such as Figure 1 As shown, the width of the first conductive transport layer 101 in the first direction X is 500 μm, therefore the width of the insulating layer 50 along the first direction X is greater than or equal to 500 μm. If the width of the insulating layer 50 along the first direction X is too small, it cannot completely isolate the first conductive transport layer 101 and the main gate electrode 30 of the opposite conductivity type; if the width of the insulating layer 50 is too large, it will waste raw materials. Optionally, the width of the insulating layer 50 along the first direction X is S1, where 200 μm ≤ S1 ≤ 800 μm. Correspondingly, the insulating layer 50 on the second conductive transport layer 102 can be configured with reference to the first conductive transport layer 101, and will not be described again here.

[0081] It is understood that the widths of the first conductive transport layer 101 and the second conductive transport layer 102 in the first direction X may be adjusted according to the type of the corresponding doped semiconductor layer 12. Their widths may be the same or different, and this is not limited here. In addition, the widths of the insulating layer 50 on the first conductive transport layer 101 and the insulating layer 50 on the second conductive transport layer 102 in the first direction X may be the same or different, and this is not limited here.

[0082] Optionally, such as Figure 1 and Figure 4 As shown, a conductive connection layer 40 is also provided on the battery body 10 at the first junction. Two adjacent sub-electrodes 21 are electrically connected through the conductive connection layer 40, and an insulating layer 50 is disposed between the conductive connection layer 40 and the main grid electrode 30. In this way, the disconnected portion of the fine grid electrode 20 can form a conductive path through the conductive connection layer 40, so that the carriers generated at the first junction can be collected through the fine grid electrode 20 and the conductive connection layer 40, thereby ensuring the collection of carriers at the disconnected portion of the fine grid electrode 20 and further improving battery efficiency. In addition, the insulating layer 50 is disposed between the conductive connection layer 40 and the main grid electrode 30 to insulate and isolate the conductive connection layer 40 from electrodes of the opposite conductivity type, and at the same time, to prevent the insulating layer 50 from interfering with the electrical connection between the fine grid electrode 20 and the conductive connection layer 40.

[0083] Specifically, the battery body 10 has a conductive connection layer 40 at the location where the first fine grid 201 is broken, and also has a conductive connection layer 40 at the location where the second fine grid 202 is broken. The part of the first fine grid 201 that is broken is electrically connected to the corresponding conductive connection layer 40 to form a conductive path, and the part of the second fine grid 202 that is broken is electrically connected to the corresponding conductive connection layer 40 to form a conductive path. It should be noted that the structure and material of the conductive connection layer 40 at the location where the first fine grid 201 is broken and the conductive connection layer 40 at the location where the second fine grid 202 is broken can be the same or different, and no limitation is made here.

[0084] In some embodiments, such as Figure 1 As shown, the conductive connection layer 40 extends along the first direction X, and the width of the conductive connection layer 40 in the first direction X is less than or equal to the width of the first conductive transport layer 101 in the first direction X. This allows the conductive connection layer 40 to have maximum contact with the first conductive transport layer 101, further improving carrier collection. If the width of the conductive connection layer 40 in the first direction X is greater than the width of the first conductive transport layer 101 in the first direction X, it not only wastes material and increases cost, but may also come into contact with the second conductive transport layer 102, which has the opposite conductivity type, further increasing the risk of short circuits.

[0085] For example, such as Figure 1As shown, the width of the first conductive transport layer 101 in the first direction X is 500 μm, therefore the width of the conductive connection layer 40 along the first direction X is less than or equal to 500 μm. If the width of the conductive connection layer 40 along the first direction X is too small, it will result in poor connection with the sub-electrode 21 and reduce the contact area with the first conductive transport layer 101, thus reducing carrier collection. If the width is too large, it will waste raw materials and also pose a short-circuit risk. For example, the width of the conductive connection layer 40 along the first direction X is S2, where 100 μm ≤ S2 ≤ 700 μm. Optionally, the conductive connection layer 40 may be made of one or more of the following materials: gold, silver, copper, nickel, aluminum, iron, and carbon, to ensure the conductivity of the conductive connection layer 40. By providing the conductive connection layer 40 at the break point of the fine gate electrode 20, a conductive path is formed at the break point of the fine gate electrode 20, ensuring the flow of current between different parts of the fine gate electrode 20. At the same time, it can also improve the ability of the fine gate electrode 20 to collect charge carriers at the break point.

[0086] In some embodiments, the conductive connecting layer 40 may be made of conductive ink, which may include conductive fillers, adhesives, solvents, and additives. Conductive fillers include conductive metal powders (e.g., silver powder, copper powder, gold powder), graphite, carbon black, carbon fiber, etc. Adhesives include epoxy resins, alkyd resins, acrylic resins, polyurethane resins, melamine-formaldehyde resins, phenolic resins, vinyl chloride-vinyl acetate copolymer resins, etc. Solvents include organic liquids capable of dissolving the adhesive, such as alcohol solvents, ester solvents, ketone solvents, and ether ester solvents. Specifically, the solvent may be a medium-boiling-point solvent with a boiling point between 120°C and 230°C. Additives may include dispersants, slip agents, coupling agents, etc.

[0087] In other embodiments, the orthographic projection of the conductive connection layer 40 onto the battery body 10 is one or more of the following: circular, elliptical, or polygonal (e.g., rectangular, square, etc.). Of course, the specific shape and structure of the conductive connection layer 40 can be flexibly set according to actual needs, and this application embodiment does not limit it in this regard.

[0088] It should be noted that the insulating layer 50 can be made of insulating materials such as insulating adhesive, insulating ink, and UV adhesive. Of course, it can also be made of other insulating materials, which can be flexibly selected according to actual needs. This application does not limit this.

[0089] In some embodiments, the fine grid electrode 20 and the main grid electrode 30 are made of the same material. Specifically, both the fine grid electrode 20 and the main grid electrode 30 are made of a non-burn-through paste. Further, the non-burn-through paste can be formed from low-temperature silver-coated copper paste, low-temperature copper paste, low-temperature nickel paste, etc. The use of low-temperature silver-free metallization technology for the main grid electrode 30 and the fine grid electrode 20 avoids the price and supply disadvantages of silver paste products, saves resources from high-temperature technology, and avoids the thermal effects introduced by high-temperature technology, effectively reducing production costs. More specifically, the non-burn-through fine grid electrode 20 and the main grid electrode 30 can be made of base metal paste, further reducing the cost of the solar cell. Of course, the fine grid electrode 20 and the main grid electrode 30 can also be made of other materials, which can be flexibly selected by those skilled in the art according to actual needs, and are not limited here. It should be noted that base metal mainly refers to materials that do not contain silver or contain very little silver. The base metal paste mentioned here may include: copper paste, aluminum paste, or paste with a precious metal content of less than 50% by mass. The precious metal may include silver. For example, the base metal mentioned here may be silver-coated copper paste, etc.

[0090] It is understood that, using the solar cell structure of this application, since the fine grid electrode 20 and the main grid electrode 30 can be processed simultaneously in a one-time molding process, the fine grid electrode 20 and the main grid electrode 30 can be fabricated from the same material. This helps to improve the bonding strength and conductivity of the fine grid electrode 20 and the main grid electrode 30, which have the same conductivity type, at the connection point, thereby improving the performance of the solar cell. Furthermore, since the fine grid electrode 20 and the main grid electrode 30 can be made from the same material, it is not necessary to design and process different materials for the fine grid electrode 20 and the main grid electrode 30 separately, thus simplifying the processing flow and reducing manufacturing costs.

[0091] Specifically, such as Figure 4 and Figure 5 As shown, the sub-electrode 21 includes a main body portion 211 and an overlapping portion 212 connected to each other. The main body portion 211 is electrically connected to the battery body 10, and the overlapping portion 212 extends to the conductive connection layer 40 and forms an electrical connection with the conductive connection layer 40. In this way, the main body portion 211 collects the charge carriers generated in the corresponding area of ​​the battery body 10, while the charge carriers generated in the corresponding area where the fine grid electrode 20 is disconnected are collected by the conductive connection layer 40. Furthermore, by extending the overlapping portion 212 of the sub-electrode 21 to the conductive connection layer 40 and forming an electrical connection with the conductive connection layer 40, the connection strength and conductivity between the sub-electrode 21 and the conductive connection layer 40 are improved. At the same time, it also facilitates the one-time processing and forming of the fine grid electrode 20 and the main grid electrode 30.

[0092] Optionally, such as Figure 4 and Figure 5As shown, the overlapping portion 212 extends to cover the side of the conductive connection layer 40 away from the battery body 10, so as to form an overlap with the conductive connection layer 40.

[0093] In this embodiment, the conductive connection layer 40 covers the surface of the battery body 10 at the junction, so that the overlapping portion 212 of the sub-electrode 21 extends to cover the side of the conductive connection layer 40 away from the battery body 10, thereby increasing the contact area between the overlapping portion 212 and the conductive connection layer 40. This not only improves the connection strength between the sub-electrode 21 and the conductive connection layer 40, but also improves the conductivity between the sub-electrode 21 and the conductive connection layer 40, and facilitates the one-time processing and forming of the fine grid electrode 20 and the main grid electrode 30.

[0094] Optionally, such as Figure 7 and Figure 8 As shown, the conductive connection layer 40 has an opening 401 along the edge of the second direction Y, and the overlapping portion 212 is at least partially embedded in the opening 401.

[0095] In this embodiment of the application, by providing an opening 401 in the conductive connection layer 40 at a position corresponding to the overlap portion 212 of the sub-electrode 21, the overlap portion 212 can be at least partially embedded in the opening 401, thereby increasing the connection strength between the sub-electrode 21 and the conductive connection layer 40.

[0096] In some embodiments, such as Figure 7 As shown, the projected area of ​​the overlapping portion 212 on the battery body 10 can be equal to the projected area of ​​the opening 401 on the battery body 10, so that the overlapping portion 212 can be precisely embedded in the opening 401 of the conductive connection layer 40. That is, at the opening 401, the conductive connection layer 40 surrounds the overlapping portion 212 and forms an electrical connection with the overlapping portion 212.

[0097] In other embodiments, such as Figure 8 As shown, the projected area of ​​the overlapping portion 212 on the battery body 10 is larger than the projected area of ​​the opening 401 on the battery body 10. That is, part of the overlapping portion 212 is embedded in the opening 401 of the conductive connection layer 40, and part of the overlapping portion 212 extends to cover the conductive connection layer 40 around the opening 401. In this way, the contact area between the overlapping portion 212 and the conductive connection layer 40 can be increased, thereby increasing the bonding force and conductivity between the sub-electrode 21 and the conductive connection layer 40.

[0098] It is understood that, along the thickness direction of the battery body 10, the opening 401 penetrates the conductive connection layer 40, and the portion of the overlapping part 212 embedded in the opening 401 is electrically connected to both the conductive connection layer 40 and the battery body 10 at the opening 401.

[0099] It should be noted that when the conductive connection layer 40 has a sub-electrode 21 on one side along the second direction Y, the conductive connection layer 40 has a corresponding opening 401; when the conductive connection layer 40 has sub-electrodes 21 on both sides along the second direction Y, the conductive connection layer 40 has two corresponding openings 401, and each opening 401 corresponds to the overlapping part 212 of a sub-electrode 21.

[0100] Optionally, such as Figure 4 As shown, along the thickness direction of the battery body 10, the thickness of the overlapping portion 212 is h2, and the thickness of the main body portion 211 is h1, satisfying: 0.8≤h2 / h1≤1. For example, h2 / h1 can be set to 0.8, 0.85, 0.9, 0.95, 1, etc.

[0101] In this embodiment, by setting the ratio of the thickness h2 of the overlap portion 212 to the thickness h1 of the main body portion 211 to be between 0.8 and 1, it is possible to ensure both the ability of the main body portion 211 of the sub-electrode 21 to collect charge carriers in the battery body 10, and the connection strength and conductivity between the overlap portion 212 of the sub-electrode 21 and the conductive connection layer 40. Simultaneously, based on the thickness h1 of the main body portion 211, the thickness of the overlap portion 212 can be appropriately reduced, thereby reducing the thickness difference between the surface of the battery body 10 at the overlap portion 212 and the main body portion 211, and thus reducing the risk of microcracks in the battery body 10 due to the thickness difference during processing.

[0102] It is understandable that in the process of preparing solar cells into photovoltaic modules, it is also necessary to lay encapsulation films, front plates, back plates, etc. on the cell body 10, and then obtain laminates through lamination. If the height difference at different positions on the cell body 10 is too large, it is easy to cause local microcracks or damage to the cell body 10 during the lamination process, which will affect the performance of the photovoltaic module.

[0103] Optionally, such as Figure 4 As shown, the thickness h1 of the main body 211 ranges from 5μm to 35μm. By setting the thickness h1 of the main body 211 to between 5μm and 35μm, the carrier collection capability of the main body 211 of the sub-electrode 21 is ensured, while avoiding excessive thickness of the main body 211 of the sub-electrode 21, which would result in a large height difference at different positions on the surface of the battery body 10. This avoids affecting the battery lamination process and also saves material costs.

[0104] For example, the thickness h1 of the main body 211 can be set to: 5μm, 8μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, etc.

[0105] Optionally, such as Figure 4As shown, the length of the overlap portion 212 along the second direction Y is W1, satisfying: W1 ≥ 25 μm. Preferably, W1 is in the range of 15 μm-30 μm. By setting the length W1 of the overlap portion 212 of the sub-electrode 21 along the second direction Y to be greater than or equal to 25 μm, the connection strength and conductivity between the overlap portion 212 and the conductive connection layer 40 are ensured.

[0106] For example, the length W1 of the overlapping portion 212 can be set to: 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 100μm, etc.

[0107] Optionally, such as Figure 4 As shown, the width of the second gap M2 along the second direction Y is W2, which satisfies: W2 ≥ 15 μm. Preferably, W2 is in the range of 15 μm to 80 μm.

[0108] It is understandable that the materials used to prepare the insulating layer 50 typically contain organic matter. During the molding and processing of the insulating layer 50, the organic matter in the processing material will diffuse outwards and cover the conductive connecting layers 40 on both sides of the insulating layer 50. When the overlap 212 extends onto the conductive connecting layer 40 and connects with it, if the distance between the overlap 212 and the insulating layer 50 is too small, the overlap 212 will connect with the conductive connecting layer 40 whose surface is covered with organic matter. Due to the influence of the organic matter, the bonding force and conductivity between the overlap 212 and the conductive connecting layer 40 will be reduced.

[0109] Therefore, in this application, a second gap M2 greater than or equal to 15 μm is provided between one end of the overlap portion 212 of the sub-electrode 21 and the corresponding insulating layer 50, so as to reserve a certain safety area between the sub-electrode 21 and the insulating layer 50. This facilitates the simultaneous processing of the fine grid electrode 20 and the main grid electrode 30 using a one-time processing molding process, and also ensures the connection performance between the overlap portion 212 of the sub-electrode 21 and the conductive connection layer 40.

[0110] Specifically, the width W2 of the second gap M2 can be set to: 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 80μm, 100μm, etc.

[0111] Optionally, such as Figure 4As shown, at the first intersection, the length L1 of the conductive connection layer 40 along the second direction Y is greater than the length L2 of the insulating layer 50 along the second direction Y. This allows a portion of the surface of the conductive connection layer 40 to remain uncovered by the insulating layer 50, thus enabling electrical connection with the disconnected fine grid electrode 20. This structural design allows for the pre-fabrication of the conductive connection layer 40 and the insulating layer 50 during battery processing, followed by simultaneous fabrication of the fine grid electrode 20 and the main grid electrode 30 in a single process, simplifying the manufacturing process. Furthermore, it facilitates the formation of an overlap structure between the fine grid electrode 20 and the conductive connection layer 40 at the disconnection point, thereby improving the connection strength and conductivity between the fine grid electrode 20 and the conductive connection layer 40.

[0112] Optionally, such as Figure 4 As shown, along the second direction Y, the length L1 of the conductive connection layer 40 and the length L2 of the insulating layer 50 satisfy: 0.5 ≤ L2 / L1 ≤ 0.9. For example, L2 / L1 can be set to 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.

[0113] In this application, by setting the ratio L2 / L1 of the length L1 of the conductive connection layer 40 to the length L2 of the insulating layer 50 to be between 0.5 and 0.9, it is possible to ensure that the insulating layer 50 has sufficient length in the second direction Y to form an insulating isolation between the conductive connection layer 40 and the main gate electrode 30, while also reserving a certain area on the conductive connection layer 40 that is not covered by the insulating layer 50, so as to form an electrical connection with the fine gate electrode 20.

[0114] In some embodiments, such as Figure 4 As shown, along the second direction Y, the length L1 of the conductive connection layer 40 and the length L2 of the insulating layer 50 satisfy: L1-L2≥80μm. For example, the value of L1-L2 can be set to: 80μm, 90μm, 100μm, 120μm, 150μm, 200μm, etc.

[0115] In this embodiment, by setting the difference between the length L1 of the conductive connection layer 40 and the length L2 of the insulating layer 50 to be greater than or equal to 80 μm, a portion of the surface of the conductive connection layer 40 is not covered by the insulating layer 50 in the second direction Y, thereby forming an electrical connection with the fine gate electrode 20, while also saving the manufacturing cost of the conductive connection layer 40.

[0116] In some embodiments, such as Figure 4As shown, the length of the insulating layer 50 along the second direction Y is L2, and the width of the main gate electrode 30 along the second direction Y is L3, satisfying: 0.3≤L3 / L2<1. Specifically, L3 / L1 can be set to: 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.99, etc.

[0117] In this embodiment, by setting the length L2 of the insulating layer 50 along the second direction Y to be greater than the width L3 of the main gate electrode 30 along the second direction Y, the insulating layer 50 ensures its insulating isolation effect between the main gate electrode 30 and the conductive connection layer 40. Furthermore, by setting L3 / L1 to be greater than or equal to 0.3, the material waste of the insulating layer 50 is avoided due to a large difference between the length L2 of the insulating layer 50 and the width L3 of the main gate electrode 30. Simultaneously, it also avoids the insulating layer 50 being too wide, occupying too much space on the conductive connection layer 40, thereby affecting the electrical connection between the conductive connection layer 40 and the fine gate electrode 20.

[0118] In some embodiments, the thickness of the conductive connection layer 40 ranges from 1 μm to 10 μm. For example, the thickness of the conductive connection layer 40 can be set to 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0119] In this embodiment, by setting a reasonable thickness range for the conductive connection layer 40, it is ensured that the conductive connection layer 40 has a certain thickness to collect and transport charge carriers in the battery body 10. At the same time, it also avoids the conductive connection layer 40 being too thick, which would cause a large height difference between the height at the junction and the height of other areas on the battery body 10, thereby affecting the subsequent processing of the battery and helping to reduce the risk of local microcracks in the battery body 10.

[0120] In some embodiments, the thickness of the insulating layer 50 ranges from 1 μm to 30 μm. For example, the thickness of the insulating layer 50 can be set to 1 μm, 3 μm, 5 μm, 7 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc.

[0121] Understandably, if the insulating layer 50 is too thin, it is easily punctured, causing a short circuit between the main grid electrode 30 and the fine grid electrode 20, which have opposite conductivity types. Conversely, if the insulating layer 50 is too thick, it not only increases production costs but also increases the height of the junction. Therefore, in this application, the thickness of the insulating layer 50 is set between 1μm and 30μm. This ensures that the insulating layer 50 has a certain thickness to effectively insulate and isolate the conductive connection layer 40 from the main grid electrode 30. At the same time, it also avoids the insulating layer 50 being too thick, which would cause a large height difference between the height of the junction and other areas on the battery body 10, thereby reducing the risk of local microcracks during the processing of the battery body 10.

[0122] In some embodiments, the thickness of the main gate electrode 30 ranges from 3μm to 35μm. For example, the thickness of the main gate electrode 30 can be set to 3μm, 5μm, 8μm, 10μm, 15μm, 20μm, 25μm, 30μm, etc.

[0123] In this embodiment, by setting a reasonable thickness range for the main grid electrode 30, both the connection and conductivity of the main grid electrode 30 can be ensured, facilitating a good electrical connection between the main grid electrode 30 and other main grid electrodes 30 of the same conductivity type, so as to utilize the main grid electrode 30 to collect the charge carriers collected by the fine grid electrode 20. Simultaneously, it avoids the main grid electrode 30 being too thick, which would result in a large height difference between the height at the junction and other areas on the battery body 10, thereby reducing the risk of local microcracks occurring during the processing of the battery body 10.

[0124] Optionally, embodiments of this application also provide a photovoltaic module, including multiple battery strings, each battery string including multiple solar cells and multiple interconnecting elements, the interconnecting elements being used to connect the multiple solar cells in series; wherein, the solar cells are the solar cells in the above embodiments.

[0125] In this embodiment, by disconnecting the fine grid electrode 20 at the junction with the main grid electrode 30 (which has the opposite conductivity type) and maintaining a first gap between the end of the sub-electrode 21 and the main grid electrode 30, mutual interference between the layout structures of the fine grid electrode 20 and the main grid electrode 30 (which have opposite conductivity types) on the battery body can be avoided. Simultaneously, by providing a conductive layer between the fine grid electrode 20 and the battery body 10, electrical connection between the fine grid electrode 20 and the battery body 10 is achieved. This facilitates the simultaneous fabrication of the main grid electrode 30 and the fine grid electrode 20 using a low-temperature slurry in a single process, thereby simplifying the process flow and reducing production costs.

[0126] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0127] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A solar cell, characterized in that, include: The battery body has intersecting first and second directions; the battery body is provided with a plurality of fine grid electrodes arranged at intervals along the first direction and a plurality of main grid electrodes arranged at intervals along the second direction; wherein, the conductivity types of two adjacent fine grid electrodes are opposite, and the conductivity types of two adjacent main grid electrodes are opposite. The fine grid electrode and the main grid electrode, which have opposite conductivity types, have a first junction. The fine grid electrode is disconnected at the first junction to form a plurality of discontinuously arranged sub-electrodes. A first gap is provided between the end of the sub-electrode and the main grid electrode. A conductive layer is provided between the fine grid electrode and the battery body. The fine grid electrode is electrically connected to the battery body through the conductive layer.

2. The solar cell according to claim 1, characterized in that, The battery body includes a silicon substrate and a doped semiconductor layer formed on the silicon substrate; The conductive layer is covered on the doped semiconductor layer, and both the main gate electrode and the fine gate electrode are disposed on the conductive layer; Alternatively, a dielectric layer may be further covered on the doped semiconductor layer, and a plurality of vias may be provided in the dielectric layer to expose the doped semiconductor layer in corresponding areas. The conductive layer may be provided in the vias; the fine gate electrode extends at least partially into the vias and forms an electrical connection with the doped semiconductor layer through the conductive layer.

3. The solar cell according to claim 1, characterized in that, The conductive layer includes a transparent conductive layer or a base metal layer.

4. The solar cell according to claim 1, characterized in that, The fine gate electrode and the main gate electrode, which have the same conductivity type, have a second junction. The fine gate electrode and the main gate electrode form an integral structure at the second junction. The thickness of the integral structure is greater than or equal to the thickness of the fine gate electrode.

5. The solar cell according to claim 1, characterized in that, An insulating layer is provided between the main grid electrode and the battery body at the first junction, and a second gap exists between the end of the sub-electrode and the corresponding insulating layer.

6. The solar cell according to claim 5, characterized in that, The width of the second gap along the second direction is W2, which satisfies: W2≥15μm.

7. The solar cell according to claim 5, characterized in that, The battery body is further provided with a conductive connection layer at the first junction, and two adjacent sub-electrodes are electrically connected through the conductive connection layer. The insulating layer is disposed between the conductive connection layer and the main grid electrode. The sub-electrode includes a main body and an overlapping part that are connected to each other. The main body is electrically connected to the battery body, and the overlapping part extends to the conductive connection layer and forms an electrical connection with the conductive connection layer.

8. The solar cell according to claim 7, characterized in that, The overlapping portion extends to cover the side of the conductive connection layer opposite to the battery body, so as to form an overlap with the conductive connection layer.

9. The solar cell according to claim 7, characterized in that, The conductive connection layer has an opening along the edge of the second direction, and the overlapping portion is at least partially embedded in the opening.

10. The solar cell according to claim 7, characterized in that, The thickness of the overlapping part is h2, and the thickness of the main body part is h1, satisfying: 0.8≤h2 / h1≤1.

11. The solar cell according to claim 10, characterized in that, The thickness h1 of the main body is in the range of 5μm-35μm.

12. The solar cell according to claim 7, characterized in that, The length of the overlapping portion along the second direction is W1, which satisfies: W1≥25μm.

13. The solar cell according to claim 7, characterized in that, Along the second direction, the length L1 of the conductive connection layer and the length L2 of the insulating layer satisfy: 0.5≤L2 / L1≤0.9, and / or, L1-L2≥80μm.

14. The solar cell according to any one of claims 7-13, characterized in that, The solar cell must satisfy at least one of the following conditions: A. The length of the insulating layer along the second direction is L2, and the width of the main gate electrode along the second direction is L3, satisfying: 0.3≤L3 / L2<1; B. The thickness range of the conductive connection layer is 1μm-10μm; C. The thickness range of the insulating layer is 1μm-30μm; D. The orthographic projection shape of the conductive connection layer on the battery body is one or a combination of two or more of the following: circular, elliptical, and polygonal.

15. The solar cell according to any one of claims 1-13, characterized in that, The solar cell must satisfy at least one of the following conditions: E. The thickness range of the main gate electrode is 3μm-35μm; F. The fine gate electrode and the main gate electrode are made of the same material, including copper; G. The width of the first gap along the second direction is W3, which satisfies: 0.01mm≤W3≤3mm.

16. A photovoltaic module, characterized in that, It includes multiple battery strings, each battery string comprising multiple solar cells and multiple interconnecting elements, the interconnecting elements being used to connect the multiple solar cells together in series; The solar cell is any one of claims 1-15.

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