Chip packaging structure, memory and electronic equipment
By employing horizontal laying and staggered stacking in the chip packaging structure, and utilizing the transfer lines of the intermediate substrate to bypass the space near the main control chip, the risks of glue contamination and bulging are solved, resulting in more efficient chip packaging and lower maintenance costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BIWIN STORAGE TECH CO LTD
- Filing Date
- 2025-06-10
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, the stacking method of the main control chip and NAND flash memory chip has the problems of high risk of glue contamination and finger bonding, and high risk of finished product bulging.
The chip packaging structure is adopted, in which the main control chip and chipset are laid horizontally on the bottom substrate. The middle part of the chipset is inserted through the intermediate substrate, and the first wire bonding point is set on the side of the lower chipset away from the main control chip to directly connect to the bottom substrate. The upper chipset is indirectly connected to the bottom substrate through the adapter line of the intermediate substrate, avoiding glue contamination of the wire bonding fingers.
It reduces the risk of wire bonding failure and finished product bulging, simplifies the wire bonding process, improves production efficiency, and reduces maintenance costs and signal crosstalk.
Smart Images
Figure CN224250164U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure, memory, and electronic device. Background Technology
[0002] Embedded memory chip particles internally encapsulate the main control chip and NAND flash memory chips. The number of communication I / O channels between the main control chip and NAND has increased from the original 1 channel, 2 channels to the current 4 channels, which brings greater difficulty to the substrate design, stacking layout and I / O routing.
[0003] like Figure 1 and Figure 2 As shown, there are two main stacking methods for existing controller chips and NAND flash memory chips:
[0004] 1. The main control chip and NAND flash memory chips can be laid horizontally, and the NAND chips can be stacked in a stepped manner with wires bonded on both sides;
[0005] 2. The main control chip is attached to the substrate, and the NAND flash memory chips are stacked on top of the main control chip. The suspended part between the NAND flash memory chips and the substrate is supported by virtual support blocks.
[0006] In the first stacking method, after the controller chip and NAND flash memory chip are laid flat, there is not enough space for the adhesive because the gap between the controller chip and the NAND flash memory chip is used to lay the bonding fingers of the NAND flash memory chip. This will cause the adhesive to contaminate the bonding fingers, resulting in a higher risk of bonding failure. In the second method, because the controller chip needs to be buried under the NAND flash memory chip, a chip coating process is used, which results in a higher risk of bulging in the finished product. Utility Model Content
[0007] The technical problem to be solved by this utility model is to propose a chip packaging structure, memory and electronic device to avoid glue contamination of the bonding fingers connecting the main control chip I / O and NAND flash memory chip, thereby reducing the high risk of packaging wire bonding failure and the risk of finished product bulging.
[0008] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:
[0009] A chip packaging structure includes an underlying substrate, a main control chip, and a chipset;
[0010] The main control chip and the chipset are horizontally laid out on the bottom substrate;
[0011] The chipset includes an upper chipset, an intermediate substrate, and a lower chipset. The lower chipset, the intermediate substrate, and the upper chipset are stacked sequentially and staggered on the bottom substrate. The intermediate substrate is provided with a transition circuit.
[0012] The lower-layer chipset has a first wire bonding point on the side away from the main control chip. The first wire bonding point is electrically connected to the bottom substrate. The upper-layer chipset has a second wire bonding point. The second wire bonding point is electrically connected to one end of the adapter line, and the other end of the adapter line is electrically connected to the bottom substrate.
[0013] Furthermore, the upper-layer chipset includes at least two first memory chips stacked in a staggered manner;
[0014] The second wire bonding point is located on the upper surface of the first memory chip that is not overlapped by the first memory chip of the previous layer. The second wire bonding point corresponds one-to-one with the transition line of the intermediate substrate and is electrically connected.
[0015] Furthermore, the size of the intermediate substrate is the same as the size of the first memory chip.
[0016] Furthermore, all the first memory chips are staggered or overlapped in a stepped manner.
[0017] Furthermore, the second bonding point is located on the side of the upper-layer chipset closer to the main control chip.
[0018] Furthermore, the lower-level chipset includes at least two second memory chips stacked in a stepped manner;
[0019] The first bonding point is located on the upper surface of the second memory chip that is not overlapped by the upper layer of the second memory chip or the intermediate substrate.
[0020] Furthermore, a third bonding point is provided on the adapter cable;
[0021] The third bonding point is electrically connected to the bottom substrate.
[0022] Furthermore, the adapter line is located on the upper surface of the intermediate substrate, close to the main control chip and not overlapped by the upper chip group.
[0023] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is as follows:
[0024] The memory includes a motherboard and the aforementioned chip package structure, wherein the chip package structure is disposed on the motherboard.
[0025] To solve the above-mentioned technical problems, another technical solution adopted by this utility model is as follows:
[0026] An electronic device includes the memory described above.
[0027] The beneficial effects of this utility model are as follows: It provides a chip packaging structure, memory, and electronic device. Based on the horizontal laying of the main control chip and chipset on the bottom substrate, an intermediate substrate is inserted in the middle part of the chipset. For the lower chipset, a first wire bonding point is set on the side away from the main control chip to directly connect to the bottom substrate. The upper chipset needs to be indirectly connected to the bottom substrate through the adapter line of the intermediate substrate. The adapter line can bypass the space near the main control chip and establish wire bonding fingers with the bottom substrate, avoiding the wire bonding fingers from being contaminated by glue. Compared with the existing solution, it can reduce the high risk of packaging wire bonding failure and the risk of finished product bulging. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of a stacked structure of existing main control chips and NAND flash memory chips.
[0029] Figure 2 This is a schematic diagram of another stacking structure for existing main control chips and NAND flash memory chips;
[0030] Figure 3 This is a schematic diagram of a chip packaging structure according to the present invention.
[0031] Label Explanation:
[0032] 1. Bottom substrate; 2. Main control chip; 3. Upper chipset; 4. Middle substrate; 5. Lower chipset; 6. First bonding point; 7. Second bonding point; 8. Third bonding point. Detailed Implementation
[0033] To explain in detail the technical content, objectives, and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0034] Please refer to Figure 3 A chip packaging structure includes a base substrate 1, a main control chip 2, and a chipset;
[0035] The main control chip 2 and the chipset are horizontally laid out on the bottom substrate 1;
[0036] The chipset includes an upper chipset 3, an intermediate substrate 4, and a lower chipset 5. The lower chipset 5, the intermediate substrate 4, and the upper chipset 3 are stacked sequentially and staggered on the bottom substrate 1. The intermediate substrate 4 is provided with a transfer circuit.
[0037] The lower-layer chipset 5 has a first bonding point 6 on the side away from the main control chip 2. The first bonding point 6 is electrically connected to the bottom substrate 1. The upper-layer chipset 3 has a second bonding point 7. The second bonding point 7 is electrically connected to one end of the adapter line, and the other end of the adapter line is electrically connected to the bottom substrate 1.
[0038] As can be seen from the above description, the beneficial effects of this utility model are as follows: Based on the horizontal laying of the main control chip 2 and the chipset on the bottom substrate 1, an intermediate substrate 4 is inserted in the middle part of the chipset. For the lower chipset 5, a first wire bonding point 6 is set on the side away from the main control chip 2 to be directly electrically connected to the bottom substrate 1. The upper chipset 3 needs to be indirectly electrically connected to the bottom substrate 1 through the adapter line of the intermediate substrate 4. The adapter line can bypass the space near the main control chip 2 and establish a wire bonding finger with the bottom substrate 1, avoiding the wire bonding finger from being contaminated by glue. Compared with the existing solution, it can reduce the high risk of packaging wire bonding failure and the risk of finished product bulging.
[0039] Furthermore, the upper-layer chipset 3 includes at least two first memory chips stacked in a staggered manner;
[0040] The second bonding point 7 is located on the upper surface of the first memory chip that is not overlapped by the first memory chip of the previous layer. The second bonding point 7 corresponds one-to-one with the transition line of the intermediate substrate 4 and is electrically connected.
[0041] As can be seen from the above description, by staggered stacking, the upper surface of each first memory chip has an unobstructed area, which is convenient for setting the second bonding point 7. This avoids the problem of bonding points being covered by upper-layer chips in traditional stacking, and electrical connection can be achieved without the need for complex side bonding or through-hole processes.
[0042] Furthermore, the size of the intermediate substrate 4 is the same as the size of the first memory chip.
[0043] As described above, the size of the intermediate substrate 4 is the same as that of the first memory chip, eliminating redundant space at the edge of the substrate in traditional packaging, making the overall package size more compact and meeting the requirements of high-density storage.
[0044] Furthermore, all the first memory chips are staggered or overlapped in a stepped manner.
[0045] As described above, the stepped structure ensures that the second bonding points 7 of each first memory chip are located on the same side and at the same height, simplifying the bonding process and improving production efficiency. Furthermore, if a chip malfunctions, the stepped layout facilitates individual testing and replacement, reducing maintenance costs. The stepped gaps between adjacent chips form a natural shield, reducing signal crosstalk.
[0046] Furthermore, the second bonding point 7 is located on the side of the upper chipset 3 closest to the main control chip 2.
[0047] As can be seen from the above description, the wire bonding direction is towards the main control chip 2, which makes the signal path between the upper storage chip and the main control chip the shortest, and the routing length of the transfer line can also be shortened, reducing latency and improving data read and write speed; reducing power consumption: the short path reduces signal attenuation and reduces the driving power requirement; the wire bonding is concentrated on one side, which facilitates the wiring planning of the bottom substrate 1, reduces the number of line crossings and interlayer vias, and reduces wiring complexity.
[0048] Furthermore, the lower-level chipset 5 includes at least two second memory chips stacked in a stepped manner;
[0049] The first bonding point 6 is located on the upper surface of the second memory chip that is not overlapped by the upper layer of the second memory chip or the intermediate substrate 4.
[0050] As can be seen from the above description, the lower-layer chip is directly connected to the bottom substrate 1 through the first bonding point 6; the stepped layout can stack more chips, and the gaps between the chips increase the heat dissipation area.
[0051] Furthermore, a third punch point 8 is provided on the adapter cable;
[0052] The third bonding point 8 is electrically connected to the bottom substrate 1.
[0053] As can be seen from the above description, the third bonding point 8 can be connected to the bottom substrate 1 independently through the bonding fingers. Combined with the changes in the routing of the adapter circuit, the bonding fingers are effectively prevented from being contaminated by glue.
[0054] Furthermore, the adapter line is located on the upper surface of the intermediate substrate 4, close to the main control chip 2 and not overlapped by the upper chip group 3.
[0055] As can be seen from the above description, the uncovered area can accommodate more complex switching lines without worrying about physical interference with upper-layer chips, thus increasing the flexibility of wiring.
[0056] Example 1
[0057] A chip packaging structure, such as Figure 3As shown, the system includes a bottom substrate 1, a main control chip 2, and a chipset. The main control chip 2 and the chipset are horizontally laid out on the bottom substrate 1. The chipset includes an upper chipset 3, an intermediate substrate 4, and a lower chipset 5. The lower chipset 5, the intermediate substrate 4, and the upper chipset 3 are stacked sequentially and staggered on the bottom substrate 1. The intermediate substrate 4 is provided with a transfer line. The lower chipset 5 has a first bonding point 6 on the side away from the main control chip 2. The first bonding point 6 is electrically connected to the bottom substrate 1. The upper chipset 3 has a second bonding point 7. The second bonding point 7 is electrically connected to one end of the transfer line, and the other end of the transfer line is electrically connected to the bottom substrate 1.
[0058] In this embodiment, as Figure 3 As shown, the lower chipset 5 has a first wire bonding point 6 on the side away from the main control chip 2, so there is no need to worry about the bonding fingers connecting it to the bottom substrate 1 being contaminated by glue. However, the upper chipset 3 cannot also have a second wire bonding point 7 on the side away from the main control chip 2 due to information path crosstalk and other reasons. If the second wire bonding point 7 is set on the side of the upper memory chip close to the main control chip 2 and directly connected to the bottom substrate 1 by bonding fingers, it is easy to be contaminated by the glue used to fix the main control chip 2. Therefore, an intermediate substrate 4 is provided, and a transition line is set on the intermediate substrate 4. The second wire bonding point 7 is electrically connected to one end of the transition line, which bypasses the space near the main control chip 2 that is easily interfered with by glue. The other end of the transition line is electrically connected to the line on the bottom substrate 1 that connects to the I / O port of the main control chip 2.
[0059] Among them, such as Figure 3 As shown, the size of the intermediate substrate 4 is the same as that of the first memory chip. The upper chip group 3 includes at least two first memory chips stacked in a staggered manner. The second bonding point 7 is located on the upper surface of the first memory chip that is not overlapped by the first memory chip of the upper layer. The second bonding point 7 corresponds one-to-one with the transition line of the intermediate substrate 4 and is electrically connected. All the first memory chips are staggered or stacked in a stepped manner.
[0060] Furthermore, a third bonding point 8 is provided on the adapter line; the third bonding point 8 is electrically connected to the bottom substrate 1. The adapter line is located on the upper surface of the intermediate substrate 4, close to the main control chip 2 and not overlapped by the upper chip group 3.
[0061] like Figure 3 As shown, all the first memory chips are preferably stacked in a stepped manner, and all the second bonding points 7 are located on the side of the upper chip group 3 near the main control chip 2, that is, the second bonding point 7 is set on each "step" of the stepped stack; then the second bonding point 7 is bonded to the corresponding intermediate transfer line.
[0062] In this embodiment, the lower chipset 5 includes at least two second memory chips stacked in a stepped manner; the first bonding point 6 is located on the upper surface of the second memory chip that is not overlapped by the second memory chip of the upper layer or the intermediate substrate 4.
[0063] Example 2
[0064] The memory includes a motherboard and a chip package structure as described in Embodiment 1, wherein the chip package structure is disposed on the motherboard.
[0065] Example 3
[0066] An electronic device including the memory of Embodiment 2.
[0067] In summary, this utility model discloses a memory and an electronic device. Based on horizontally laying out the main control chip and chipset on a bottom substrate, an intermediate substrate is inserted into the middle portion of the chipset. For the lower chipset, a first wire bonding point is set on the side furthest from the main control chip, directly electrically connected to the bottom substrate. The upper chipset needs to be indirectly electrically connected to the bottom substrate through the adapter lines of the intermediate substrate. Using the adapter lines, the space near the main control chip can be bypassed, and wire bonding fingers can be established with the bottom substrate, avoiding glue contamination of the wire bonding fingers. Compared with existing solutions, this reduces the high risk of wire bonding failure and the risk of finished product bulging. When stacking memory chips, the stepped structure ensures that the second wire bonding points of each first memory chip are located on the same side and at the same height, simplifying the wire bonding process and improving production efficiency. Furthermore, if a chip fails, the stepped layout facilitates individual testing and replacement, reducing maintenance costs. The stepped gaps between adjacent chips form a natural shield, reducing signal crosstalk.
[0068] The above description is merely an embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent modifications made based on the content of this utility model specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of this utility model.
Claims
1. A chip packaging structure, characterized in that, This includes the underlying substrate, the main control chip, and the chipset; The main control chip and the chipset are horizontally laid out on the bottom substrate; The chipset includes an upper chipset, an intermediate substrate, and a lower chipset. The lower chipset, the intermediate substrate, and the upper chipset are stacked sequentially and staggered on the bottom substrate. The intermediate substrate is provided with a transition circuit. The lower-layer chipset has a first wire bonding point on the side away from the main control chip. The first wire bonding point is electrically connected to the bottom substrate. The upper-layer chipset has a second wire bonding point. The second wire bonding point is electrically connected to one end of the adapter line, and the other end of the adapter line is electrically connected to the bottom substrate.
2. The chip packaging structure according to claim 1, characterized in that, The upper-layer chipset includes at least two first memory chips stacked in a staggered manner; The second wire bonding point is located on the upper surface of the first memory chip that is not overlapped by the first memory chip of the previous layer. The second wire bonding point corresponds one-to-one with the transition line of the intermediate substrate and is electrically connected.
3. The chip packaging structure according to claim 2, characterized in that, The dimensions of the intermediate substrate are the same as those of the first memory chip.
4. The chip packaging structure according to claim 2, characterized in that, All of the first memory chips are either misaligned or overlapped in a stepped manner.
5. The chip packaging structure according to claim 1, characterized in that, The second bonding point is located on the side of the upper-layer chipset closer to the main control chip.
6. The chip packaging structure according to claim 1, characterized in that, The lower-level chipset includes at least two second memory chips stacked in a stepped manner; The first bonding point is located on the upper surface of the second memory chip that is not overlapped by the upper layer of the second memory chip or the intermediate substrate.
7. The chip packaging structure according to claim 1, characterized in that, The adapter cable is equipped with a third punch point; The third bonding point is electrically connected to the bottom substrate.
8. The chip packaging structure according to claim 1, characterized in that, The adapter line is located on the upper surface of the intermediate substrate, close to the main control chip and not overlapped by the upper-layer chipset.
9. A memory, characterized in that, The invention includes a motherboard and a chip packaging structure as described in any one of claims 1 to 8, wherein the chip packaging structure is disposed on the motherboard.
10. An electronic device, characterized in that, Includes the memory as described in claim 9.