High-voltage super junction terminal structure
By introducing cross-arranged P-pillars and N-pillars and a cutoff ring into the terminal structure of the high-voltage superjunction device, the problem of ineffective cutoff of electric field lines under small step pitch is solved, the withstand voltage performance and current handling capability of the device are improved, and the manufacturing process is simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHAANXI HUAMAO SEMICON TECH CO LTD
- Filing Date
- 2025-07-14
- Publication Date
- 2026-05-19
AI Technical Summary
Existing high-voltage superjunction devices have termination structures that cannot effectively cut off surface electric field lines with small step sizes, leading to breakdown point shift and increased leakage current, especially performance degradation at high temperatures.
The structure employs a cross-arranged P-pillar and N-pillar structure, and sets up a cutoff ring with adjustable depth and width in the terminal region, filled with a low dielectric constant insulating medium to enhance the electric field convergence and cutoff effect.
It effectively reduces leakage current, improves the device's withstand voltage and current handling capabilities, while simplifying the manufacturing process and reducing chip area.
Smart Images
Figure CN224265382U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of power semiconductor technology, specifically relating to a high-voltage superjunction termination structure. Background Technology
[0002] The on-resistance of conventional high-voltage MOSFETs exhibits a 2.5-power exponential relationship with their breakdown voltage, a phenomenon known in the industry as the "silicon limit." To address this issue, in the early 1990s, Chen Xingbi and others proposed introducing a composite buffer layer theory in the drift region, successfully transforming the one-dimensional triangular electric field distribution into a rectangular one. Through in-depth research and detailed calculations, it was determined that the on-resistance and breakdown voltage exhibit a 1.23-power exponential relationship. This structure was later dubbed the "superjunction MOSFET" and successfully commercialized. Its mechanism primarily utilizes charge balance theory, introducing a P-type impurity diffusion region into the N-type drift region, forming a regular cross-arrangement of P-pillar and N-pillar thin layers. When the device is under blocking conditions, if the positive and negative ionized charges in the periodic region reach a relative balance, the original one-dimensional triangular electric field distribution can be transformed into a two-dimensional approximate rectangular distribution, increasing the breakdown voltage. Therefore, while maintaining the same breakdown voltage, the impurity concentration in the drift region of a superjunction device can be an order of magnitude higher than that of a conventional VDMOS, resulting in a significant reduction in on-resistance and breaking through the so-called "silicon limit" of on-resistance in high-voltage MOSFETs.
[0003] Superjunction device structures are typically implemented in two ways: one is through multilayer epitaxy followed by selective ion implantation, and then a final push-through annealing; the other is through deep trenching followed by in-situ doped silicon epitaxy, and then backfilling the trenches. Multilayer epitaxy requires multiple epitaxial layers and photolithographic implantations, facing a series of challenges such as alignment accuracy, lateral diffusion during annealing, and charge balance control, making the process relatively more difficult. With advancements in modern IC (integrated circuit) technology, deep trenching, which facilitates doping control and charge balance, is increasingly becoming the mainstream process for superjunction devices.
[0004] Taking a deep trench superjunction MOS structure as an example, in the bottom region of the trench, in US patent US5216275, alternating P-pillar and N-pillar thin layers are connected to the N+ substrate. In US patent US6630698B1, the P-pillar and N-pillar thin layers can have a gap greater than zero with the N+ substrate. Currently, the latter approach is commonly used in deep trench superjunction device design because it improves the reverse recovery characteristics of the superjunction device. In the top region of the P-pillars, surface-mount devices can be fabricated directly using P-body implantation, or a short-thickness epitaxial layer can be added upwards before similar fabrication. The breakdown voltage of the unit cell in the middle region mainly depends on the impurity concentration distribution of the P-pillars and N-pillars, the pillar width, the trench depth, the total step size, the well concentration distribution, and the junction depth. These parameters can be calculated using relevant theories to obtain basic reference points, and then optimized and adjusted using simulation iterations. When a large breakdown voltage is required, the handling of the edge termination and corner electric field becomes crucial in superjunction device design, determining the performance of static breakdown voltage, power output, and dynamic surge parameters.
[0005] In recent years, the design of superjunction MOS devices has been continuously iterating and upgrading, with the most significant advancements being the reduction of cell pitch, increased breakdown voltage and current density, decreased on-resistance, and improved avalanche withstand capability. As the pitch decreases, the breakdown voltage capability of superjunction MOS devices becomes increasingly sensitive to the termination structure, particularly in terms of the ever-higher requirements for the cutoff efficiency of edge electric field lines. Simulation experiments show that for superjunction termination structures with smaller pitches, if surface electric field lines cannot be quickly and effectively cut off, it can lead to breakdown point shift and hotspot generation, especially with a rapid increase in leakage current and a rapid decrease in breakdown voltage at high temperatures. Utility Model Content
[0006] To address the aforementioned problems in the prior art, this invention provides a high-voltage superjunction termination structure. This structure enables rapid and effective convergence and cutoff of the surface electric field at the device termination edge, reducing leakage current under reverse bias and improving the device's withstand voltage performance. The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] This invention provides a high-voltage superjunction termination structure, comprising an N-type substrate and an N-type epitaxial layer disposed on the N-type substrate. The upper surface of the N-type epitaxial layer has multiple P-pillars spaced apart.
[0008] The terminal structure includes a terminal region located outside the active region. The plurality of P-pillars are located in the active region and the terminal region. The plurality of P-pillars and the N-type epitaxial layers between adjacent P-pillars form a plurality of alternating layers of P-pillars and N-pillars. At least one stop ring filled with insulating material is provided on the N-type epitaxial layer at the outer edge of the plurality of P-pillars. The depth of the stop ring is greater than or equal to the depth of the P-pillar.
[0009] A P-type body region is disposed inside the upper surface of the N-type epitaxial layer of the active region, and the outer end of the P-type body region extends to the terminal region; a field oxide layer is disposed on the upper surface of the N-type epitaxial layer of the terminal region, the field oxide layer including a terminal region oxide layer and an edge oxide layer disposed at intervals, the terminal region oxide layer being located above the P-pillar and the N-pillar, and the edge oxide layer being disposed at the edge of the terminal region; a gate oxide layer is also disposed on the upper surface of the N-type epitaxial layer and the field oxide layer;
[0010] A gate layer is disposed on the upper surface of the gate oxide layer located in the active region. A first polysilicon layer is disposed on the gate oxide layer above the terminal region oxide layer. A second polysilicon layer is disposed on the gate oxide layer between the terminal region oxide layer and the edge oxide layer. An insulating dielectric layer is covered on the upper surfaces of the gate layer, the first polysilicon layer, and the second polysilicon layer. A plurality of contact holes are etched on the insulating dielectric layer. The plurality of contact holes extend downward to contact the P-pillar, the first polysilicon layer, or the second polysilicon layer.
[0011] Each of the plurality of contact holes is provided with a metal layer to form a gate lead-out electrode and a source lead-out electrode; a drain electrode is provided on the lower surface of the N-type substrate.
[0012] In one embodiment of this utility model, the plurality of P pillars have the same depth, and the depth of the plurality of P pillars is less than the thickness of the N-type epitaxial layer; the width of the stop ring is less than or equal to the width of the P pillars.
[0013] In one embodiment of this utility model, the P-pillars in the active region are arranged in parallel and in a strip-like pattern, and the P-pillars in the terminal region are arranged in a ring and surround the P-pillars in the active region; or,
[0014] The P-pillars in the active region and the P-pillars in the terminal region are both distributed in a concentric ring.
[0015] In one embodiment of this invention, the insulating material filled in the stop ring is silicon dioxide or benzocyclobutene.
[0016] In one embodiment of this utility model, the width of the P-type body region is 30~80μm and the thickness is 2~5μm.
[0017] In one embodiment of this invention, the thickness of the field oxide layer is 2000~30000 angstroms, and the thickness of the gate oxide layer is 200~3000 angstroms.
[0018] Compared with the prior art, the beneficial effects of this utility model are as follows:
[0019] 1. The high-voltage superjunction terminal structure of this utility model adopts a cross-arranged P-pillar and N-pillar structure inside the terminal protection structure, which is simple in process; the outermost part of the terminal protection structure is provided with one or more cut-off rings, the depth of which is greater than or equal to that of the P-pillar, and the width is relatively wide, and is completely filled with a low dielectric constant insulating medium, which can fully absorb the electric field lines emitted by the P-pillar in the terminal area, eliminate the occurrence of leakage current, and effectively improve the withstand voltage performance of the terminal structure.
[0020] 2. The high-voltage superjunction terminal structure of this invention features a wide adjustable range for the depth and width of the stop ring, which helps reduce manufacturing difficulty. The depth of the stop ring can be the same as or slightly deeper than the P-pillar, allowing for one-piece molding with the P-pillar and saving manufacturing costs. The number and spacing of the stop rings can be set according to the breakdown voltage requirements, with good adjustment tolerance. The distance between the stop ring filled with insulating medium and the outermost protective ring P-pillar can be adjusted; the optimal distance can be determined through simulation.
[0021] 3. In the high-voltage superjunction termination structure of this invention, a P-type body region is formed at the top of the P-pillar through P-body injection, which increases the radius of curvature at the junction corner and reduces the electric field intensity at the edge corner, similar to the function of a field-limiting ring. The number, distribution density, and doping concentration of the terminal P-body injection region can be optimized. The distance between the P-type body region and the first P-pillar of the termination structure is determined through simulation calculation to prevent excessive electric field concentration at this location, which could lead to premature breakdown at the surface.
[0022] 4. This utility model uses a stop ring filled with a low dielectric constant insulating medium, which can further reduce the lateral dimensions of the P-pillar and N-pillar. Combined with other means of reducing the corner electric field, it can promote the further updating and iteration of superjunction device design, continuously reduce the chip area while maintaining the same withstand voltage capability, and improve the chip current handling capability per unit area.
[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of a high-voltage superjunction terminal structure provided in an embodiment of this utility model.
[0025] Explanation of reference numerals in the attached figures:
[0026] 1-N-type substrate; 2-N-type epitaxial layer; 3-P-pillar; 4-Stop ring; 5-P-type body region; 6-Field oxide layer; 61-Termination region oxide layer; 62-Edge oxide layer; 7-Gate oxide layer; 8-Gate layer; 9-First polysilicon layer; 10-Second polysilicon layer; 11-Insulating dielectric layer; 12-Contact hole; 13-Metal layer; 14-Drain electrode. Detailed Implementation
[0027] To further illustrate the technical means and effects adopted by this utility model to achieve its intended purpose, the following detailed description of a high-voltage superjunction terminal structure proposed according to this utility model is provided in conjunction with the accompanying drawings and specific embodiments.
[0028] The foregoing and other technical contents, features, and effects of this utility model will be clearly presented in the following detailed description of the specific embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by this utility model to achieve the intended purpose. However, the accompanying drawings are only provided for reference and illustration and are not intended to limit the technical solution of this utility model.
[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.
[0030] Please see Figure 1 , Figure 1This is a schematic diagram of a high-voltage superjunction termination structure provided in an embodiment of this utility model. The high-voltage superjunction termination structure includes an N-type substrate 1 and an N-type epitaxial layer 2 disposed on the N-type substrate 1. Multiple P-pillars 3 are spaced apart on the upper surface of the N-type epitaxial layer 2. The termination structure includes a termination region located outside the active region. The active region is the core region of the device, used to form the core element, and the termination region is used to form a voltage-resistant protective peripheral structure. The specific structural form of the core element in the active region can be designed as needed, and the structures of the termination region and the active region can be formed together. In this embodiment, the core element adopts a superjunction structure, that is, the superjunction structure of the core region has several alternating P-pillars and N-pillars. Multiple P-pillars 3 are located in the active region and the termination region. Multiple N-type epitaxial layers 2 between adjacent P-pillars 3 form multiple N-pillars, thus forming several layers of alternating P-pillars and N-pillars.
[0031] At least one stop ring 4 filled with insulating material is disposed on the N-type epitaxial layer 2 at the outer edge of multiple P-pillars 3. The stop ring 4 is annular and surrounds the periphery of the P-pillars 3, and the depth of the stop ring 4 is greater than or equal to the depth of the P-pillars 3. In this embodiment, an N-type material is used as the substrate of the device, and the N-type epitaxial layer 2 is grown on it. The material of the N-type epitaxial layer 2 is N-type doped silicon. The growth thickness and resistivity are determined according to the required withstand voltage of the device. Preferably, the thickness of the N-type epitaxial layer 2 is in the range of 5~200μm, and the resistivity is in the range of 1~100Ω·cm.
[0032] In other embodiments of this invention, the substrate may also be a silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate with a semiconductor layer doped with N-type or P-type dopant. The N-type epitaxial layer may have the same conductivity type as the substrate, but the doping concentration of the N-type epitaxial layer is lower than that of the substrate. The N-type epitaxial layer 2 may be a multilayer epitaxial stack structure.
[0033] In this embodiment, the multiple P-pillars 3 have the same depth, and the depth of each P-pillar 3 is less than the thickness of the N-type epitaxial layer 2. That is, the P-pillars 3 located in the active region and the P-pillars 3 located in the terminal region have the same depth, and their depths are all less than the thickness of the N-type epitaxial layer 2. Optionally, the distribution density of the P-pillars 3 in the active region (i.e., the spacing between adjacent P-pillars 3) is different from the distribution density of the P-pillars 3 in the terminal region, and the linewidth of the P-pillars 3 in the active region is different from the linewidth of the P-pillars 3 in the terminal region. As an example, the distribution density of the P-pillars 3 in the active region is greater than the distribution density of the P-pillars 3 in the terminal region, and the linewidth of the P-pillars 3 in the active region is smaller than the linewidth of the P-pillars 3 in the terminal region.
[0034] In this embodiment, the P-pillars 3 located in the active region and the P-pillars 3 located in the terminal region are arranged in parallel and in a strip-like pattern. In another embodiment of this utility model, the P-pillars 3 in the active region are arranged in parallel and in a strip-like pattern, and the P-pillars 3 in the terminal region are arranged in a ring and surround the P-pillars 3 in the active region; or, the P-pillars 3 in the active region and the P-pillars 3 in the terminal region are both distributed in a concentric ring-like pattern.
[0035] The width (line width) of the stop ring 4 is less than or equal to the width of the P-pillar 3. The insulating material filled in the stop ring 4 is silicon dioxide or benzocyclobutene. The depth of the stop ring 4 is 1~15μm, and the width is 0.6~10μm. In this embodiment, the stop ring is rectangular. In other embodiments of this invention, the stop ring can also be stepped, with the width decreasing gradually from top to bottom.
[0036] Furthermore, a P-type body region 5 is disposed inside the upper surface of the N-type epitaxial layer 2 of the active region, and the outer end of the P-type body region 5 extends to the terminal region. In this embodiment, the P-type body region 5 is formed by implanting P-type conductive ions onto the P-pillars 3 and N-pillars, with an implantation dose of 1e12~1e15. The width of the P-type body region 5 is 30~80 μm, and the thickness is 2~5 μm. In this embodiment, the P-type body region 5 is disposed adjacent to the edge of the active region and is formed on the top of at least one P-pillar 3 and / or N-pillar. For example, the P-type body region 5 is disposed on the top of four consecutive adjacent P-pillars 3 and N-pillars adjacent to the active region.
[0037] A field oxide layer 6 is disposed on the upper surface of the N-type epitaxial layer 2 in the terminal region. The field oxide layer 6 includes a terminal region oxide layer 61 and an edge oxide layer 62 disposed at intervals. The terminal region oxide layer is located above the P-pillars and N-pillars, and the edge oxide layer 62 is disposed at the edge of the terminal region. A gate oxide layer 7 is also disposed on the upper surface of the N-type epitaxial layer 2 and the field oxide layer 6. Preferably, the thickness of the field oxide layer 6 is 2000~30000 angstroms, and the thickness of the gate oxide layer 7 is 200~3000 angstroms.
[0038] A gate layer 8 is disposed on the upper surface of the gate oxide layer 7 located in the active region. A first polysilicon layer 9 is disposed on the gate oxide layer 7 above the terminal oxide layer 61. A second polysilicon layer 10 is disposed on the gate oxide layer 7 between the terminal oxide layer 61 and the edge oxide layer 62. An insulating dielectric layer 11 is covered on the upper surfaces of the gate layer 8, the first polysilicon layer 9, and the second polysilicon layer 10. A plurality of contact holes 12 are etched on the insulating dielectric layer 11. The plurality of contact holes 12 extend downward to the contact P pillar 3, the first polysilicon layer 9, or the second polysilicon layer 10. A metal layer 13 is disposed in each of the plurality of contact holes 12 to form a gate lead-out electrode and a source lead-out electrode. A drain electrode 14 is disposed on the lower surface of the N-type substrate 1.
[0039] Preferably, the insulating material used for the insulating dielectric layer 11 is silicon dioxide or other insulating material, with a thickness of 5000~30000 angstroms. The gate electrode and source electrode, i.e., the metal layer 13, are preferably aluminum-silicon-copper alloys with a thickness of 1~10μm; the drain electrode 14 is preferably a titanium-nickel-silver composite metal layer with a thickness of 0.3~5μm.
[0040] This utility model discloses a high-voltage superjunction terminal structure. The internal structure of the terminal protection structure employs a cross-arranged P-pillar and N-pillar structure, simplifying the manufacturing process. The outermost part of the terminal protection structure features one or more stop rings with a depth greater than or equal to the P-pillars and a wider width, completely filled with a low-dielectric-constant insulating medium. This effectively absorbs the electric field lines emitted by the internal protection rings, preventing leakage current and significantly improving the voltage withstand performance of the terminal structure. The depth and width of the stop rings have a wide adjustment range, reducing manufacturing difficulty. The depth of the stop rings can be the same as or slightly deeper than the P-pillars, allowing for one-piece molding with the P-pillars, saving manufacturing costs. The number and spacing of the stop rings can be set according to the breakdown voltage requirements, with good adjustment tolerance. The distance between the insulating-filled stop rings and the outermost protection ring P-pillar can be adjusted; the optimal distance can be determined through simulation.
[0041] This invention employs a stop ring filled with a low dielectric constant insulating medium, which can further reduce the lateral dimensions of the P-pillars and N-pillars. Combined with other methods to reduce the corner electric field, it enables the design of superjunction devices to be further updated and iterated, continuously reducing the chip area while maintaining the same withstand voltage capability, and improving the chip current handling capability per unit area.
[0042] In the several embodiments provided by this utility model, it should be understood that the apparatus and method disclosed in this utility model can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0043] Furthermore, in the various embodiments of this utility model, the functional modules can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in a combination of hardware and software functional modules.
[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the protection scope of the present invention.
Claims
1. A high-voltage superjunction terminal structure, characterized in that, It includes an N-type substrate (1) and an N-type epitaxial layer (2) disposed on the N-type substrate (1), wherein a plurality of P-pillars (3) are spaced apart on the upper surface of the N-type epitaxial layer (2), wherein, The terminal structure includes a terminal region located outside the active region. The plurality of P-pillars (3) are located in the active region and the terminal region. The plurality of P-pillars (3) and the N-type epitaxial layers (2) between adjacent P-pillars (3) form a plurality of alternating layers of P-pillars and N-pillars. At least one stop ring (4) filled with insulating material is provided on the N-type epitaxial layer (2) at the outer edge of the plurality of P-pillars (3). The depth of the stop ring is greater than or equal to the depth of the P-pillar. A P-type body region (5) is disposed inside the upper surface of the N-type epitaxial layer (2) of the active region, and the outer end of the P-type body region (5) extends to the terminal region; a field oxide layer (6) is disposed on the upper surface of the N-type epitaxial layer (2) of the terminal region, the field oxide layer (6) includes a terminal region oxide layer (61) and an edge oxide layer (62) disposed at intervals, the terminal region oxide layer (61) is located above the P-pillar and the N-pillar, and the edge oxide layer (62) is disposed at the edge of the terminal region; a gate oxide layer (7) is also disposed on the upper surface of the N-type epitaxial layer (2) and the field oxide layer (6); A gate layer (8) is disposed on the upper surface of the gate oxide layer (7) located in the active region. A first polysilicon layer (9) is disposed on the gate oxide layer (7) above the terminal region oxide layer (61). A second polysilicon layer (10) is disposed on the gate oxide layer (7) between the terminal region oxide layer (61) and the edge oxide layer (62). The upper surfaces of the gate layer (8), the first polysilicon layer (9), and the second polysilicon layer (10) are all covered with an insulating dielectric layer (11). A plurality of contact holes (12) are etched on the insulating dielectric layer (11). The plurality of contact holes (12) extend downward to contact the P-pillar (3), the first polysilicon layer (9), or the second polysilicon layer (10). Each of the plurality of contact holes (12) is provided with a metal layer (13) to form a gate lead-out electrode and a source lead-out electrode; a drain electrode (14) is provided on the lower surface of the N-type substrate (1).
2. The high-voltage superjunction terminal structure according to claim 1, characterized in that, The plurality of P pillars (3) have the same depth, and the depth of the plurality of P pillars (3) is less than the thickness of the N-type epitaxial layer (2); the width of the stop ring (4) is less than or equal to the width of the P pillars (3).
3. The high-voltage superjunction terminal structure according to claim 1, characterized in that, The P-pillars (3) in the active region are arranged in parallel and in a strip-like pattern, and the P-pillars (3) in the terminal region are arranged in a ring and surround the periphery of the P-pillars (3) in the active region; or, The P-pillars (3) in the active region and the P-pillars (3) in the terminal region are both distributed in a concentric ring.
4. The high-voltage superjunction terminal structure according to claim 1, characterized in that, The insulating material filled in the stop ring (4) is silicon dioxide or benzocyclobutene.
5. The high-voltage superjunction terminal structure according to claim 1, characterized in that, The width of the P-type body region (5) is 30~80μm and the thickness is 2~5μm.
6. The high-voltage superjunction terminal structure according to claim 1, characterized in that, The thickness of the field oxide layer (6) is 2000~30000 angstroms, and the thickness of the gate oxide layer (7) is 200~3000 angstroms.