A latch application circuit

Abstract

This utility model relates to the field of circuit design technology, and provides a latch application circuit, comprising a 4G communication module, a latch U1, and a SOC application chip. The latch U1 includes a latch enable pin LE, a latch pin D, an output status pin Q, and a power supply VCC. The 4G communication module includes a first GPIO port GPIO1 and a second GPIO port GPIO2. The latch enable pin LE is connected to the first GPIO port GPIO1 of the 4G communication module; the latch pin D is connected to the second GPIO port GPIO2 of the 4G communication module; and the output status pin Q is used to control the power supply of the SOC application chip. This utility model has a simple circuit structure, low cost, and can promptly supply power to the SOC application chip after the 4G communication module is powered off, based on the power supply status of the 4G communication module.

Description

Technical Field

[0001] This utility model relates to the field of circuit design technology, and more specifically, to a latch application circuit. Background Technology

[0002] In IoT products, a 4G communication module is often used as the main controller, while the System-on-a-Chip (SoC) is responsible for the specific application's product architecture. In such designs, the power supply circuit of the SoC is typically controlled by the 4G communication module. However, when the 4G communication module experiences an abnormal restart, the power supply to the SoC can be shut off, leading to the loss of critical processed information and severely impacting device reliability and data integrity.

[0003] To address the aforementioned issues, various existing technologies have been attempted, but most suffer from drawbacks such as complex circuitry, high cost, or insufficient reliability. Therefore, there is an urgent need for a simple, low-cost power supply circuit that can effectively prevent the loss of critical information on SOC application chips due to unexpected power outages.

[0004] To solve this problem, this utility model proposes a latch application circuit. Utility Model Content

[0005] This invention aims to solve the problem of data loss caused by unexpected restarts of SOC application chips. It provides a simple latch application circuit with a simple structure and low cost. Moreover, it can provide power to the SOC application chip in a timely manner after the 4G communication module is powered off, based on the power supply status of the 4G communication module, effectively avoiding the loss of important information on the SOC application chip due to unexpected power outages.

[0006] The technical solution adopted by this utility model to solve its technical problem is:

[0007] A latch application circuit includes a 4G communication module, a latch U1, and a SOC application chip. The latch U1 includes a latch enable pin LE, a latch pin D, an output status pin Q, and a power supply VCC.

[0008] The 4G communication module includes a first GPIO port GPIO1 and a second GPIO port GPIO2.

[0009] The latch enable pin LE is connected to the first GPIO port GPIO1 of the 4G communication module.

[0010] The latch pin D is connected to the second GPIO port GPIO2 of the 4G communication module;

[0011] The output status pin Q is used to control the power supply of the SOC application chip.

[0012] As an embodiment of this utility model, the first GPIO port GPIO1 outputs a low level by default, and the second GPIO port GPIO2 outputs a high level by default.

[0013] As an embodiment of this utility model, the latch U1 is further provided with an enable / disable pin OE and a pin GND; the enable / disable pin OE is grounded; and the pin GND is grounded.

[0014] As an embodiment of this utility model, the first end of the latch enable pin LE is connected to the enable disable pin OE, and the second end of the latch enable pin LE is connected to the pin GND.

[0015] As an embodiment of this utility model, the first end of the latching pin D is connected to the pin GND, and the second end of the latching pin D is connected to the first end of the output status pin Q in the latch U1.

[0016] As an embodiment of this utility model, the second end of the output status pin Q in the latch U1 is connected to the first end of the power supply VCC in the latch U1, and the second end of the power supply VCC in the latch U1 is connected to the enable / disable pin OE.

[0017] As an embodiment of this utility model, the output status pin Q is externally coupled to a power switch CTL.

[0018] In one embodiment of this utility model, the power switch CTL is a MOSFET or a transistor.

[0019] In one embodiment of this utility model, the power supply VCC is connected to the SOC application chip.

[0020] The beneficial effects of this utility model are:

[0021] Compared with the prior art, the circuit of this utility model is as follows:

[0022] 1) Simple and easy to implement: It only requires a latch circuit to work with two GPIO ports of the 4G communication module, without the need for complex control logic or additional chips, which reduces the difficulty and cost of circuit design.

[0023] 2) Strong anti-interference capability: By utilizing the state retention characteristic of the latch, the abnormal restart of the 4G communication module is isolated from the power supply of the SOC application chip, ensuring power supply stability.

[0024] 3) High reliability: Effectively avoids power outages in peripherals due to main controller malfunctions, ensuring the integrity of important information and improving the reliability of IoT devices. Attached Figure Description

[0025] Figure 1This is a circuit diagram of an embodiment of the present invention. In the diagram, the latch enable pin (LE, pin 1) of latch U1 is connected to the first GPIO port (GPIO1) of the 4G communication module, the latch pin (D, pin 3) is connected to the second GPIO port (GPIO2), and the output status pin (Q, pin 4) is connected to the power supply control terminal of the SOC application chip - the power switch CTL; the power supply terminal (VCC, pin 5) of the latch is connected to the power supply of the SOC application chip, the ground terminal (GND, pin 2) is grounded, and the enable / disable pin (OE, pin 6) is grounded to ensure that the latch works normally; the GPIO signal lines adopt differential routing to reduce external electromagnetic interference. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] like Figure 1 As shown, an embodiment of this utility model provides a latch application circuit, which includes a 4G communication module, a latch U1 and a SOC application chip. The latch U1 includes a latch enable pin LE, a latch pin D, an output status pin Q, and a power supply VCC.

[0028] The 4G communication module includes a first GPIO port GPIO1 and a second GPIO port GPIO2.

[0029] The latch enable pin LE is connected to the first GPIO port GPIO1 of the 4G communication module.

[0030] The latch pin D is connected to the second GPIO port GPIO2 of the 4G communication module;

[0031] The output status pin Q is used to control the power supply of the SOC application chip.

[0032] The 4G communication module, acting as the main control unit, outputs control signals through the first GPIO port (GPIO1) and the second GPIO port (GPIO2) to initialize and control the state of the latch. When the 4G communication module is powered on and operating normally, the first GPIO port (GPIO1) outputs a low level by default, and the second GPIO port (GPIO2) outputs a high level by default.

[0033] The working principle of the latch application circuit of this utility model is as follows:

[0034] During device startup: After the 4G communication module starts, the first GPIO port GPIO1 outputs a high-level pulse, causing the latch enable pin LE of the latch to be in a high-level state. At this time, the default high-level state of the second GPIO port GPIO2 is transmitted to the output status pin Q through the latch pin D. The output status pin Q outputs a high level, triggering the power supply circuit of the SOC application chip to conduct, thus supplying power to the SOC.

[0035] Latch and hold phase: After the high-level pulse on the latch enable pin LE ends, GPIO1 returns to its default low-level state. At this time, the latch enters the latching state. Regardless of how the level of the latch pin D changes, the output status pin Q always remains at the high level of the previous moment, maintaining the continuous power supply to the SOC.

[0036] Abnormal Restart Handling: When the 4G communication module experiences an abnormal restart, since the first GPIO port GPIO1 and the second GPIO port GPIO2 are in the default low and high level states respectively, the latch enable pin LE remains at a low level, the latch maintains its original latch state, and the latch enters latch mode. However, since the latch has locked the output status pin Q to a high level, it will open the power supply VCC of latch U1 through the control power switch CTL, making it in the working state, keeping the SOC power supply terminal in the conducting state, and the output status pin Q continues to output a high level.

[0037] Therefore, the power supply to the SOC application chip will not be interrupted due to the restart of the 4G module, ensuring that important information is not lost during processing.

[0038] In an embodiment of this utility model, the latch U1 is further provided with an enable / disable pin OE and a ground pin GND; the enable / disable pin OE is grounded; and the ground pin GND is grounded. Introducing a ground terminal can prevent interference from abnormal signals.

[0039] In an embodiment of this utility model, the first end of the latch enable pin LE is connected to the enable disable pin OE, and the second end of the latch enable pin LE is connected to the GND pin; the first end of the latch pin D is connected to the GND pin, and the second end of the latch pin D is connected to the first end of the output status pin Q in the latch U1; the second end of the output status pin Q in the latch U1 is connected to the first end of the power supply VCC in the latch U1, and the second end of the power supply VCC in the latch U1 is connected to the enable disable pin OE. This forms a complete circuit.

[0040] In an embodiment of this utility model, the output status pin Q is externally coupled to a power switch CTL.

[0041] In embodiments of this invention, the power switch CTL is a MOSFET or a transistor. A transistor is preferred.

[0042] In an embodiment of this utility model, the power supply VCC is connected to the SOC application chip.

[0043] by Figure 1 Taking the illustrated embodiment as an example, the working principle of the latch in this embodiment is as follows:

[0044] When the latch enable pin (LE) is high and the latch pin (D) is low, the output status pin (Q) is also low.

[0045] When the latch enable pin (LE) is high and the latch pin (D) is high, the output status pin (Q) is also high.

[0046] When the latch enable pin (LE) is low and the latch pin (D) is low or high, the output status pin (Q) remains unchanged from the previous state, indicating that the previous high or low level is latched.

[0047] When the device is powered on, the GPIO ports of the 4G communication module, which control the latch enable pin (LE) and latch pin (D), output a high level through GPIO1, pulling the latch enable pin high. This high level from GPIO2 is then passed to the latch's output status pin, which is pulled high, supplying power to the SOC application chip. After GPIO0, which controls the latch enable pin (LE), is pulled high and then pulled low, the output pin (Q) remains at the previous high level and is no longer affected by the high or low level of the latch pin (D).

[0048] When the 4G communication module restarts abnormally, because GPIO1 and GPIO2 select the default low and high level IO ports respectively, the latch pin (D) CTL will not be affected by the restart. Therefore, the SOC application chip is powered normally and important information will not be lost.

[0049] Obviously, the above embodiments of this utility model are merely examples for clearly illustrating this utility model, and are not intended to limit the implementation of this utility model. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the protection scope of the claims of this utility model.

Claims

1. A latch application circuit, characterized in that, It includes a 4G communication module, a latch U1 and an SOC application chip. The latch U1 includes a latch enable pin LE, a latch pin D, an output status pin Q, and a power supply VCC. The 4G communication module includes a first GPIO port GPIO1 and a second GPIO port GPIO2. The latch enable pin LE is connected to the first GPIO port GPIO1 of the 4G communication module. The latch pin D is connected to the second GPIO port GPIO2 of the 4G communication module; The output status pin Q is used to control the power supply of the SOC application chip.

2. The latch application circuit according to claim 1, characterized in that, The first GPIO port GPIO1 outputs a low level by default, and the second GPIO port GPIO2 outputs a high level by default.

3. The latch application circuit according to claim 1, characterized in that, The latch U1 is also provided with an enable / disable pin OE and a pin GND; the enable / disable pin OE is grounded; and the pin GND is grounded.

4. The latch application circuit according to claim 3, characterized in that, The first end of the latch enable pin LE is connected to the enable disable pin OE, and the second end of the latch enable pin LE is connected to the GND pin. The first end of the latch pin D is connected to the GND pin, and the second end of the latch pin D is connected to the first end of the output status pin Q in the latch U1. The second terminal of the output status pin Q in latch U1 is connected to the first terminal of the power supply VCC in latch U1, and the second terminal of the power supply VCC in latch U1 is connected to the enable / disable pin OE.

5. The latch application circuit according to any one of claims 1 or 4, characterized in that, The output status pin Q is externally coupled to the power switch CTL.

6. The latch application circuit according to claim 5, characterized in that, The power switch CTL is a MOSFET or a transistor.

7. The latch application circuit according to claim 1, characterized in that, The power supply VCC is connected to the SOC application chip.

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