An auxiliary edge covering device for a silicon wafer

Abstract

The utility model discloses an auxiliary edge covering device of silicon wafer, at least including the conductor with silicon wafer interval distribution and located silicon wafer side, wherein, the positive and negative nature of the charge of conductor and the charge of silicon wafer is opposite, make the conductor to the edge covering paint of the side edge of silicon wafer produce electrostatic attraction, for realizing the auxiliary edge covering effect of silicon wafer, the utility model discloses for improving the protection coating thickness of the position of the adjacent surface intersection of silicon wafer side edge has obvious improvement effect, and single edge covering can obtain enough protection coating thickness, greatly improved the production speed of silicon wafer edge covering, and the static auxiliary edge covering device structure simple, easy to process of the application provides, and the equipment cost investment is less, is suitable for batch production.

Description

Technical Field

[0001] This utility model relates to the field of solar cells, specifically to an auxiliary edge-wrapping device for silicon wafers. Background Technology

[0002] Monocrystalline silicon solar cells account for a large proportion of the current photovoltaic market (approximately over 95%), possessing numerous advantages such as high conversion efficiency, good stability, and low cost. However, because monocrystalline silicon is a brittle material and very fragile, it is typically encapsulated in rigid glass to manufacture photovoltaic modules, lacking the flexibility to bend. With the development of photovoltaic application technologies, more and more scenarios require lightweight and flexible photovoltaic modules, such as rooftops, car roofs, portable power supplies, and wearable electronic devices. Therefore, improving the bendability and flexibility of monocrystalline silicon solar cells has an urgent practical application need.

[0003] Studies have confirmed that the fragility of monocrystalline silicon solar cells is closely related to the edge marks and surface texture left during silicon wafer slicing. The textured surface, created through anisotropic reactions of the monocrystalline silicon wafer in an alkaline solution, is a pyramidal light-trapping structure designed to capture more sunlight. However, these edge marks and pyramidal structures reduce the mechanical strength of the silicon wafer. The valleys of the marks and adjacent pyramids form sharp angles, similar to microscopic "notches" on the wafer. When the wafer is subjected to bending, vibration, or thermal shock (drastic temperature changes), stress concentration occurs at these notches, making the wafer prone to breakage. Silicon wafer breakage can occur during the production of solar cells, modules, and the use of photovoltaic products.

[0004] Furthermore, for example, the invention patent application with application number CN202211090758X discloses a method and structure for smoothing the edges of silicon wafers, making the silicon wafers flexible; another example is the invention patent application with application number CN2023101757573, which discloses a method for edge processing using plasma etching; yet another example is the invention patent application with application number CN2023101363247, which discloses a single-crystal textured silicon wafer with polished edges and a preparation method, which prepares a smooth surface without pyramid structures in the area of ​​the silicon wafer edge width of 0.1~5mm, which can effectively reduce the stress concentration generated at the pyramid angles and improve the bendability and flexibility of the silicon wafer.

[0005] During the implementation of the application, the applicant discovered that when silicon wafers are made into solar cells, they need to undergo a series of solar cell manufacturing processes, during which the bendability of the silicon wafers gradually decreases, seriously affecting the production qualification rate of flexible solar cells. To address this, the applicant proposed a scheme in prior application 202510122724.1 to edge-wrap the silicon wafers (i.e., "covering the sides of the silicon wafers with a protective coating") to prevent the edges of the silicon wafers from being chemically corroded and mechanically damaged, thus maintaining the original bendability of the silicon wafers during the solar cell manufacturing process.

[0006] During the edge-wrapping process of the silicon wafer, the applicant further discovered that: because the adjacent faces of the silicon wafer edge are perpendicular to each other, the edge-wrapping coating has a certain fluidity before curing. Under the action of surface tension, the protective coating thickness at the intersection of adjacent faces (also known as the "edge position") is very thin, and the edge of silicon wafer 1' may even be completely exposed and cannot be effectively covered by the edge-wrapping coating 3' (see [link to relevant documentation]). Figure 1 and Figure 7 As shown, the outline of the protective coating 4' is arc-shaped, but the thickness of the protective coating 4' at the intersection of adjacent surfaces of the silicon wafer 1' approaches zero, thus failing to provide effective edge protection for the silicon wafer 1' and making it difficult to achieve the expected edge protection effect. To increase the thickness of the protective coating at the intersection of adjacent surfaces, multiple applications and curing of the edge coating are required, which greatly affects the production speed of the production line.

[0007] Therefore, the applicant hopes to find a technical solution to address the above technical problems. Summary of the Invention

[0008] In view of this, the purpose of this utility model is to provide an auxiliary edge-wrapping device for silicon wafers, which has a significant effect on improving the thickness of the protective coating at the intersection of adjacent surfaces on the side of the silicon wafer. Sufficient protective coating thickness can be obtained in a single edge-wrapping operation, which greatly improves the production speed of silicon wafer edge-wrapping. Moreover, the static auxiliary edge-wrapping device provided in this application has a simple structure, is easy to process, has a low equipment cost, and is suitable for mass production.

[0009] The technical solution adopted in this utility model is as follows:

[0010] An auxiliary edge-wrapping device for a silicon wafer includes at least conductors spaced apart from and located on the side of the silicon wafer; wherein the conductors carry charges that are opposite in nature to the charges on the silicon wafer, causing the conductors to generate an electrostatic attraction to an edge-wrapping coating located on the side of the silicon wafer, thereby achieving an auxiliary edge-wrapping effect on the silicon wafer.

[0011] Preferably, the coverage width of the edge coating on the front edge or the back edge of the silicon wafer ranges from 0.1 to 5 mm.

[0012] Preferably, the conductor is electrically connected to one electrode of the electrostatic generator via a conductor wire; and the silicon wafer is electrically connected to the other electrode of the electrostatic generator; the voltage range applied by the electrostatic generator is preferably 1-50kV.

[0013] Preferably, the silicon wafer is placed on a conductive base and electrically connected to another electrode of the electrostatic generator through the conductive base.

[0014] Preferably, the conductor is in a closed shape, located on the outer periphery of the silicon wafer, and its perimeter is greater than the perimeter of the silicon wafer.

[0015] Preferably, the surface of the conductor is covered with a conductor insulation layer to prevent the generation of an electric arc after the air is broken down by the electrostatic field; wherein preferably, the diameter of the conductor is in the range of 1-5mm, and the thickness of the conductor insulation layer is in the range of 0.1-3mm.

[0016] Preferably, the conductor includes at least a first conductor unit and a second conductor unit that are spaced vertically relative to the silicon wafer and located on the side of the silicon wafer; wherein the charge carried by the first conductor unit and the charge carried by the second conductor unit are of the same positive and negative nature, and are opposite to the positive and negative nature of the charge carried by the silicon wafer, so that the first conductor unit and the second conductor unit simultaneously generate electrostatic attraction to the edge coating located on the side of the silicon wafer, thereby achieving an auxiliary edge coating effect on the silicon wafer.

[0017] Preferably, an integrated auxiliary packaging structure is adopted; wherein, the integrated auxiliary packaging structure includes at least: a first conductor unit, a first silicon wafer, a second conductor unit, a second silicon wafer, and a third conductor unit arranged coaxially and spaced vertically; wherein,

[0018] Each conductor unit is located on the side of its corresponding silicon wafer;

[0019] The positive and negative properties of the charges carried by the first conductor unit, the second conductor unit, and the third conductor unit are all the same, and are opposite to the positive and negative properties of the charges carried by the first silicon wafer and the second silicon wafer.

[0020] This causes the first conductor unit and the second conductor unit to simultaneously generate electrostatic attraction to the edge coating located on the side of the first silicon wafer, thereby achieving an auxiliary edge coating effect on the first silicon wafer.

[0021] This causes the second and third conductor units to simultaneously generate electrostatic attraction to the edge coating located on the side of the second silicon wafer, thereby achieving an auxiliary edge coating effect on the second silicon wafer.

[0022] Preferably, the conductor units are arranged at equal intervals in the vertical direction; preferably, the shape of each conductor unit corresponds to the shape of the four sides of the silicon wafer; wherein, the two conductor units located above and below the silicon wafer are symmetrically distributed with respect to the silicon wafer; the spacing between adjacent conductor units is 10-100mm.

[0023] Preferably, each conductor unit is electrically connected to one electrode of the electrostatic generator via a conductor wire, and the silicon wafer is placed on a conductive base and electrically connected to the other electrode of the electrostatic generator via the conductive base.

[0024] This utility model specifically proposes an auxiliary edge-wrapping device for use in edge-wrapping silicon wafers. By setting a conductor structure with opposite positive and negative charges to the silicon wafer, the conductor generates an electrostatic attraction to the edge-wrapping coating located on the side of the silicon wafer during edge-wrapping. This significantly improves the protective coating thickness at the intersection of adjacent surfaces on the side of the silicon wafer. Sufficient protective coating thickness can be obtained in a single edge-wrapping operation, greatly increasing the production speed of silicon wafer edge-wrapping. Moreover, the electrostatic auxiliary edge-wrapping device provided by this application has a simple structure, is easy to process, and has a low equipment cost, making it suitable for mass production. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of the silicon wafer edge obtained by the conventional edge-wrapping process described in the background art;

[0026] Figure 2a This is a schematic diagram illustrating the working principle of the auxiliary edge-wrapping device used in a specific embodiment of this application (single conductor, actual implementation effect is worse than...). Figure 2b (The implementation effect shown)

[0027] Figure 2b This is a schematic diagram of the working principle of auxiliary edge wrapping using an auxiliary edge wrapping device in a specific embodiment of this application (using two conductor units).

[0028] Figure 3 This is a schematic diagram of the working state of the integrated auxiliary packaging structure for auxiliary edge wrapping under the specific implementation of this application;

[0029] Figure 4 yes Figure 3 A schematic diagram of the side structure;

[0030] Figure 5 yes Figure 3 A schematic diagram of the structure viewed from below;

[0031] Figure 6 This is a laser micrograph of the silicon wafer edge section obtained by using an auxiliary edge-wrapping device in Embodiment 1 of this application (the right image is an enlarged view of the area in the box in the left image).

[0032] Figure 7 This is a laser micrograph of the edge section of a silicon wafer obtained in Comparative Example 1 of this application without the use of an auxiliary edge-wrapping device (the right image is an enlarged view of the area in the box in the left image). Detailed Implementation

[0033] Please see Figure 2a As shown, this embodiment proposes an auxiliary edge-wrapping device for silicon wafers, which includes at least conductors 2 spaced apart from the silicon wafer 1 and located on the side of the silicon wafer. The conductors 2 carry charges with opposite polarities to those on the silicon wafer 1, causing them to electrostatically attract the edge-wrapping coating 3 located on the side of the silicon wafer. This achieves the auxiliary edge-wrapping effect on the silicon wafer. The edge-wrapping coating is then heated and cured to obtain a protective coating. This embodiment significantly improves the thickness of the protective coating at the intersection of adjacent surfaces on the side of the silicon wafer 1, achieving sufficient protective coating thickness in a single edge-wrapping operation, greatly increasing the production speed of silicon wafer edge-wrapping. Preferably, in this embodiment, the coverage width of the edge-wrapping coating 3 on the front edge or back edge of the silicon wafer 1 ranges from 0.1 to 5 mm.

[0034] It should be noted that the silicon wafer edge-wrapping process used in the embodiments of this application can be directly referred to the relevant scheme described in the prior published patent application: 202510122724.1. In order to save space, this application will not elaborate on it further.

[0035] Preferably, to further facilitate the simultaneous application of electrostatic assisted edge-wrapping to both the front and back edges of the silicon wafer, please refer to [reference needed]. Figure 2b , Figure 3 , Figure 4 and Figure 5 As shown, in this embodiment, the conductor includes at least a first conductor unit 2a and a second conductor unit 2b that are spaced vertically relative to the silicon wafer 1 and located on the side of the silicon wafer; wherein, the charge carried by the first conductor unit 2a and the charge carried by the second conductor unit 2b are of the same positive and negative nature, and are opposite to the positive and negative nature of the charge carried by the silicon wafer 1, so that the first conductor unit 2a and the second conductor unit 2b simultaneously generate electrostatic attraction to the edge coating 3 located on the side of the silicon wafer 1, thereby achieving an auxiliary edge coating effect on the silicon wafer 1;

[0036] Specifically, after applying an edge-sealing coating to the side of silicon wafer 1, one conductor 2 or two conductor units 2a and 2b are placed at a certain distance from the edge of silicon wafer 1. These units are located on one side or the top and bottom sides of the silicon wafer's extended surface (i.e., the outer perimeter of the silicon wafer). Their relative positions to silicon wafer 1 are shown in the respective references. Figure 2a and Figure 2bAs shown; a high voltage is applied between the silicon wafer 1 and the conductor 2 or conductor units 2a, 2b, so that the edge coating 3, conductor 2 or conductor units 2a, 2b carry opposite charges. That is, the charge on the edge coating 3 can be positive or negative, and the charge on conductor 2 or conductor units 2a, 2b is opposite in nature to the charge on the edge coating 3. During auxiliary edge coating, the charged edge coating 3 moves towards the front edge and / or back edge of the silicon wafer 1 under the action of electrostatic attraction, thereby increasing the thickness of the edge coating at the edge of the silicon wafer 1.

[0037] More preferably, to improve the efficiency of the auxiliary edging, please also refer to... Figure 3 , Figure 4 and Figure 5 As shown, in this embodiment, an integrated auxiliary packaging structure is adopted; wherein, the integrated auxiliary packaging structure includes at least: a first conductor unit 2a, a first silicon wafer 1a, a second conductor unit 2b, a second silicon wafer 1b, and a third conductor unit 2c arranged vertically and coaxially; wherein, each conductor unit 2a, 2b, 2c is located on the side of its corresponding silicon wafer 1a, 1b; the positive and negative properties of the charges carried by the first conductor unit 2a, the second conductor unit 2b, and the third conductor unit 2c are the same, and opposite to the positive and negative properties of the charges carried by the first silicon wafer 1a and the second silicon wafer 1b; such that the first conductor unit 2a and the second conductor unit 1b simultaneously generate electrostatic attraction to the edge coating 3 located on the side of the first silicon wafer 1a, thereby achieving an auxiliary edge coating effect for the first silicon wafer 1a; simultaneously, the second conductor unit 2b and the third conductor unit 2c simultaneously generate electrostatic attraction to the edge coating 3 located on the side of the second silicon wafer 1b, thereby achieving an auxiliary edge coating effect for the second silicon wafer 1b.

[0038] Preferably, in this embodiment, the conductor units 2a, 2b, and 2c are arranged at equal intervals in the vertical direction; preferably, the shapes of the conductor units 2a, 2b, and 2c correspond to the shapes of the four sides of the silicon wafers 1a and 1b; wherein, the two conductor units located above and below the silicon wafers 1a and 1b are symmetrically distributed vertically relative to the silicon wafers; the spacing between adjacent conductor units is 10-100 mm.

[0039] Preferably, in this embodiment, each conductor unit is electrically connected to one electrode (which can be either the negative or positive electrode) of the electrostatic generator via a conductor wire 5, and each silicon wafer 1a, 1b is placed on its corresponding conductive base 6, and is electrically connected to the other electrode (which can be either the positive or negative electrode) of the electrostatic generator via the conductive base 6. The conductive base 6 is electrically connected to the other electrode of the electrostatic generator via a wire 7. More preferably, in this embodiment, the voltage range applied by the electrostatic generator is preferably 1-50kV.

[0040] It should be noted that the conductive base 6 involved in this application is in a fixed installation state, and the specific installation structure adopted is a conventional technical means for those skilled in the art. This embodiment will not elaborate on or limit it.

[0041] Preferably, in order to obtain a stable and reliable edge-wrapping electrostatic auxiliary effect, in this embodiment, each conductor unit 2a, 2b, 2c is in a closed shape (specifically, in this embodiment, it is set as a conductive closed loop structure), located on the outer periphery of silicon wafers 1a, 1b, and its perimeter is greater than that of silicon wafers 1a, 1b; more specifically, in this embodiment, silicon wafers 1a, 1b are rectangular (in other embodiments, they can also be square, circular, or other shapes), and each conductor unit 2a, 2b, 2c is also correspondingly rectangular, and its length is 10-100mm longer than that of silicon wafers 1a, 1b, and its width is 10-100mm wider than that of silicon wafers 1a, 1b;

[0042] Preferably, in this embodiment, the surface of each conductor unit 2a, 2b, 2c is covered with a conductor insulation layer 21 to prevent the air from being broken down by the electrostatic field and generating an electric arc; wherein preferably, the diameter of each conductor unit 2a, 2b, 2c is in the range of 1-5mm, and the thickness of the corresponding conductor insulation layer 21 is in the range of 0.1-3mm.

[0043] In this embodiment, each silicon wafer 1a, 1b with the edge coating 3 applied to its side is placed sequentially on its corresponding conductive base 6, so that the center of each silicon wafer 1a, 1b is aligned with the center of each conductor unit 2a, 2b, 2c, and the four edges of each silicon wafer 1a, 1b are parallel to the four edges of its corresponding conductor unit 2a, 2b, 2c. A voltage of appropriate value (preferably 1-50kV) is applied between each conductor unit 2a, 2b, 2c and its corresponding conductive base 6, and each silicon wafer 1a, 1b is heated to cure the edge coating 3 and form a protective coating 4 for achieving the edge coating effect. Then, the cured silicon wafers are removed sequentially, and the next batch of silicon wafers to be cured is placed accordingly.

[0044] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0045] To further illustrate the implementation process and effects of this application, based on the above implementation scheme, this application further proposes the following embodiments:

[0046] Example 1: Refer to Figure 3 , Figure 4 and Figure 5 The integrated auxiliary packaging structure shown features 51 conductor units (specifically, rectangular conductive ring structures) arranged coaxially with equal vertical spacing. Each conductor unit is a rectangle formed by bending a 3mm diameter stainless steel rod. The rectangle has an internal length of 230mm and a width of 125mm. A 3mm inner diameter PFA tube (as a conductor insulation layer) is fitted over the stainless steel rod. The PFA tube has a wall thickness of 1mm. PFA stands for Perfluoroalkoxy, a perfluorinated thermoplastic polymer. Adjacent conductors... The spacing between the units is 20mm. The plane of each conductor unit is parallel to the horizontal plane and is electrically connected to the negative terminal of the electrostatic generator through conductor wires. A stainless steel conductive base is placed between every two adjacent conductive units, for a total of 50 units. The upper surface of each stainless steel conductive base is located at the center between the upper and lower conductive units. Each stainless steel conductive base is connected to the positive terminal of the electrostatic generator by a wire. A hot air blower is placed around the auxiliary edging device (i.e., conductor unit) to dry the edging coating. There is an exhaust device on the top to remove the organic matter volatilized from the edging coating.

[0047] The edge-sealing coating used in this embodiment 1 is a PTFE coating with a viscosity of 2000cp. After applying the edge-sealing coating to the side of the silicon wafer (size specification is 210×105mm) on the edge-sealing machine, it is placed on its corresponding stainless steel conductive base. The voltage of the electrostatic generator is set to 8kV and the hot air temperature is set to 150℃. The edge-sealed silicon wafers are placed from top to bottom. Then, the silicon wafers that have been dried for 2 minutes are taken out one by one and the subsequent known process steps are carried out.

[0048] Because the edge coating is fluid before drying, it moves towards the front and back edges of the silicon wafer under the electrostatic attraction provided by the auxiliary edge coating device, increasing the thickness of the edge coating at the edge of the silicon wafer. After drying and curing, it still maintains the morphology under the electrostatic attraction.

[0049] Comparative Example 1: The remaining technical solutions of Comparative Example 1 are the same as those of Example 1, except that in this Comparative Example 1, there is no electrostatic generator for activating the auxiliary edge-wrapping device, that is, the electrostatic generator does not apply voltage between the silicon wafer and each conductor unit.

[0050] Please see Figure 6 and Figure 7 As shown, compared to Comparative Example 1 without electrostatic edge coating assistance, the edge coating thickness at the silicon wafer edge position in Example 1 is close to 0 μm (in Comparative Example 1). Figure 7 The value was increased to 10-15 μm (as shown). Figure 6 As shown in the figure, it can effectively protect the sides of the silicon wafer.

[0051] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0052] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An auxiliary edge-wrapping device for silicon wafers, characterized in that, The device includes at least conductors spaced apart from and located on the sides of the silicon wafer; wherein the conductors include at least a first conductor unit and a second conductor unit spaced vertically relative to the silicon wafer and located on the sides of the silicon wafer; wherein the charge carried by the first conductor unit and the second conductor unit has the same positive and negative nature, and the positive and negative nature is opposite to that of the charge carried by the silicon wafer, so that the first conductor unit and the second conductor unit simultaneously generate electrostatic attraction to the edge coating located on the sides of the silicon wafer, thereby achieving an auxiliary edge coating effect on the silicon wafer; the shape of each conductor unit corresponds to the shape of the four sides of the silicon wafer; wherein the two conductor units located above and below the silicon wafer are symmetrically distributed vertically relative to the silicon wafer.

2. The auxiliary edge-wrapping device for silicon wafers according to claim 1, characterized in that, The coverage width of the edge coating on the front edge or the back edge of the silicon wafer ranges from 0.1 to 5 mm.

3. The auxiliary edge-wrapping device for silicon wafers according to claim 1, characterized in that, The conductor is electrically connected to one electrode of the electrostatic generator via a conductor wire; and the silicon wafer is electrically connected to the other electrode of the electrostatic generator.

4. The auxiliary edge-wrapping device for silicon wafers according to claim 3, characterized in that, The electrostatic generator applies a voltage range of 1-50kV.

5. The auxiliary edge-wrapping device for silicon wafers according to claim 3, characterized in that, The silicon wafer is placed on a conductive base and electrically connected to another electrode of the electrostatic generator through the conductive base.

6. The auxiliary edge-wrapping device for silicon wafers according to claim 1, characterized in that, The conductor is in a closed shape, located on the outer periphery of the silicon wafer, and its perimeter is greater than that of the silicon wafer.

7. The auxiliary edge-wrapping device for silicon wafers according to claim 1 or 6, characterized in that, The surface of the conductor is covered with a conductor insulation layer to prevent the air from being broken down by the electrostatic field and generating an electric arc.

8. The auxiliary edge-wrapping device for silicon wafers according to claim 7, characterized in that, The diameter of the conductor ranges from 1 to 5 mm, and the thickness of the conductor insulation layer ranges from 0.1 to 3 mm.

9. The auxiliary edge-wrapping device for silicon wafers according to claim 1, characterized in that, An integrated auxiliary packaging structure is adopted; wherein, the integrated auxiliary packaging structure includes at least: a first conductor unit, a first silicon wafer, a second conductor unit, a second silicon wafer, and a third conductor unit arranged coaxially and spaced vertically; wherein, Each conductor unit is located on the side of its corresponding silicon wafer; The positive and negative properties of the charges carried by the first conductor unit, the second conductor unit, and the third conductor unit are all the same, and are opposite to the positive and negative properties of the charges carried by the first silicon wafer and the second silicon wafer. This causes the first conductor unit and the second conductor unit to simultaneously generate electrostatic attraction to the edge coating located on the side of the first silicon wafer, thereby achieving an auxiliary edge coating effect on the first silicon wafer. This causes the second and third conductor units to simultaneously generate electrostatic attraction to the edge coating located on the side of the second silicon wafer, thereby achieving an auxiliary edge coating effect on the second silicon wafer.

10. The auxiliary edge-wrapping device for a silicon wafer according to claim 1 or 9, characterized in that, Each conductor unit is arranged at equal intervals in the vertical direction; the spacing between adjacent conductor units is 10-100mm.

11. The auxiliary edge-wrapping device for silicon wafers according to claim 1 or 9, characterized in that, Each conductor unit is electrically connected to one electrode of the electrostatic generator via a conductor wire, and the silicon wafer is placed on a conductive base and electrically connected to the other electrode of the electrostatic generator via the conductive base.

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