A trench capacitor cell and capacitor chip
By employing a multi-layer stacked structure and an optimized trench capacitor cell design with interconnected contacts and metal elements, the problem of high parasitic inductance in traditional ceramic capacitors has been solved. This results in a high-density capacitor chip with low equivalent series inductance, suitable for capacitors of various package sizes.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 芯铭半导体(杭州)有限公司
- Filing Date
- 2024-06-06
- Publication Date
- 2026-05-29
AI Technical Summary
The lead length of traditional ceramic capacitors cannot be shortened, resulting in large parasitic inductance, which limits the miniaturization of terminal modules and products, and the capacitance density of silicon-based capacitors needs to be improved.
The trench capacitor cell, which adopts a multi-layer stacked structure, forms a high-density capacitor chip with low equivalent series inductance by using a 2x2 trench array and alternating plates, combined with optimized plates, contact vias and metal interconnect structures.
It improves capacitance density, reduces equivalent series inductance, and is suitable for capacitor chips of different package sizes, enabling high-performance, miniaturized, and ultra-thin capacitor designs.
Smart Images
Figure CN224306235U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to capacitors, specifically to a trench capacitor unit and capacitor chip. Background Technology
[0002] Driven by new technologies such as 5G, AI, and metaverse, terminal products are gradually evolving towards higher technological paths, exhibiting technological trends such as cross-terminal functional integration and end-to-end co-creation. This trend has propelled current products into an era of integration and miniaturization, placing numerous demands on various functional modules and electronic components, including high performance, miniaturization, ultra-thinness, low power consumption, and low cost.
[0003] Capacitors are indispensable electronic components in integrated circuits, used for storing charge and energy, filtering, and matching signals. Traditional ceramic capacitors are typically mounted on printed circuit boards (PCBs), and their parasitic inductance is relatively high due to the unshortenable lead length. The large number of mounted capacitors occupies the surface area of the PCB, limiting the miniaturization of terminal modules and even products.
[0004] Silicon-based capacitors, manufactured using semiconductor processes, offer advantages such as high performance, low equivalent series resistance (ERS), low ERS inductance, ultra-thin profile, and flexible packaging, addressing the technical limitations of traditional ceramic capacitors. To further miniaturize silicon-based capacitors, increasing their capacitance density is crucial. Utility Model Content
[0005] To improve capacitance density and reduce equivalent series inductance, this invention proposes a trench capacitor unit and capacitor chip.
[0006] A trench capacitor cell includes:
[0007] substrate;
[0008] A 2x2 trench array group is placed on the substrate and contains several trenches of equal number, length, width and spacing, which extend alternately in the horizontal and vertical directions with the center of the capacitor unit as the axis.
[0009] The first, second, third, and fourth plates have 1x1, 1x2, 2x2, and 2x2 arrays, respectively. Each first, second, third, and fourth plate sequentially surrounds two second plates, two third plates, a single fourth plate, and a single trench array group. The first plate is placed on the bottom of the trench, the sidewalls, and the surface of the substrate. The second, third, and fourth plates are sequentially placed above the first, second, and third plates. The first, second, third, and fourth plates are sequentially isolated by the first, second, and third dielectric layers to form a multilayer stacked capacitor.
[0010] The first, second, third, and fourth electrode plates have contact through holes. The first electrode plate contact through holes are arranged in an "H" shape and are located in the non-overlapping area of the first and second electrode plates. The second electrode plate contact through holes are arranged in a "T" shape and are located in the non-overlapping area of the second and third electrode plates. The third electrode plate contact through holes are arranged in an "L" shape and are located in the non-overlapping area of the third and fourth electrode plates. The fourth electrode plate contact through hole is located in the fourth electrode plate area above the trench interval area.
[0011] The metal interconnect layer includes a first metal layer, a second metal layer and a first via layer therebetween, forming a first capacitor port that connects to the contact vias of the first and third plates and a second capacitor port that connects to the contact vias of the second and fourth plates.
[0012] The method for forming the above-mentioned trench capacitor includes:
[0013] A trench array is formed on a semiconductor substrate; a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, a third dielectric layer, and a fourth electrode are sequentially deposited on the bottom, sidewalls, and surface of the semiconductor substrate; the electrode and dielectric layer are patterned to form a conductive contact area; a first port and a second port of a capacitor are formed by contact vias, a first metal layer, a first via, a second metal layer, and a pad.
[0014] A capacitor chip, comprising the aforementioned trench capacitor unit;
[0015] If the openings of the capacitor chip are located on the left and right sides of the chip, the capacitor unit does not rotate, the second metal layer and the via extend laterally, and the via and the pad are placed on the left and right sides of the chip. If the openings of the capacitor chip are located on the top and bottom sides of the chip, the capacitor unit rotates 90° clockwise or counterclockwise around the center of the capacitor unit, the second metal layer and the via extend vertically, and the via and the pad are placed on the top and bottom sides of the chip.
[0016] This invention effectively improves capacitance density through a multi-layer stacked structure. In addition, the optimized arrangement of electrode plates, contact vias, and metal interconnect structures can form a capacitor chip with high density and low equivalent series inductance. The capacitor chip can be applied to different package sizes. Attached Figure Description
[0017] The accompanying drawings show only preferred embodiments. Various features in the drawings are not drawn to scale, and the dimensions of each feature can be arbitrarily changed. These are not considered as limitations on this utility model.
[0018] Figure 1 This is a schematic diagram of the trench, electrode plate, and contact via of a multilayer stacked trench capacitor cell according to an embodiment of this application.
[0019] Figure 2 This is a schematic diagram of the metal interconnection of a multilayer stacked trench capacitor cell according to an embodiment of this application.
[0020] Figure 3 This is a cross-sectional structural diagram of a multilayer stacked trench capacitor according to an embodiment of this application.
[0021] Figure 4 This is a capacitor chip composed of a trench capacitor unit array according to an embodiment of this application.
[0022] Figure 5 This is another embodiment of the present application of a capacitor chip composed of a trench capacitor unit array. Detailed Implementation
[0023] To make the content and technical advantages of this utility model clearer and easier to understand, the content of this utility model will be described more clearly and completely below with reference to the accompanying drawings of the embodiments. It should be understood that this utility model is not limited to some specific embodiments; that is, the specific embodiments described are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, general substitutions well known to those skilled in the art are also included within the protection scope of this utility model.
[0024] To improve capacitor density, this invention provides a multi-layer stacked trench capacitor unit.
[0025] The trench capacitor unit has the following characteristics:
[0026] like Figure 1 and Figure 2 As shown, a 2x2 trench array group 100 is placed on a semiconductor substrate and contains several trenches of equal number, length, width and spacing, which extend alternately in the horizontal and vertical directions with the center of the capacitor unit as the axis.
[0027] The device comprises a first electrode 101, a second electrode 102, a third electrode 103, and a fourth electrode 104. Based on a two-dimensional projection pattern angle, the first electrode 101 has a 1x1 array, the second electrode 102 has a 1x2 array, the third electrode 103 has a 2x2 array, and the fourth electrode 104 has a 2x2 array. A single first electrode 101 surrounds two second electrode 102s, a single second electrode 102 surrounds two third electrode 103s, a single third electrode 103 surrounds a single fourth electrode 104, and a single fourth electrode 104 surrounds a single trench array group 100. Based on a three-dimensional structural angle (… Figure 3The first electrode 101 is placed on the bottom of the trench, the sidewalls, and the surface of the substrate. The second electrode 102 is placed on the first electrode 101. The third electrode 103 is placed on the second electrode 102. The fourth electrode 104 is placed on the third electrode 103. The first electrode 101 and the second electrode 102 are isolated by a first dielectric layer 105. The second electrode 102 and the third electrode 103 are isolated by a second dielectric layer 106. The third electrode 103 and the fourth electrode 104 are isolated by a third dielectric layer 107, forming a multilayer stacked capacitor.
[0028] It has a first electrode contact through hole 108, a second electrode contact through hole 109, a third electrode contact through hole 110, and a fourth electrode contact through hole 111. The first electrode contact through holes 108 are arranged in an "H" shape and are located in the non-overlapping area of the first electrode 101 and the second electrode 102. The second electrode contact through holes 109 are arranged in a "T" shape and are located in the non-overlapping area of the second electrode 102 and the third electrode 103. The third electrode contact through holes 110 are arranged in an "L" shape and are located in the non-overlapping area of the third electrode 103 and the fourth electrode 104. The fourth electrode contact through hole 111 is located on the fourth electrode 104 above the groove spacing area.
[0029] The capacitor has a first metal layer 112, including a first metal layer 112a leading to a first port of the capacitor and a first metal layer 112b leading to a second port of the capacitor. The first metal layer 112a is connected to the first electrode contact through-hole 108 and the third electrode contact through-hole 110, and the first metal layer 112b is connected to the second electrode contact through-hole 109 and the fourth electrode contact through-hole 111. It also has a first through-hole 113, including a first through-hole 113a leading to a first port of the capacitor and a first through-hole 113b leading to a second port of the capacitor. The first through-hole 113a is connected to the first metal layer 112a, and the first through-hole 113b is connected to the first metal layer 112b. Finally, it has a second metal layer 114, including a second metal layer 114a leading to a first port of the capacitor and a second metal layer 114b leading to a second port of the capacitor. The second metal layer 114a is connected to the first through-hole 113a, and the second metal layer 114b is connected to the first through-hole 113b.
[0030] Figure 3 A cross-sectional structural diagram of the trench capacitor of this invention is shown. To further detail the manufacturing method of this invention, the manufacturing steps will be described in detail below with reference to the schematic diagram:
[0031] In some embodiments, a semiconductor substrate 115 is provided, which is, for example, a semiconductor-related material such as silicon, germanium, or silicon carbide. In this embodiment, preferably, the semiconductor substrate 115 is a silicon substrate. A thin insulating layer (not shown) is deposited on the semiconductor substrate 115. The thin insulating layer is, for example, a material such as an oxide or nitride. The thin insulating layer is formed by methods such as thermal oxidation or chemical vapor deposition. The thickness of the thin insulating layer is between 5 and 20 nm.
[0032] In some embodiments, a photoresist layer is formed on the thin oxide layer, the thickness of the photoresist layer being between 4-6 μm.
[0033] In other embodiments, before forming the photoresist layer, a hard mask layer is deposited on top of the thin insulating layer. The hard mask layer is, for example, an oxide or nitride material. The hard mask layer is formed by a method such as chemical vapor deposition. The thickness of the hard mask layer is between 200-600 nm. Then, a photoresist layer is formed on the hard mask layer.
[0034] Further, photolithography and etching processes are performed to form high aspect ratio concave trenches on the semiconductor substrate 115. The etching process is, for example, a wet process or a dry process. In this embodiment, preferably, the etching process is a BOSCH etching process. The BOSCH etching process achieves etching and sidewall passivation by alternately switching etching gas and passivation gas, wherein the etching gas is SF6 and the passivation gas is C4F8. Through periodic "etch-passivation-etch", deep trench etching is achieved, with a trench aspect ratio as high as 50:1. Next, a wet etching process is performed to remove residual photoresist, hard mask layer, and thin insulating layer.
[0035] In some embodiments, an insulating layer 116 is deposited on the bottom of the trench, the sidewalls, and the surface of the semiconductor substrate 115. The insulating layer 116 is, for example, an oxide, a nitride, or other material. The insulating layer 116 is formed by, for example, chemical vapor deposition, atomic layer deposition, or other methods. The thickness of the insulating layer 116 is between 10-30 nm. The insulating layer 116 is used to achieve electrical isolation between the capacitor and the semiconductor substrate.
[0036] In some embodiments, the first electrode 101, the first dielectric layer 105, the second electrode 102, the second dielectric layer 106, the third electrode 103, the third dielectric layer 107, and the fourth electrode 104 are deposited sequentially. The materials of the first electrode 101, the second electrode 102, the third electrode 103, and the fourth electrode 104 are, for example, doped polycrystalline silicon, metal, or metal nitride, and the methods for forming the first electrode 101, the second electrode 102, the third electrode 103, and the fourth electrode 104 are, for example, chemical vapor deposition, physical vapor deposition, etc.
[0037] In this embodiment, preferably, the first electrode 101, the second electrode 102, the third electrode 103, and the fourth electrode 104 are doped polycrystalline silicon, formed by low-pressure chemical vapor deposition, specifically by deposition of silane and phosphine at 560-620 degrees Celsius, followed by rapid high-temperature annealing. The thickness of the first electrode 101, the second electrode 102, the third electrode 103, and the fourth electrode 104 is all between 50-300 nm.
[0038] In some embodiments, the materials of the first dielectric layer 105, the second dielectric layer 106, and the third dielectric layer 107 are, for example, oxides, nitrides, or oxynitrides, such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, lanthanum oxide, or zirconium oxide. The methods for forming the first dielectric layer 105, the second dielectric layer 106, and the third dielectric layer 107 are, for example, chemical vapor deposition, atomic layer deposition, etc. The structures of the first dielectric layer 105, the second dielectric layer 106, and the third dielectric layer 107 are, for example, a single-layer structure composed of a single dielectric material, or a multilayer stacked structure or composite structure composed of multiple dielectric materials.
[0039] In this embodiment, preferably, the first dielectric layer 105, the second dielectric layer 106 and the third dielectric layer 107 are multilayer stacked structures or composite structures composed of multiple dielectric materials deposited by atomic layer deposition, and the thicknesses of the first dielectric layer 105, the second dielectric layer 106 and the third dielectric layer 107 are all between 5-30 nm.
[0040] In some embodiments, photolithography and etching processes are performed to pattern the first electrode 101, the first dielectric layer 105, the second electrode 102, the second dielectric layer 106, the third electrode 103, the third dielectric layer 107, and the fourth electrode 104. Preferably, the patterning sequence is as follows: first, patterning of the fourth electrode 104 and the third dielectric layer 107; second, patterning of the third electrode 103 and the second dielectric layer 106; third, patterning of the second electrode 102 and the first dielectric layer 105; fourth, patterning of the first electrode 101, wherein the etching process is a reactive ion etching process.
[0041] In some embodiments, an isolation sidewall 117 is formed on the sidewalls of the first electrode 101, the second electrode 102, the third electrode 103, and the fourth electrode 104. Specifically, a double-layer or triple-layer thin film, such as a combination of oxides and nitrides, or a combination of oxides, nitrides, and oxides, is deposited. The formation method is, for example, chemical vapor deposition. Then, an anisotropic dry etching process is performed to form the isolation sidewall 117.
[0042] In some embodiments, a dielectric layer (not shown) is deposited, such as an oxide or nitride, and the dielectric layer is formed by a method such as chemical vapor deposition. Then, photolithography and etching processes are performed to expose the electrode contact area. Next, a metal layer and a titanium nitride layer (not shown) are deposited, such as a conductive material like cobalt, titanium, or nickel, and the metal layer and titanium nitride layer are formed by a method such as physical vapor deposition. Then, one or more rapid thermal annealing processes are performed to form a low-resistivity metal silicide 118.
[0043] In some embodiments, an interlayer dielectric layer 119 is deposited, which is, for example, a material such as tetraethyl orthosilicate, fluorine or carbon-doped silicon oxide, and the interlayer dielectric layer 119 is formed by, for example, sub-atmospheric pressure chemical vapor deposition, and the thickness of the interlayer dielectric layer 119 is between 1 and 1.5 μm.
[0044] In other embodiments, an etch barrier layer is deposited before depositing the interlayer dielectric layer 119. The etch barrier layer is, for example, a material such as silicon nitride, and the etch barrier layer is formed by, for example, plasma-enhanced chemical vapor deposition. The thickness of the etch barrier layer is between 40-100 nm.
[0045] Further, a chemical mechanical planarization process is performed to planarize the interlayer dielectric layer 119. After the chemical mechanical planarization process, the thickness of the interlayer dielectric layer 119 is between 0.8 and 1.2 μm.
[0046] In some embodiments, photolithography and etching processes are performed to form holes in the interlayer dielectric layer 119. Further, an adhesive layer and a metal layer are deposited on the bottom and sidewalls of the holes and on the interlayer dielectric layer 119. The adhesive layer is, for example, a material such as tantalum, tantalum nitride, titanium, or titanium nitride, and the metal layer is, for example, a material such as tungsten, copper, or aluminum. The adhesive layer and the metal layer are formed by a method such as physical vapor deposition. Further, a chemical mechanical planarization process is performed to remove the surface metal layer and adhesive layer, thereby forming a first electrode contact via 108, a second electrode contact via 109, a third electrode contact via 110, and a fourth electrode contact via 111. After the chemical mechanical planarization process, the thickness of the interlayer dielectric layer 119 is between 0.7 and 1.1 μm.
[0047] In some embodiments, a back-end metal interconnect is formed, which is, for example, a copper wire metal interconnect or an aluminum wire metal interconnect.
[0048] In this embodiment, preferably, the back-end metal interconnect is a copper wire metal interconnect. Specifically, a first metal layer 112 is formed using a single damask process, including a first metal layer 112a leading to the first port of the capacitor and a first metal layer 112b leading to the second port of the capacitor. The steps include: depositing an etch barrier layer 120 and a dielectric layer 121 using chemical vapor deposition, wherein the etch barrier layer 120 and the dielectric layer 121 are, for example, a combination of nitride and oxide; then, performing photolithography and etching processes to form concave trenches; then, depositing a diffusion barrier layer and a seed layer using physical vapor deposition; then, performing an electroplating process to fill with copper; and then performing a chemical mechanical planarization process to remove the diffusion barrier layer and copper from the surface, thereby forming the first metal layer 112, the thickness of which is between 0.8-1.5 μm.
[0049] Further, a first via 113 and a second metal layer 114 are formed using a dual damascene process, including a first via 113a and a second metal layer 114a leading out a first port of a capacitor, and a first via 113b and a second metal layer 114b leading out a second port of a capacitor. The steps include: depositing an etch barrier layer 122 and a dielectric layer 123 using chemical vapor deposition; then performing two photolithography and etching processes to form vias and concave trenches; then depositing a diffusion barrier layer and a seed layer using physical vapor deposition; then performing an electroplating process to fill with copper; and then performing a chemical mechanical planarization process to remove the diffusion barrier layer and copper from the surface, thereby forming the first via 113 and the second metal layer 114. The thickness of the first via 113 is between 0.8 and 1.2 μm, and the thickness of the second metal layer 114 is between 0.8 and 1.5 μm.
[0050] Further, vias 124, pads 125, and windows 126 are formed, including vias 124a, pads 125a, and windows 126a leading out the first port of the capacitor, and vias 124b, pads 125b, and windows 126b leading out the second port of the capacitor. The steps include: depositing an etch barrier layer 126 and a dielectric layer 127 using chemical vapor deposition; then performing photolithography and etching processes to form vias 124; then depositing aluminum using physical vapor deposition; then performing photolithography and etching processes to form pads 125, the thickness of which is between 2-3 μm; then depositing a passivation layer 128 using chemical vapor deposition; then performing photolithography and etching processes to form windows 126.
[0051] Figure 4 and Figure 5 A schematic diagram of a capacitor chip composed of an array of trench capacitor cells is shown, providing a metal interconnection scheme for reducing impedance for capacitor chips with different packages. For simplification, only the capacitor area is shown, omitting areas such as the package strips and cut lines. The capacitor area only shows the second metal layer 114, the via 124, the pad layer 125, and the window 126.
[0052] Reference Figure 4 If the opening of the capacitor chip is located on the left and right sides of the chip, the capacitor unit does not rotate, the second metal layer 114 and the through hole 124 extend laterally, and the through hole 124 and the pad layer 125 are placed on the left and right sides of the chip.
[0053] Reference Figure 5 If the opening of the capacitor chip is located on the upper and lower sides of the chip, the capacitor unit rotates 90° clockwise or counterclockwise around the center of the capacitor unit. The second metal layer 114 and the through hole 124 extend vertically, and the through hole 124 and the pad layer 125 are placed on the upper and lower sides of the chip.
[0054] In summary, this invention effectively improves capacitance density based on a multi-layer stacked structure. In addition, the optimized arrangement of electrode plates, contact vias, and metal interconnect structures can form a capacitor chip with high density and low equivalent series inductance. The capacitor chip can be applied to different package sizes.
[0055] It should be noted that, in the specific embodiments described above, the terms used to describe the orientation or positional relationship, such as "above," "below," "left," "right," "horizontal," and "vertical," refer only to the orientation or positional relationship in the accompanying drawings, and do not indicate or imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation. Furthermore, in describing the embodiments of this utility model in detail, in order to clearly illustrate the structure of this utility model for ease of explanation, the structure in the accompanying drawings is not drawn to scale and has been partially enlarged, deformed, and simplified. Therefore, it should not be interpreted as a limitation of this utility model.
Claims
1. A trench capacitor unit, characterized in that, include: substrate; A 2x2 trench array group, wherein the trench array group is placed on the substrate; The first, second, third, and fourth plates are sequentially isolated by the first, second, and third dielectric layers to form a multilayer stacked capacitor. Contact holes for the first, second, third, and fourth electrode plates; The metal interconnect layer includes a first metal layer, a second metal layer, and a first via layer therebetween.
2. The trench capacitor unit according to claim 1, characterized in that, The trench array group contains several trenches of equal number, length, width, and spacing, and extends alternately in the horizontal and vertical directions with the center of the capacitor unit as the axis.
3. A trench capacitor unit according to claim 1, characterized in that, The first, second, third, and fourth plates have 1x1, 1x2, 2x2, and 2x2 arrays, respectively.
4. A trench capacitor unit according to claim 1, characterized in that, The single first, second, third, and fourth electrode plates sequentially surround two second electrode plates, two third electrode plates, a single fourth electrode plate, and a single trench array group.
5. A trench capacitor unit according to claim 1, characterized in that, The first electrode plate is placed at the bottom of the trench, on the sidewall, and on the surface of the substrate, and the second, third, and fourth electrode plates are placed above the first, second, and third electrode plates in sequence.
6. A trench capacitor unit according to claim 1, characterized in that, The first electrode plate has contact holes arranged in an "H" shape and located in the non-overlapping area of the first and second electrode plates.
7. A trench capacitor unit according to claim 1, characterized in that, The contact holes of the second electrode plate are arranged in a "T" shape and are located in the non-overlapping area of the second and third electrode plates.
8. A trench capacitor unit according to claim 1, characterized in that, The contact holes of the third electrode plate are arranged in an "L" shape and are located in the non-overlapping area of the third and fourth electrode plates.
9. A capacitor chip, characterized in that, The capacitor chip includes the trench capacitor unit as described in any one of claims 1-8.