Power conversion device

Abstract

This invention provides a power conversion device that enables smooth switching and efficient operation in buck, boost, and buck-boost modes. The device includes an input terminal, an output terminal, first to fourth switching elements, an inductor, a low-side current sensing module, and a control circuit. The control circuit dynamically adjusts the operation of the switching elements in the input voltage-grounded state, the input voltage-output voltage state, and the output voltage-grounded state based on the sensed signal and the output voltage, thereby stabilizing the output voltage. To overcome the minimum duty cycle limitation, this invention extends the duty cycle in the input voltage-grounded or output voltage-grounded state by adjusting the level of the valley ramp signal or peak ramp signal, and can reduce the operating frequency, thereby reducing switching losses and electromagnetic interference.

Description

Technical Field

[0001] This utility model relates to a power conversion device, and more particularly to a power conversion device that can effectively overcome the limitation of minimum working cycle, improve device efficiency and reduce switching losses, while realizing smooth switching between modes. Background Technology

[0002] Traditional four-switch buck-boost converters convert input voltage to the desired output voltage and can operate across the entire voltage conversion ratio (VCR) range in both buck and boost modes, making them widely used in various electronic devices. However, when the input voltage approaches the output voltage, the converter needs to frequently switch between buck and boost operations, which may lead to increased output voltage ripple or decreased system stability, thus affecting overall performance and power conversion efficiency.

[0003] To address the aforementioned issues, existing technologies have disclosed the division of the voltage conversion range into three different modes: Buck mode, Buck-Boost mode, and Boost mode. Specifically, when the input voltage is greater than the output voltage, the converter operates in Buck mode; when the input voltage is approximately equal to the output voltage, the converter operates in Buck-Boost mode; and when the input voltage is less than the output voltage, it switches to Boost mode. Theoretically, using this control method, the voltage conversion ratio in Buck and Boost modes can be extended indefinitely based on the relationship between the conversion ratio and the duty cycle. However, in practical applications, parasitic effects and the on-time of the power switch significantly limit the achievable duty cycle. Therefore, a minimum duty cycle is typically set during control system design to prevent the converter from performing invalid voltage conversion operations. However, setting a minimum duty cycle also limits the achievable voltage conversion ratio, thus affecting the system's flexibility and efficiency.

[0004] On the other hand, in traditional Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM) architectures (often referred to as CBB architectures), current-mode control is widely used to simplify compensation design and enhance system stability. A key component of current-mode control is current sensing, which plays a crucial role in accurately regulating the output voltage and maintaining system stability. Current sensing can generally be classified into three types: series sensing, high-side sensing, and low-side sensing.

[0005] Series current sensing allows for the capture of inductor current information across all phases of the converter, providing comprehensive feedback to the control system by directly monitoring the inductor current in each phase. However, in series current sensing, all inductor current must pass through the sensing resistor, resulting in significant conduction losses. Furthermore, since the sensing resistor is located at the switching node of the power stage, the current sensing circuit must maintain accuracy when handling high input common-mode transients. This adds considerable complexity to the circuit design, making it extremely challenging to achieve a sensing solution that is both accurate and robust under these conditions.

[0006] The second current sensing method is high-side sensing. In this method, during the inductor demagnetization phase in buck mode, the inductor current does not pass through the sensing resistor, which helps reduce conduction losses in buck mode. However, the implementation of high-side sensing circuitry requires high-voltage components capable of withstanding high input common-mode voltage, which occupies a larger chip area. Furthermore, this method cannot obtain inductor current information during the demagnetization phase, thus only peak current-mode control can be used in all modes. The duration of the demagnetization phase is set to a fixed minimum duty cycle. The setting of the minimum duty cycle must consider several factors, such as input voltage, inductor current, and cycle length. To ensure proper operation under various operating conditions, the minimum duty cycle is usually set to a relatively large value. However, this leads to increased inductor current ripple, ultimately reducing power conversion efficiency. Larger inductor current ripple increases AC losses and peak current in the power switch, resulting in higher conduction losses and limiting achievable efficiency under high load conditions.

[0007] The last current sensing method is low-side sensing, which has the lowest conduction losses because the inductor current only flows through the sensing resistor during specific switching states (e.g., switches S1 and S3 are on, or S2 and S4 are on). However, since limited inductor current information can only be obtained within these specific intervals, the control system must use peak current limiting control in boost mode and valley current-mode control in buck mode. Furthermore, buck mode still requires operation with a fixed minimum duty cycle, which may reduce device efficiency. Additionally, in buck-boost mode, inductor current regulation requires four slope segments to control the voltage, increasing complexity compared to the traditional method (which only requires three slope segments). This not only increases switching losses but also exacerbates electromagnetic interference problems.

[0008] Despite these limitations, low-side sensing remains attractive compared to series and high-side sensing methods due to its smaller impact on conduction losses, especially for applications requiring higher efficiency. Therefore, the industry is working to reduce switching losses in low-side sensing in buck-boost modes to further improve overall device stability and energy efficiency. Utility Model Content

[0009] Therefore, the main objective of this invention is to provide a power conversion device to overcome the shortcomings of the prior art.

[0010] This utility model provides a power conversion device, comprising: an input terminal for receiving an input voltage; an output terminal for providing an output voltage; a first, second, third, and fourth switching element, wherein the first switching element is connected to the input terminal and the second switching element, the second switching element is connected to the third switching element, and the fourth switching element is connected to the third switching element and the output terminal; the connection between the first and second switching elements forms a first node, the connection between the third and fourth switching elements forms a second node, and the connection between the second and third switching elements forms a third node; an inductor connected to the first and second nodes; and a low-side current sensing module disposed between the third node and a ground terminal, used to provide an output voltage when the first to fourth switching elements are operating in an input voltage grounded state and an output voltage... In the voltage-to-ground state, the current between the third node and the ground terminal is sensed, and a sensing signal is generated; and a control circuit, coupled to the low-side current sensing module, the output terminal and the first to fourth switching elements, is used to dynamically switch the first to fourth switching elements to operate in a boost mode, a buck mode and a buck-boost mode according to the sensing signal, the working period of the input voltage-to-ground state and the working period of the output voltage-to-ground state, so as to control the first to fourth switching elements to convert the input voltage into the output voltage with a target voltage value; wherein, in the buck-boost mode, the control circuit controls the first to fourth switching elements to periodically operate in the input voltage-to-ground state, the output voltage-to-ground state and an input voltage-to-output voltage state, and extends the working period of the input voltage-to-ground state or the working period of the output voltage-to-ground state.

[0011] The control circuit includes: an error amplification module for generating an error amplification signal based on the output voltage; a valley ramp signal generation module for generating a valley ramp signal based on the error amplification signal, the operating period of the input voltage ground state, and a mode indication signal; a peak ramp signal generation module for generating a peak ramp signal based on the error amplification signal, the operating period of the output voltage ground state, and the mode indication signal; and a comparator module coupled to the low-side current sensing module, the valley ramp signal generation module, and the peak ramp signal generation module for... The system compares the sensed signal with the valley ramp signal to generate a valley comparison result, and compares the sensed signal with the peak ramp signal to generate a peak comparison result; a drive module, coupled to the comparator module and the first to fourth switching elements, is used to control the first to fourth switching elements to be turned on or off according to the valley comparison result and the peak comparison result; and a mode selection module is used to generate the mode indication signal according to the working period of the input voltage ground state, the working period of the output voltage ground state, the valley comparison result, and the peak comparison result.

[0012] The valley ramp signal generation module includes: a ramp generator for generating a ramp signal; an adder coupled to the ramp generator, the error amplification module, and the comparator module for adding the ramp signal to the error amplification signal to generate the valley ramp signal and outputting it to the comparator module; and a ramp control circuit coupled to the ramp generator and the mode selection module for controlling the ramp generator to add an offset signal to the ramp signal when the mode indication signal indicates a switch from the buck mode to the boost mode, thereby reducing one bit level of the valley ramp signal and extending the working cycle of the output voltage ground state.

[0013] In this step-down mode, when the duty cycle of the output voltage ground state reaches a minimum fixed duty cycle and the valley comparison result and the peak comparison result show that the sensing signal is between the valley ramp signal and the peak ramp signal, the mode indicator signal is changed from indicating the step-down mode to indicating the boost mode.

[0014] The mode indicator signal indicates a switch from the boost mode to the buck mode, and the duty cycle of the input voltage ground state reaches the minimum fixed duty cycle. The ramp control circuit can control the ramp generator to remove the offset signal from the ramp signal to restore the level of the valley ramp signal.

[0015] The ramp generator generates the ramp signal based on a clock signal. The ramp control circuit is further used to control the ramp generator to periodically skip at least one clock cycle of the clock signal when the mode indication signal indicates a switch from the buck mode to the boost mode, so as to reduce the switching frequency of the input voltage ground state, the output voltage ground state, and the input voltage output voltage state.

[0016] The peak ramp signal generation module includes: a ramp generator for generating a ramp signal; an adder coupled to the ramp generator, the error amplification module, and the comparator module for adding the ramp signal to the error amplification signal to generate the peak ramp signal and outputting it to the comparator module; and a ramp control circuit coupled to the ramp generator and the mode selection module for controlling the ramp generator to add an offset signal to the ramp signal when the mode indication signal indicates a switch from the boost mode to the buck mode, thereby boosting one level of the peak ramp signal and extending the operating cycle of the input voltage ground state.

[0017] In this boost mode, when the duty cycle of the input voltage ground state reaches the minimum fixed duty cycle and the valley comparison result and the peak comparison result show that the sensing signal is between the valley ramp signal and the peak ramp signal, the mode selection module changes the mode indication signal from indicating the boost mode to indicating the buck mode.

[0018] The mode indicator signal indicates a switch from buck mode to boost mode, and the duty cycle of the output voltage ground state reaches the minimum fixed duty cycle. The ramp control circuit can control the ramp generator to remove the offset signal from the ramp signal to restore the level of the peak ramp signal.

[0019] The ramp generator generates the ramp signal based on a clock signal. The ramp control circuit is further used to control the ramp generator to periodically skip at least one clock cycle of the clock signal when the mode indication signal indicates a switch from the boost mode to the buck mode, so as to reduce the switching frequency of the input voltage ground state, the output voltage ground state and the input voltage output voltage state. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a power conversion device.

[0021] Figure 2A , Figure 2B and Figure 2C for Figure 1 A schematic diagram showing the current direction of a power conversion device operating in different states.

[0022] Figure 3A for Figure 1 A schematic diagram of the relevant signals when the power conversion device operates in boost mode.

[0023] Figure 3B for Figure 1 A schematic diagram of the relevant signals when the power conversion device operates in buck mode.

[0024] Figure 3C for Figure 1 A schematic diagram of the relevant signals when the power conversion device operates in buck-boost mode.

[0025] Figure 4 This is a schematic diagram of the power conversion device according to Embodiment 1 of this utility model.

[0026] Figure 5A for Figure 4 The diagram shows the relevant signals for the power conversion device to switch from buck mode to buck-boost mode and then back to boost mode.

[0027] Figure 5B for Figure 4 The diagram shows the relevant signals for the power conversion device to switch from boost mode to buck-boost mode and then back to buck mode.

[0028] Figure 6 for Figure 4 A schematic diagram of the operation flow of the control circuit.

[0029] Figure 7A This is a schematic diagram of the power conversion device according to Embodiment 1 of this utility model.

[0030] Figure 7B This is a schematic diagram of a voltage-to-current converter.

[0031] Figure 8 This is a schematic diagram of the control flow of Embodiment 1 of this utility model.

[0032] Figure 9A and Figure 9B This is a schematic diagram comparing inductor currents.

[0033] Figure reference numerals: 10 - Power conversion device; 102 - Input terminal; Vin - Input voltage; 104 - Output terminal; Vout - Output voltage; SW1~SW4 - Switching elements; L - Inductor; 12 - Low-side current sensing module; 14 - Control circuit; N1 - First node; N2 - Second node; N3 - Third node; Gnd - Ground; Rsen - Resistor; 120 - Current sensing unit; Vsen - Sensing signal; Vin_Gnd - Input voltage grounding state; Vin_Vout - Input voltage output voltage state; Gnd_Vout - Output voltage grounding state; 20, 22, 24 - Current direction; IL - Inductor current; 40 - Power conversion device; 42 - Control circuit; 420 - Error amplification module; 422 - Valley ramp signal generation module; 424 - Peak ramp signal generation module; 426 - Comparator module; 428 - Driver module; 430 - Mode selection module; Vea - Error amplification signal; BU - Mode indication signal; Vvl - Valley ramp signal; BO - Mode indication signal; Vpk - Peak ramp signal; CMP_BU - Valley comparison result; CMP_BO - Peak comparison result; 4220 - Ramp generator; 4222 - Adder; 4224 - Ramp control circuit; CT_BU - Control signal; 42 40 - Ramp generator; 4242 - Adder; 4244 - Ramp control circuit; CT_BO - Control signal; Dmin - Minimum fixed duty cycle; CLK - Clock signal; ta1~ta6, tb1~tb6: Time points; Ta12, Ta56, Tb12, Tb56 - Time periods; OS, US - Levels; 60 - Operation flow; 600~634 - Steps; 70 - Power conversion device; 72 - Control circuit; 720 - Error amplification module; 722 - Valley ramp signal generation module; 724 - Peak ramp signal generation module; 726 - Comparator module; 728 - Driver module; 730 - Mode selection Module; EA - Error Amplifier; R1~R3 - Resistors; C1 - Capacitor; Vref - Reference Voltage Generator; CMP1, CMP2 - Comparators; 7280 - Pulse Width Signal Generator; 7282, 7284 - Type D Inverters; 7220 - Ramp Generation Circuit; 7222 - Adder; 7224 - Ramp Control Circuit; 7226 - Voltage to Current Converter; 7240 - Ramp Generation Circuit; 7242 - Adder; 7244 - Ramp Control Circuit; 7246 - Voltage to Current Converter; Vir - Voltage; Iref - Current; 80 - Control Flow; 800~806 - Steps; 90~96 - Curves. Detailed Implementation

[0034] Please refer to Figure 1 , Figure 1This is a schematic diagram of a power conversion device 10. The power conversion device 10 receives an input voltage Vin through an input terminal 102 and provides an output voltage Vout through an output terminal 104. The power conversion device 10 includes switching elements SW1-SW4, an inductor L, a low-side current sensing module 12, and a control circuit 14. Switching element SW1 is connected to the input terminal 102 and switching element SW2; switching element SW2 is connected to switching element SW3; switching element SW4 is connected to switching element SW3 and the output terminal 104. The connection between switching elements SW1 and SW2 forms a first node N1; the connection between switching elements SW3 and SW4 forms a second node N2; and the connection between switching elements SW2 and SW3 forms a third node N3. The inductor L is connected between the first node N1 and the second node N2. The low-side current sensing module 12 is located between the third node N3 and a ground terminal Gnd. It includes a resistor Rsen and a current sensing unit 120 to sense the current passing through the third node N3 and the ground terminal Gnd, and generate a sensing signal Vsen to achieve low conduction loss current monitoring. The control circuit 14 is coupled to the low-side current sensing module 12, the output terminal 104, and the switching elements SW1 to SW4. It is used to dynamically adjust the operation of the switching elements SW1 to SW4 according to the sensing signal Vsen and the output voltage Vout, so that the output voltage Vout approaches a target voltage value.

[0035] Based on the sensing signal Vsen and the output voltage Vout, the control circuit 14 can dynamically adjust the operation of switching elements SW1 to SW4, enabling the power conversion device 10 to operate in buck mode, boost mode, and buck-boost mode. On the other hand, to avoid short circuits and damage caused by the simultaneous conduction of single-sided switches (such as switching elements SW1 and SW2, or switching elements SW3 and SW4), the control circuit 14 controls the switching elements SW1 to SW4 to operate in three specific states: input voltage ground state (Vin_Gnd), input voltage output voltage state (Vin_Vout), and output voltage ground state (Gnd_Vout). In the input voltage ground state Vin_Gnd, the control circuit 14 controls switching elements SW1 and SW3 to be turned on, and switching elements SW2 and SW4 to be turned off, allowing current to flow from the input terminal 102 through switching element SW1, through inductor L, and then through switching element SW3 to ground Gnd. Figure 2A As shown in Figure 20. Under the input voltage and output voltage conditions Vin_Vout, the control circuit 14 controls the switching elements SW1 and SW4 to be turned on, and the switching elements SW2 and SW3 to be turned off, so that the current flows from the input terminal 102 through the switching element SW1, through the inductor L, and then through the switching element SW4 to the output terminal 104, i.e. Figure 2BAs shown in Figure 22. With the output voltage grounded (Gnd_Vout), control circuit 14 controls switching elements SW2 and SW4 to conduct, and switching elements SW1 and SW3 to close, allowing current to flow from ground Gnd through switching element SW2, through inductor L, and then through switching element SW4 to the output terminal 104. Figure 2C As shown in direction 24. By periodically switching between these three states, the control circuit 14 can control the power conversion device 10 to operate in buck mode, boost mode, and buck-boost mode, thereby maintaining system stability.

[0036] Specifically, when the input voltage Vin is lower than the output voltage Vout, the power conversion device 10 should operate in boost mode, such as... Figure 3A As shown. In boost mode, control circuit 14 controls switching elements SW1 to SW4 to operate periodically in the input voltage ground state Vin_Gnd and the input voltage output voltage state Vin_Vout, thereby controlling the inductor L to periodically store and release energy. Therefore, the current IL of inductor L (hereinafter referred to as inductor current IL) increases during the operating cycle of the input voltage ground state Vin_Gnd and decreases during the operating cycle of the input voltage output voltage state Vin_Vout, keeping inductor L in the magnetization stage and realizing the conversion from a lower input voltage Vin to a higher output voltage Vout.

[0037] When the input voltage Vin is higher than the output voltage Vout, the power conversion device 10 should operate in buck mode, such as... Figure 3B As shown. In buck mode, control circuit 14 controls switching elements SW1 to SW4 to operate periodically in the output voltage ground state Gnd_Vout and the input voltage output voltage state Vin_Vout. Therefore, the inductor current IL increases during the input voltage output voltage cycle and decreases during the output voltage ground state Gnd_Vout cycle, keeping the inductor L in a demagnetized phase, thus achieving the transition from a higher input voltage Vin to a lower output voltage Vout.

[0038] When the input voltage Vin is close to the output voltage Vout, in order to avoid the power conversion device 10 frequently switching between buck and boost modes, the power conversion device 10 should operate in buck-boost mode, such as... Figure 3CAs shown, this achieves smooth mode switching. In buck-boost mode, control circuit 14 controls switching elements SW1 to SW4 to operate periodically in the input voltage ground state Vin_Gnd, the input voltage output voltage state Vin_Vout, and the output voltage ground state Gnd_Vout. Specifically, the inductor current IL increases during the operating cycle of the input voltage ground state Vin_Gnd, decreases during the operating cycle of the output voltage ground state Gnd_Vout, and remains constant during the operating cycle of the input voltage output voltage state Vin_Vout, allowing the power conversion device 10 to smoothly switch between buck and boost modes.

[0039] Furthermore, because the power conversion device 10 employs a low-side current sensing architecture, the control circuit 14 can only sense the current IL when switching elements S1 and S3 or switching elements S2 and S4 are turned on, i.e., the aforementioned input voltage ground state Vin_Gnd or output voltage ground state Gnd_Vout. It must also operate with a minimum duty cycle to prevent the power conversion device 10 from performing invalid voltage conversions. These limitations reduce the efficiency of the power conversion device 10, increase switching losses, and may even exacerbate electromagnetic interference problems.

[0040] In this context, the present invention introduces a mechanism to extend the duty cycle of the input voltage ground state Vin_Gnd (i.e., extend the on-time of switching elements SW1 and SW3) or the output voltage ground state Gnd_Vout (i.e., extend the on-time of switching elements SW2 and SW4) in buck-boost mode. In other words, when the power conversion device 10 operates in buck-boost mode, the control circuit 14, in addition to controlling the switching elements SW1 to SW4 to periodically operate in the input voltage ground state Vin_Gnd, the input voltage output state Vin_Vout, and the output voltage ground state Gnd_Vout, also extends the duty cycle of either the input voltage ground state Vin_Gnd or the output voltage ground state Gnd_Vout. For example, in one embodiment, if the power conversion device 10 switches from buck mode to buck-boost mode, and the duty cycle of the output voltage ground state Gnd_Vout reaches a minimum fixed duty cycle, the control circuit 14 can extend the duty cycle of the output voltage ground state Gnd_Vout. In another embodiment, if the power conversion device 10 switches from boost mode to buck-boost mode, and the duty cycle of the input voltage ground state Vin_Gnd reaches a minimum fixed duty cycle, the control circuit 14 can extend the duty cycle of the input voltage ground state Vin_Gnd. Besides extending the duty cycle of the input voltage ground state Vin_Gnd or the output voltage ground state Gnd_Vout, in another embodiment, the control circuit 14 can further reduce the operating frequency to extend the duty cycle of the input voltage output voltage state Vin_Vout, thereby reducing switching losses.

[0041] It should be noted that this invention reduces instability and output voltage ripple caused by mode switching by appropriately extending the duty cycle of the input voltage ground state Vin_Gnd or the output voltage ground state Gnd_Vout in buck-boost mode. This allows the power conversion device 10 to switch more smoothly between boost, buck, and buck-boost modes. It should be understood that the implementation of this invention is not limited to a specific architecture; different technical solutions can be adopted to achieve the above objectives depending on system requirements or application scope.

[0042] For example, please refer to Figure 4 , Figure 4This is a schematic diagram of a power conversion device 40 according to an embodiment of the present invention. For ease of explanation, the same components in the power conversion device 40 and the power conversion device 10 are represented by the same symbols. In addition, a control circuit 42 of the power conversion device 40 includes an error amplification module 420, a valley ramp signal generation module 422, a peak ramp signal generation module 424, a comparator module 426, a driver module 428, and a mode selection module 430. The error amplification module 420 is coupled to the output terminal 104 and is used to generate an error amplification signal Vea based on the output voltage Vout, and provide it to the valley ramp signal generation module 422 and the peak ramp signal generation module 424. The valley ramp signal generation module 422 can generate a valley ramp signal Vvl based on the error amplification signal Vea, the working period of the input voltage ground state Vin_Gnd, and the mode indication signal BU provided by the mode selection module 430. The peak ramp signal generation module 424 generates a peak ramp signal Vpk based on the error amplification signal Vea, the duty cycle of the output voltage ground state Gnd_Vout, and the mode indication signal BO provided by the mode selection module 430. It should be noted that information related to the input voltage ground state Vin_Gnd (such as the duty cycle) can be represented by a signal, which, for simplicity, is also represented by the component symbol "Vin_Gnd," and is received by the valley ramp signal generation module 422 and the mode selection module 430. Similarly, information related to the output voltage ground state Gnd_Vout (such as the duty cycle) can be represented by a signal, which, for simplicity, is also represented by the component symbol "Gnd_Vout," and is received by the peak ramp signal generation module 424 and the mode selection module 430. Comparator module 426 is coupled to low-side current sensing module 12, valley ramp signal generation module 422, and peak ramp signal generation module 424. It compares the sensing signal Vsen with the valley ramp signal Vvl to generate a valley comparison result CMP_BU, and compares the sensing signal Vsen with the peak ramp signal Vpk to generate a peak comparison result CMP_BO. Drive module 428 is coupled to comparator module 426 and switching elements SW1-SW4. It controls the switching elements SW1-SW4 to turn on or off based on the valley comparison result CMP_BU and peak comparison result CMP_BO generated by comparator module 426, thereby achieving voltage conversion. Mode selection module 430 generates mode indication signals BO and BU based on the operating cycle of the input voltage ground state Vin_Gnd, the operating cycle of the output voltage ground state Gnd_Vout, the valley comparison result CMP_BU, and the peak comparison result CMP_BO, to dynamically switch operating modes.Specifically, when the sensed signal Vsen is less than the valley ramp signal Vvl and the peak ramp signal Vpk, the power conversion device 40 should operate in boost mode; when the sensed signal Vsen is greater than the valley ramp signal Vvl and the peak ramp signal Vpk, the power conversion device 40 should operate in buck mode; and when the sensed signal Vsen is greater than the valley ramp signal Vvl and less than the peak ramp signal Vpk, the power conversion device 40 should operate in buck-boost mode.

[0043] In other words, in the control circuit 42, the comparator module 426 compares the sensing signal Vsen with the valley ramp signal Vvl and the peak ramp signal Vpk, and accordingly controls the switching elements SW1 to SW4 to turn on or off through the drive module 428. The valley ramp signal Vvl and the peak ramp signal Vpk contain components of the error amplification signal Vea (which is related to the output voltage Vout), and are also related to the mode indication signals BU and BO, the operating cycle of the output voltage ground state Gnd_Vout, and the operating cycle of the input voltage ground state Vin_Gnd. That is, when the valley ramp signal generation module 422 and the peak ramp signal generation module 424 generate the valley ramp signal Vvl and the peak ramp signal Vpk, this embodiment of the invention will consider the current operating mode (via the mode indication signals BU and BO), as well as the operating cycle of the output voltage ground state Gnd_Vout and the operating cycle of the input voltage ground state Vin_Gnd. In this way, when the working period of the output voltage ground state Gnd_Vout or the input voltage ground state Vin_Gnd is too small, for example, less than or equal to a minimum fixed working period Dmin, the voltage conversion efficiency will be limited. Therefore, the present invention can extend the working period of the output voltage ground state Gnd_Vout or the input voltage ground state Vin_Gnd as appropriate.

[0044] Specifically, the valley ramp signal generation module 422 includes a ramp generator 4220, an adder 4222, and a ramp control circuit 4224, while the peak ramp signal generation module 424 includes a ramp generator 4240, an adder 4242, and a ramp control circuit 4244. The ramp generator 4220 is used to generate a ramp signal. The adder 4222 is coupled to the ramp generator 4220, the error amplification module 420, and the comparator module 426, and is used to add the ramp signal generated by the ramp generator 4220 to the error amplification signal Vea to generate a valley ramp signal Vvl, which is then output to the comparator module 426. The mode selection module 430 generates a mode indication signal BU to indicate whether the power conversion device 40 is operating in buck mode (for example, BU=1 indicates that the power conversion device 40 is operating in buck mode, and BU=0 indicates that the power conversion device 40 is not operating in buck mode, that is, the power conversion device 40 is operating in boost mode). Specifically, when the indication signal BU indicates buck mode (BU=1), the mode indication signal BO indicates non-boost mode (BO=0); when the indication signal BU indicates non-buffered mode (BU=0), the mode indication signal BO indicates boost mode (BO=1). When in buck mode, the mode selection module 430 determines that the duty cycle of the output voltage ground state Gnd_Vout reaches a minimum fixed duty cycle Dmin, and determines that the sensing signal Vsen is between the valley ramp signal Vvl and the peak ramp signal Vpk based on the valley comparison result CMP_BU and the peak comparison result CMP_BO. In this case, the mode selection module 430 changes the generated mode indication signal BU (BU = 0) to instruct the power conversion device 40 to switch to boost mode (via buck-boost mode). The ramp control circuit 4224 is coupled to the ramp generator 4220 and to the mode selection module 430 to receive the mode indication signal BU. When the mode indicator signal BU indicates a switch from buck mode to boost mode (i.e., from BU=1 to BU=0), the ramp control circuit 4224 outputs a control signal CT_BU to control the ramp generator 4220 to add an offset signal to the ramp signal, thereby changing the level of the valley ramp signal Vvl (which may be increased or decreased depending on the circuit design), thus extending the duty cycle of the output voltage ground state Gnd_Vout. For example, the on-time of switching elements SW2 and SW4 can be extended by the drive module 428 to extend the duty cycle of the output voltage ground state Gnd_Vout.

[0045] In other words, when the sensed signal Vsen is greater than both the valley ramp signal Vvl and the peak ramp signal Vpk, the power conversion device 40 operates in buck mode (i.e., the mode indication signal BU indicates buck mode). Switching elements SW1 to SW4 periodically switch between the output voltage ground state Gnd_Vout and the input voltage output voltage state Vin_Vout. The comparison result CMP_BU between the sensed signal Vsen and the valley ramp signal Vvl determines the duty cycle of the output voltage ground state Gnd_Vout. Next, if the sensed signal Vsen changes to be between the valley ramp signal Vvl and the peak ramp signal Vpk, it indicates that the power conversion device 40 should first switch to buck-boost mode. At this time, if the duty cycle of the output voltage ground state Gnd_Vout reaches the minimum fixed duty cycle Dmin, it indicates that the voltage conversion efficiency will be limited. According to the embodiment of this case, the ramp control circuit 4224 can (through the control signal CT_BU) control the ramp generator 4220 to add the generated ramp signal to the offset signal, so that the difference between the sensing signal Vsen and the valley ramp signal Vvl becomes larger (making it less likely for the sensing signal Vsen to touch the valley ramp signal Vvl), thereby extending the working cycle of the output voltage ground state Gnd_Vout.

[0046] After the ramp control circuit 4224 controls the ramp generator 4220 to add the ramp signal to the offset signal (i.e., the valley ramp signal Vvl contains the offset signal), if the sensed signal Vsen in buck-boost mode is less than the valley ramp signal Vvl and the peak ramp signal Vpk, and the ramp control circuit 4244 determines that the working cycle of the output voltage ground state Gnd_Vout reaches the minimum fixed working cycle Dmin again, it indicates that the power conversion device 40 should switch to boost mode. At this time, the valley ramp signal Vvl, which has been added with the offset signal, remains unchanged, while the peak ramp signal Vpk will recover the added offset signal (detailed later). The ramp control circuit 4224 will only control the ramp generator 4220 to remove the offset signal from the ramp signal in order to restore the level of the valley ramp signal Vvl when the mode indication signal BU indicates that the ramp mode has switched from the buck mode (i.e., from BU=0 to BU=1) and the ramp control circuit 4224 determines that the working period of the input voltage ground state Vin_Gnd has reached the minimum fixed working period Dmin.

[0047] In short, when the power conversion device 40 switches from buck mode to buck-boost mode, if the duty cycle of the output voltage ground state Gnd_Vout reaches the minimum fixed duty cycle Dmin, an offset signal will be added to the valley ramp signal Vvl. The added offset signal will only be removed from the valley ramp signal Vvl when the power conversion device 40 switches back to buck-boost mode (and then to buck mode) after operating in boost mode.

[0048] On the other hand, the ramp generator 4240 of the peak ramp signal generation module 424 is used to generate a ramp signal. The adder 4242 of the peak ramp signal generation module 424 is coupled to the ramp generator 4240, the error amplification module 420 and the comparator module 426, and is used to add the ramp signal generated by the ramp generator 4240 to the error amplification signal Vea to generate the peak ramp signal Vpk, and output it to the comparator module 426. The mode selection module 430 generates a mode indication signal BO to indicate whether the power conversion device 40 is operating in boost mode (for example, BO=1 indicates that the power conversion device 40 is operating in boost mode, and BO=0 indicates that the power conversion device 40 is not operating in boost mode, that is, the power conversion device 40 is operating in buck mode). When in boost mode, the mode selection module 430 determines that the duty cycle of the input voltage ground state Vin_Gnd reaches a minimum fixed duty cycle Dmin, and determines that the sensing signal Vsen is between the valley ramp signal Vvl and the peak ramp signal Vpk based on the valley comparison result CMP_BU and the peak comparison result CMP_BO. In this case, the mode selection module 430 changes the generated mode indication signal BO (BO = 0) to instruct the power conversion device 40 to switch to buck mode (via buck-boost mode). The ramp control circuit 4244 of the peak ramp signal generation module 424 is coupled to the ramp generator 4240 and also coupled to the mode selection module 430 to receive the mode indication signal BO. When the mode indicator signal BO indicates a switch from buck mode to boost mode (i.e., from BO=1 to BO=0), the ramp control circuit 4224 outputs a control signal CT_BO to control the ramp generator 4240 to add an offset signal to the ramp signal, thereby changing the level of the peak ramp signal Vpk (which may be increased or decreased depending on the circuit design), thus extending the duty cycle of the input voltage ground state Vin_Gnd. For example, the on-time of switching elements SW1 and SW3 can be extended by the drive module 428 to extend the duty cycle of the input voltage ground state Vin_Gnd.

[0049] In other words, when the sensed signal Vsen is less than the valley ramp signal Vvl and the peak ramp signal Vpk, the power conversion device 40 operates in boost mode (i.e., the mode indication signal BO indicates boost mode). Switching elements SW1 to SW4 periodically switch between the input voltage ground state Vin_Gnd and the input voltage output voltage state Vin_Vout. The peak value comparison result CMP_BO between the sensed signal Vsen and the peak ramp signal Vpk determines the duty cycle of the input voltage ground state Vin_Gnd. Then, if the sensed signal Vsen changes to be between the valley ramp signal Vvl and the peak ramp signal Vpk, it indicates that the power conversion device 40 should switch to buck-boost mode. At this time, if the duty cycle of the input voltage ground state Vin_Gnd reaches the minimum fixed duty cycle Dmin, it indicates that the voltage conversion efficiency will be limited. According to the embodiment of this case, the ramp control circuit 4244 can (through the control signal CT_BO) control the ramp generator 4240 to add the generated ramp signal to the offset signal, so that the difference between the sensing signal Vsen and the peak ramp signal Vpk becomes larger (making it less likely for the sensing signal Vsen to touch the peak ramp signal Vpk), thereby extending the working cycle of the input voltage ground state Vin_Gnd.

[0050] After the ramp control circuit 4244 controls the ramp generator 4240 to add the ramp signal to the offset signal (i.e., the peak ramp signal Vpk includes the offset signal), if the sensed signal Vsen is greater than the valley ramp signal Vvl and the peak ramp signal Vpk in buck-boost mode, and the ramp control circuit 4224 determines that the working cycle of the input voltage ground state Vin_Gnd reaches the minimum fixed working cycle Dmin again, it indicates that the power conversion device 40 should switch to buck mode. At this time, the peak ramp signal Vpk with the added offset signal remains unchanged, while the valley ramp signal Vvl will remove the added offset signal (as described above). The ramp control circuit 4244 will only control the ramp generator 4240 to remove the offset signal from the ramp signal in order to restore the level of the peak ramp signal Vpk when the mode indication signal BO indicates that the ramp mode has switched from buck mode to boost mode (i.e., from BO=0 to BO=1) and the ramp control circuit 4244 determines that the output voltage ground state Gnd_Vout's working period has reached the minimum fixed working period Dmin.

[0051] In short, when the power conversion device 40 switches from boost mode to buck-boost mode, if the duty cycle of the input voltage ground state Vin_Gnd reaches the minimum fixed duty cycle Dmin, an offset signal will be added to the peak ramp signal Vpk. The added offset signal will only be removed by the peak ramp signal Vpk when the power conversion device 40 switches back to buck-boost mode (and then to boost mode) after operating in buck mode.

[0052] As can be seen from the control mechanism of the valley ramp signal generation module 422 and the peak ramp signal generation module 424, this embodiment of the present invention can effectively overcome the limitation of the minimum fixed working period Dmin by dynamically adjusting the level of the valley ramp signal Vvl and the peak ramp signal Vpk to extend the working period of the output voltage ground state Gnd_Vout or the input voltage ground state Vin_Gnd in a timely manner.

[0053] On the other hand, in addition to extending the duty cycle of the output voltage ground state Gnd_Vout or the input voltage ground state Vin_Gnd in the buck-boost mode as needed, in one embodiment, the valley ramp signal generation module 422 and the peak ramp signal generation module 424 can further reduce the operating frequency of the power conversion device 40, that is, reduce the switching frequency of the input voltage ground state Vin_Gnd, the output voltage ground state Gnd_Vout, and the input voltage output voltage state Vin_Vout. For example, if the ramp generators 4220 and 4240 generate ramp signals according to a clock signal CLK, the ramp control circuits 4224 and 4244 can further control the ramp generator 4220 to periodically skip at least one clock cycle of the clock signal CLK when switching to the buck-boost mode.

[0054] The above-mentioned operating methods for extending the duty cycle of the output voltage ground state Gnd_Vout and the input voltage ground state Vin_Gnd, as well as reducing the operating frequency, of the power conversion device 40 can be referred to together. Figure 5A and Figure 5B For a more complete explanation.

[0055] first, Figure 5A This diagram illustrates the signals related to the power conversion device 40 switching from buck mode to buck-boost mode and entering boost mode. Figure 5A The upper half shows the relative relationship between the sensing signal Vsen and the valley ramp signal Vvl and peak ramp signal Vpk (i.e., the input signals of comparator module 426). The lower half shows the operating cycle of the output voltage ground state Gnd_Vout, the operating cycle of the input voltage ground state Vin_Gnd, the control signals of the switching elements SW1 to SW4, the peak comparison result CMP_BO, the valley comparison result CMP_BU, the control signal CT_BU, CT_BO, and the clock signal CLK. It should be noted that because the power conversion device 40 adopts a low-side current sensing architecture, the low-side current sensing module 12 can only output the sensing signal Vsen in the input voltage ground state Vin_Gnd or the output voltage ground state Gnd_Vout. Therefore, in Figure 5AIn the diagram, the solid line segment represents the actual sensing signal Vsen output by the low-side current sensing module 12, while the dashed line segment represents the virtual sensing signal Vsen that was not detected by the low-side current sensing module 12.

[0056] like Figure 5A As shown, when the power conversion device 40 operates in buck mode, the switching elements SW1 to SW4 periodically switch between the output voltage ground state Gnd_Vout and the input voltage output voltage state Vin_Vout. Then, at time points ta1 to ta2, the comparator module 426 detects that the sensing signal Vsen is between the valley ramp signal Vvl and the peak ramp signal Vpk, indicating that the power conversion device 40 should switch to buck-boost mode. Meanwhile, if the time period Ta12 from time point ta1 to ta2 is less than or equal to the minimum fixed working period Dmin (Ta12≤Dmin), that is, the working period of the output voltage ground state Gnd_Vout reaches the minimum fixed working period Dmin, then the valley ramp signal generation module 422 will add the generated ramp signal to the offset signal, so that the valley ramp signal Vvl is reduced by one bit OS. Then the difference between the sensing signal Vsen and the valley ramp signal Vvl will become larger, thus extending the working period of the output voltage ground state Gnd_Vout. For example, in the next cycle, the working period of the output voltage ground state Gnd_Vout is between time point ta3 and ta4, which is significantly longer than the time period Ta12 from time point ta1 to ta2, thus improving the voltage conversion efficiency.

[0057] on the other hand, Figure 5B This diagram illustrates the signals involved in the power conversion device 40 switching from boost mode to buck-boost mode and entering buck mode. The meanings of these signals are as previously stated. Figure 5A Explanation. For example... Figure 5BAs shown, when the power conversion device 40 operates in boost mode, the switching elements SW1 to SW4 periodically switch between the input voltage ground state Vin_Gnd and the input voltage output voltage state Vin_Vout. Then, at time points tb1 to tb2, the comparator module 426 detects that the sensing signal Vsen is between the valley ramp signal Vvl and the peak ramp signal Vpk, indicating that the power conversion device 40 should switch to buck-boost mode. Meanwhile, when time points tb1 to tb2 are less than or equal to the minimum fixed working period Dmin (Tb12≤Dmin), that is, when the working period of the input voltage ground state Vin_Gnd reaches the minimum fixed working period Dmin, the peak ramp signal generation module 424 adds the generated ramp signal to the offset signal, thereby boosting the peak ramp signal Vpk by one bit quasi-US. The difference between the sensing signal Vsen and the peak ramp signal Vpk will increase, thus extending the working period of the input voltage ground state Vin_Gnd. For example, in the next cycle, the working period of the input voltage ground state Vin_Gnd is between time points tb3 and tb4, which is significantly longer than the time period Tb12 between time points tb1 and tb2, thus improving the voltage conversion efficiency.

[0058] Regarding the timing of the recovery after adding the offset signal to the valley ramp signal Vvl and the peak ramp signal Vpk, please also refer to... Figure 5A and Figure 5B .like Figure 5A As shown, when the valley ramp signal Vvl contains an offset signal (i.e., at time point ta3) to lower its level OS, at time point ta5 to ta6, the sensed signal Vsen is less than both the valley ramp signal Vvl and the peak ramp signal Vpk. Furthermore, when the ramp control circuit 4244 determines that the output voltage ground state Gnd_Vout's operating cycle again reaches the minimum fixed operating cycle Dmin (i.e., the time period Ta56 from time point ta5 to ta6 is less than or equal to the minimum fixed operating cycle Dmin, Ta56≤Dmin)), it indicates that the power conversion device 40 should switch to boost mode. At this time, the valley ramp signal Vvl remains at a lower level OS, and the ramp control circuit 4244 controls the ramp generator 4240 to add the offset signal (e.g., at time point ta3) to the peak ramp signal Vpk via the control signal CT_BO. Figure 5B At time points tb3 to tb4, the peak ramp signal Vpk is removed from the boost level (US), causing the peak ramp signal Vpk to return to its original level. This continues until... Figure 5BFrom time point tb5 to tb6, when the sensed signal Vsen is greater than both the valley ramp signal Vvl and the peak ramp signal Vpk, and the ramp control circuit 4224 determines that the working period of the input voltage ground state Vin_Gnd has reached the minimum fixed working period Dmin (i.e., the time period Tb56 from time point tb5 to tb6 is less than or equal to the minimum fixed working period Dmin, Tb56≤Dmin), it indicates that the power conversion device 40 should switch to buck mode. The ramp control circuit 4224 controls the ramp generator 4220 to add the offset signal (e.g., at) the valley ramp signal Vvl through the control signal CT_BU. Figure 5B After time point tb6, the valley ramp signal Vvl is raised to level OS, thus restoring the level of the valley ramp signal Vvl.

[0059] In short, switching from buck mode to buck-boost mode ( Figure 5A At time point ta3, the valley ramp signal Vvl of the added offset signal needs to wait for the power conversion device 40 to enter boost mode. Figure 5A After point ta6, it continued until Figure 5B Before time tb1, when switching to buck-boost mode ( Figure 5B After point tb4, it is necessary to re-enter buck mode. Figure 5B The valley ramp signal Vvl will only be removed after time point tb6; similarly, when switching from boost mode to buck-boost mode ( Figure 5B At time tb3, the peak ramp signal Vpk of the added offset signal needs to wait for the power conversion device 40 to enter buck mode. Figure 5B After point tb6, continuing until Figure 5A Before time point ta1, when switching to buck-boost mode ( Figure 5A After point ta4, it is necessary to re-enter boost mode. Figure 5A It will only be removed by the peak ramp signal Vpk after time point ta6.

[0060] In addition, observation Figure 5A and Figure 5BIt is known that the valley ramp signal Vvl and the peak ramp signal Vpk have the same phase and both operate synchronously with the device's clock signal CLK. This phase consistency characteristic allows the valley ramp signal generation module 422 and the peak ramp signal generation module 424 to share the same timing basis, thereby simplifying the design and implementation of ramp generators 4220 and 4240. For example, only a single ramp generation circuit with a voltage offset mechanism is needed to generate the two signals, without the need for additional phase adjustment circuits. This not only reduces hardware complexity and manufacturing costs but also improves the coordination between signals and reduces control misjudgments caused by phase errors. Those skilled in the art can further utilize this characteristic to adjust the amplitude or slope of the valley ramp signal Vvl and the peak ramp signal Vpk according to application requirements, for example, by dynamically adjusting through adjustable resistors or digital control parameters to meet the precise control requirements of different operating modes.

[0061] The operation of the aforementioned control circuit 42 can be summarized as an operation flow 60, such as... Figure 6 The diagram illustrates the operation flow 60, which begins at step 600 and can be divided into two parts. In step 602, the valley ramp signal generation module 422 and the peak ramp signal generation module 424 check the mode indication signals BU and BO output by the mode selection module 430. In this example, if the mode indication signal BU is 1, the control circuit 42 executes the right half of the operation flow 60, i.e., steps 604 to 618; if the mode indication signal BO is 1, the control circuit 42 executes the left half of the operation flow 60, i.e., steps 620 to 634. First, if the mode indication signal BU is 1, the clock signal CLK first triggers the working cycle of the output voltage ground state Gnd_Vout (step 604), at which time the inductor is discharging. Next, the control circuit 42 detects the working cycle of the output voltage ground state Gnd_Vout (step 606). If the working cycle of the output voltage ground state Gnd_Vout reaches the minimum fixed working cycle Dmin (i.e., the working cycle of the output voltage ground state Gnd_Vout is less than or equal to the minimum fixed working cycle Dmin), then... Figure 6If Gnd_Vout ≤ Dmin, the circuit should switch to boost mode. Therefore, the mode indicator signal BU is set to 0, and the mode indicator signal BO is set to 1 (step 608). Regardless of whether the duty cycle of the output voltage ground state Gnd_Vout reaches the minimum fixed duty cycle Dmin, the control circuit 42 checks the relationship between the sensing signal Vsen, the valley ramp signal Vvl, and the peak ramp signal Vpk (step 610). If the sensing signal Vsen is less than the valley ramp signal Vvl, the control circuit 42 turns off the output voltage ground state Gnd_Vout and starts the input voltage output voltage state Vin_Vout (step 612), and starts the next cycle according to the trigger of the clock signal CLK. In addition, in order to determine the timing of mode switching, when the control circuit 42 detects that the sensing signal Vsen is less than the valley ramp signal Vvl, it immediately samples the position of the sensing signal Vsen to the peak ramp signal Vpk. If the sensed signal Vsen is detected to be less than the peak ramp signal Vpk, the control circuit 42 activates the input voltage ground state Vin_Gnd instead of the input voltage output voltage state Vin_Vout (step 614), indicating that the power conversion device 40 has entered the buck-boost mode. Subsequently, when the sensed signal Vsen is greater than the peak ramp signal Vpk, the input voltage output voltage state Vin_Vout is activated (step 616). The power conversion device 40 skips one clock cycle CLK and maintains the activated input voltage output voltage state Vin_Vout during this period (step 618). After achieving the frequency reduction effect, it enters the next cycle according to the triggering of the clock signal CLK.

[0062] Correspondingly, if the mode indication signal BO is 1, the clock signal CLK first triggers the operating cycle of the input voltage ground state Vin_Gnd (step 620), at which time the inductor is charging. Next, the control circuit 42 detects the operating cycle of the input voltage ground state Vin_Gnd (step 622). If the operating cycle of the input voltage ground state Vin_Gnd reaches the minimum fixed operating cycle Dmin (i.e., the operating cycle of the input voltage ground state Vin_Gnd is less than or equal to the minimum fixed operating cycle Dmin), then... Figure 6If Vin_Gnd ≤ Dmin, the circuit should switch to buck mode. Therefore, the mode indicator signal BO is set to 0, and the mode indicator signal BU is set to 1 (step 624). Regardless of whether the working cycle of the input voltage ground state Vin_Gnd reaches the minimum fixed working cycle Dmin, the control circuit 42 checks the relationship between the sensing signal Vsen, the valley ramp signal Vvl, and the peak ramp signal Vpk (step 626). If the sensing signal Vsen is greater than the peak ramp signal Vpk, the control circuit 42 turns off the input voltage ground state Vin_Gnd and starts the input voltage output state Vin_Vout (step 628), and starts the next cycle according to the trigger of the clock signal CLK. In addition, in order to determine the timing of mode switching, when the control circuit 42 detects that the sensing signal Vsen is greater than the peak ramp signal Vpk, it will sample the position of the sensing signal Vsen to the valley ramp signal Vvl in real time. If the sensed signal Vsen is detected to be greater than the valley ramp signal Vvl, the control circuit 42 activates the output voltage ground state Gnd_Vout instead of the input voltage output voltage state Vin_Vout (step 630), indicating that the power conversion device 40 has entered the buck-boost mode. Subsequently, when the sensed signal Vsenv is less than the peak ramp signal Vpk, the input voltage output voltage state Vin_Vout is activated (step 632). The power conversion device 40 skips one clock cycle CLK and maintains the activated input voltage output voltage state Vin_Vout during this period (step 634). After achieving the frequency reduction effect, it enters the next cycle according to the triggering of the clock signal CLK.

[0063] Detailed instructions for operation process 60 can be provided. Figure 5A , Figure 5B By observing the relevant signals, we can gain a more complete understanding.

[0064] It should be noted that, Figure 4 The power conversion device 40 is an embodiment of this utility model. Those skilled in the art can make various modifications accordingly, and are not limited thereto. For example, please refer to... Figure 7A , Figure 7AThis is a schematic diagram of a power conversion device 70 according to an embodiment of the present invention. The power conversion device 70 is derived from the power conversion device 40; therefore, identical components are represented by the same symbols. A control circuit 72 of the power conversion device 70 includes an error amplification module 720, a valley ramp signal generation module 722, a peak ramp signal generation module 724, a comparator module 726, a driver module 728, and a mode selection module 730, which respectively implement the error amplification module 420, valley ramp signal generation module 422, peak ramp signal generation module 424, comparator module 426, driver module 428, and mode selection module 430 of the control circuit 42. Detailed operation can be found in the foregoing description. The error amplification module 720 includes an error amplifier EA, resistors R1 to R3, a capacitor C1, and a reference voltage generator Vref. The valley ramp signal generation module 722 includes a ramp generation circuit 7220, an adder 7222, a ramp control circuit 7224, and a voltage-to-current converter 7226. The peak ramp signal generation module 724 includes a ramp generation circuit 7240, an adder 7242, a ramp control circuit 7244, and a voltage-to-current converter 7246. The ramp generation circuit 7220 and the voltage-to-current converter 7226 implement the ramp generator 4220. The ramp control circuit 7224 implements the ramp control circuit 4224, controlling the ramp generation circuit 7220 to add an offset signal at the appropriate time via the voltage-to-current converter 7226. The ramp generator 7220 also generates a clock signal based on the clock signal CLK_BU, thus allowing the ramp generator 7220 to skip the clock signal (details can be found in the preceding description). Similarly, the ramp generation circuit 7240 and the voltage-to-current converter 7246 are used to implement the ramp generator 4240, and the ramp control circuit 7244 is used to implement the ramp control circuit 4244. It is used to control the ramp generation circuit 7240 to add an offset signal in a timely manner through the voltage-to-current converter 7246. The ramp generator 7240 also generates a clock signal according to the clock signal CLK_BO, so it can control the ramp generator 7220 to skip the clock (for details, please refer to the above description). For example, the ramp control circuit 7224 can compare the duty cycle of the input voltage ground state Vin_Gnd with the minimum fixed duty cycle Dmin, and output a control signal CT_BU in a timely manner to control the voltage-to-current converter 7226 to convert a voltage Vir into a current Iref, thereby changing the level of the ramp signal generated by the ramp generation circuit 7220. Similarly, the ramp control circuit 7244 can compare the duty cycle of the output voltage ground state Gnd_Vout with the minimum fixed duty cycle Dmin, and output a control signal CT_BO in a timely manner to control the voltage-to-current converter 7246 to convert a voltage Vir into a current Iref, thereby changing the level of the ramp signal generated by the ramp generation circuit 7240. Please refer to [further details omitted]. Figure 7B , Figure 7B This is a schematic diagram of a voltage-to-current converter. Figure 7B The voltage-to-current converters 7226 and 7246 are used to convert voltage Vir into current Iref. Adder 7222 is used to implement adder 4222, adding the ramp signal generated by ramp generation circuit 7220 to the error amplification signal Vea to generate a valley ramp signal Vvl. Similarly, adder 7242 is used to implement adder 4242, adding the ramp signal generated by ramp generation circuit 7240 to the error amplification signal Vea to generate a peak ramp signal Vpk.

[0065] Comparator module 726 consists of comparators CMP1 and CMP2. One input terminal of comparator CMP1 (e.g., positive input terminal (+)) receives a sensing signal Vsen from low-side current sensing module 12, and its other input terminal (e.g., negative input terminal (-)) receives a valley ramp signal Vvl from valley ramp signal generation module 722. One input terminal of comparator CMP2 (e.g., positive input terminal (+)) receives a sensing signal Vsen from low-side current sensing module 12, and its other input terminal (e.g., negative input terminal (-)) receives a peak ramp signal Vpk from peak ramp signal generation module 724. Driver module 728 consists of a pulse width signal generator 7280 and D-type flip-flops 7282 and 7284.

[0066] In addition, those skilled in the art can make various modifications to suit specific application requirements or implementation methods. For example, the switching elements SW1 to SW4 can be MOSFETs, BJTs, or IGBTs, and their selection can be based on the power requirements of the power conversion device, switching frequency, or cost considerations. The inductor L can be an air-core inductor or an iron-core inductor, and can be adjusted according to the required inductance value and current capacity. The resistor Rsen in the low-side current sensing module 12 can be replaced with a Hall effect sensor or a current transformer to improve the accuracy of current sensing or reduce power consumption. The implementation of the control circuits 14, 42, or 72 is not limited to a single chip-built-in logic circuit; they can be separated into discrete component combinations or integrated into a microcontroller (MCU) and digital signal processor (DSP) to further implement more complex control algorithms. Furthermore, the ramp generators 4220 and 4240 in the valley ramp signal generation module 422 and the peak ramp signal generation module 424 can use analog circuits to generate sawtooth waves or generate pulse width modulation (PWM) signals digitally to adapt to the needs of different device architectures. These changes do not depart from the core spirit of this utility model and can be flexibly adjusted according to actual application scenarios.

[0067] Furthermore, although the aforementioned description identifies the mode indication signals BU and BO as different signals, they can be different levels of the same signal. For example, a high level (e.g., logic 1) of a single mode indication signal can represent buck mode, and a low level (e.g., logic 0) can represent boost mode, simplifying the design of the control circuit. The generation of the valley ramp signal Vvl and the peak ramp signal Vpk is not limited to an analog ramp generator; it can also be achieved using a digital counter paired with a digital-to-analog converter (DAC), with its slope or offset dynamically adjusted according to the clock signal CLK. In addition, the error amplification signal Vea can be further filtered to reduce the impact of high-frequency noise on the control loop, or its gain value can be adjusted according to application requirements. These signal-related derivative variations can all be adjusted and implemented by those skilled in the art according to device performance requirements or hardware limitations, without departing from the technical scope of this utility model.

[0068] on the other hand, Figure 4 The operation of the power conversion device 40 can be summarized as a control process 80, such as... Figure 8 As shown. Control flow 80 includes the following steps:

[0069] Step 800: Begin.

[0070] Step 802: When the switching elements SW1 to SW4 are operating in the input voltage ground state Vin_Gnd and the output voltage ground state Gnd_Vout, the current between the third node N3 and the ground terminal Gnd is sensed, and a sensing signal Vsen is generated.

[0071] Step 804: Based on the sensing signal Vsen, the operating cycle of the input voltage ground state Vin_Gnd, and the operating cycle of the output voltage ground state Gnd_Vout, dynamically switch the switching elements SW1 to SW4 to operate in a boost mode, a buck mode, and a buck-boost mode to control the switching elements SW1 to SW4 to convert the input voltage Vin into an output voltage Vout with a target voltage value; wherein, in the buck-boost mode, the switching elements SW1 to SW4 are controlled to periodically operate in the input voltage ground state Vin_Gnd, the output voltage ground state Gnd_Vout, and the input voltage output voltage state Vin_Vout, and are controlled to extend the operating cycle of the input voltage ground state Vin_Gnd or the output voltage ground state Gnd_Vout.

[0072] Step 806: End.

[0073] For detailed instructions on the operation of control process 80, please refer to the foregoing description. They will not be repeated here.

[0074] As described above, this invention effectively overcomes the limitation of the minimum working cycle, improves device efficiency, and reduces switching losses by dynamically adjusting the levels of the valley ramp signal Vvl and the peak ramp signal Vpk, while simultaneously achieving smooth mode transitions. For example, please refer to... Figure 9A , Figure 9B , Figure 9A , Figure 9B This is a schematic diagram comparing inductor currents. Figure 9A When the power conversion device switches from buck mode to buck-boost mode, the change in inductor current with and without the extended duty cycle mechanism of this invention can correspond to... Figure 5A The solid curve 90 represents the inductor current change when the extended duty cycle mechanism of this invention is used, while the dashed curve 92 represents the inductor current change when the extended duty cycle mechanism of this invention is not used. A comparison shows that when the power conversion device switches from buck mode to buck-boost mode, the inductor current change is smoother under the extended duty cycle mechanism of this invention, thus achieving a smooth transition between modes. Similarly, Figure 9B When the power conversion device switches from boost mode to buck-boost mode, the change in inductor current with and without the extended duty cycle mechanism of this invention can correspond to... Figure 5B In the figure, solid curve 94 represents the inductor current change when the extended duty cycle mechanism of this invention is adopted, while dashed curve 96 represents the inductor current change when the extended duty cycle mechanism of this invention is not adopted. The comparison shows that when the power conversion device switches from boost mode to buck-boost mode, the inductor current change is smoother under the extended duty cycle mechanism of this invention, thus achieving a smooth transition between modes.

[0075] In existing technologies, power conversion devices often suffer from reduced voltage conversion efficiency, increased switching losses, and even electromagnetic interference when switching between buck, boost, and buck-boost modes due to the limitation of the minimum duty cycle, making it difficult to achieve smooth mode transitions and stable output voltage. In contrast, this invention overcomes the minimum duty cycle limitation by dynamically adjusting the levels of the valley ramp signal and the peak ramp signal, extending the duty cycle of the input voltage grounding state or output voltage grounding state as needed, and combining this with a reduction in operating frequency. This improves device efficiency, reduces switching losses, and simultaneously achieves smooth mode transitions.

[0076] In summary, this utility model provides a highly efficient and stable power conversion device and its control method. Through a low-side current sensing architecture and an innovative control mechanism, it not only maintains the stability of the output voltage but also reduces electromagnetic interference and device losses. It is suitable for various application scenarios with different input and output voltage requirements and has significant technical advantages and practical value.

Claims

1. A power conversion device, characterized in that, Include: One input terminal is used to receive an input voltage; One output terminal is used to provide an output voltage; A first switching element, a second switching element, a third switching element, and a fourth switching element are provided. The first switching element is connected to the input terminal and the second switching element. The second switching element is connected to the third switching element. The fourth switching element is connected to the third switching element and the output terminal. The connection between the first switching element and the second switching element forms a first node. The connection between the third switching element and the fourth switching element forms a second node. The connection between the second switching element and the third switching element forms a third node. An inductor is connected between the first node and the second node; A low-side current sensing module is disposed between the third node and a ground terminal to sense the current between the third node and the ground terminal and generate a sensing signal when the first to fourth switching elements are operating in an input voltage ground state and an output voltage ground state. as well as A control circuit, coupled to the low-side current sensing module, the output terminal, and the first to fourth switching elements, is used to dynamically switch the first to fourth switching elements to operate in a boost mode, a buck mode, and a buck-boost mode according to the sensing signal, the duty cycle of the input voltage ground state, and the duty cycle of the output voltage ground state, so as to control the first to fourth switching elements to convert the input voltage into the output voltage having a target voltage value; In the buck-boost mode, the control circuit controls the first to fourth switching elements to operate periodically in the input voltage ground state, the output voltage ground state, and an input voltage output voltage state, and extends the working cycle of the input voltage ground state or the output voltage ground state.

2. The power conversion device according to claim 1, characterized in that, The control circuit includes: An error amplifier module is used to generate an error amplification signal based on the output voltage; A valley ramp signal generation module is used to generate a valley ramp signal based on the error amplification signal, the working cycle of the input voltage grounding state, and a mode indication signal. A peak ramp signal generation module is used to generate a peak ramp signal based on the error amplification signal, the working cycle of the output voltage ground state, and the mode indication signal. A comparator module, coupled to the low-side current sensing module, the valley ramp signal generation module and the peak ramp signal generation module, is used to compare the sensing signal with the valley ramp signal to generate a valley comparison result, and to compare the sensing signal with the peak ramp signal to generate a peak comparison result. A drive module, coupled to the comparator module and the first to fourth switching elements, is used to control the on or off of the first to fourth switching elements based on the valley comparison result and the peak comparison result; and A mode selection module is used to generate a mode indication signal based on the working cycle of the input voltage ground state, the working cycle of the output voltage ground state, the valley comparison result, and the peak comparison result.

3. The power conversion device according to claim 2, characterized in that, The valley ramp signal generation module includes: A ramp generator is used to generate a ramp signal; An adder, coupled to the ramp generator, the error amplification module, and the comparator module, is used to add the ramp signal to the error amplification signal to generate the valley ramp signal, and output it to the comparator module; and A ramp control circuit, coupled to the ramp generator and the mode selection module, is used to control the ramp generator to add an offset signal to the ramp signal when the mode indication signal indicates a switch from the buck mode to the boost mode, so as to reduce the level of the valley ramp signal and extend the working cycle of the output voltage ground state.

4. The power conversion device according to claim 3, characterized in that, In buck mode, when the duty cycle of the output voltage ground state reaches a minimum fixed duty cycle and the valley comparison result and the peak comparison result show that the sensed signal is between the valley ramp signal and the peak ramp signal, the mode selection module changes the mode indicator signal from indicating buck mode to indicating boost mode.

5. The power conversion device according to claim 4, characterized in that, The mode indicator signal indicates a switch from the boost mode to the buck mode, and the duty cycle of the input voltage ground state reaches the minimum fixed duty cycle. The ramp control circuit can control the ramp generator to remove the offset signal from the ramp signal to restore the level of the valley ramp signal.

6. The power conversion device according to claim 3, characterized in that, The ramp generator generates the ramp signal based on a clock signal. The ramp control circuit is further used to control the ramp generator to periodically skip at least one clock cycle of the clock signal when the mode indication signal indicates a switch from the buck mode to the boost mode, so as to reduce the switching frequency of the input voltage ground state, the output voltage ground state and the input voltage output voltage state.

7. The power conversion device according to claim 2, characterized in that, The peak ramp signal generation module includes: A ramp generator is used to generate a ramp signal; An adder, coupled to the ramp generator, the error amplification module, and the comparator module, is used to add the ramp signal to the error amplification signal to generate the peak ramp signal, and output it to the comparator module; and A ramp control circuit, coupled to the ramp generator and the mode selection module, is used to control the ramp generator to add an offset signal to the ramp signal when the mode indication signal indicates a switch from the boost mode to the buck mode, thereby increasing the level of the peak ramp signal and extending the working cycle of the input voltage ground state.

8. The power conversion device according to claim 7, characterized in that, In the boost mode, when the duty cycle of the input voltage ground state reaches a minimum fixed duty cycle and the valley comparison result and the peak comparison result show that the sensed signal is between the valley ramp signal and the peak ramp signal, the mode selection module changes the mode indication signal from indicating the boost mode to indicating the buck mode.

9. The power conversion device according to claim 8, characterized in that, The mode indicator signal indicates a switch from the buck mode to the boost mode, and the duty cycle of the output voltage ground state reaches the minimum fixed duty cycle. The ramp control circuit can control the ramp generator to remove the offset signal from the ramp signal to restore the level of the peak ramp signal.

10. The power conversion device according to claim 7, characterized in that, The ramp generator generates the ramp signal based on a clock signal. The ramp control circuit is further used to control the ramp generator to periodically skip at least one clock cycle of the clock signal when the mode indication signal indicates a switch from the boost mode to the buck mode, so as to reduce the switching frequency of the input voltage ground state, the output voltage ground state, and the input voltage output voltage state.

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