Switching module for a high-reliability clock synchronization system
Through redundant design and multi-protocol support, the highly reliable clock synchronization system solves the problem of synchronization failure caused by a single clock source, achieving synchronization accuracy from nanosecond to millisecond level, adaptability, and anti-interference capability, meeting the clock synchronization needs of different scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU HENGQING KEXUN TECHNOLOGY CO LTD
- Filing Date
- 2025-06-09
- Publication Date
- 2026-06-02
AI Technical Summary
In existing clock synchronization systems, the reliance on a single clock source makes system synchronization susceptible to failure, unable to achieve millisecond-level switching, and vulnerable to electromagnetic interference, failing to meet the accuracy requirements of different scenarios.
The high-reliability clock synchronization system with redundant design integrates a master clock and a backup clock, supports IEEE 1588 (PTP), NTP, 1PPS+TOD and ARINC429 protocols, achieves nanosecond-level synchronization through the PTP unit built into the switching chip, and achieves millisecond-level synchronization by combining with the NTP server, and optimizes the signal path to reduce electromagnetic interference.
It significantly reduces the risk of single point of failure, improves the system's fault tolerance, adaptability, and accuracy, meets the synchronization requirements of different scenarios, and reduces the impact of electromagnetic interference on clock signals.
Smart Images
Figure CN224319371U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of communication equipment technology, specifically relating to a switching module for a high-reliability clock synchronization system. Background Technology
[0002] In distributed systems, communication networks, and the Internet of Things (IoT), clock synchronization is a key technology for ensuring system reliability and data consistency. With the rapid development of information technology, the demands for time accuracy in collaborative work between various devices are increasing. For example, financial trading systems rely on microsecond-level timestamps to avoid conflicts, 5G communication requires nanosecond-level synchronization to achieve ultra-low latency, and the collaborative control of multi-axis robotic arms in industrial automation also depends on high-precision clock alignment. Clock discrepancies between devices can lead to data corruption or even system-wide failures.
[0003] In traditional clock synchronization schemes, Network Time Protocol (NTP) achieves millisecond-level accuracy through hierarchical time servers and is widely used in Internet scenarios. Precision Time Protocol (PTP / IEEE 1588) utilizes hardware timestamps and a master-slave clock architecture to improve accuracy to sub-microsecond levels, becoming a core solution in industrial Ethernet and telecommunications fields.
[0004] Even so, existing time synchronization switching modules still rely on a single clock source (such as the PTP master clock), which will cause system synchronization interruption if it fails; cannot achieve millisecond-level switching; and are susceptible to electromagnetic interference or hardware damage.
[0005] Therefore, to address the aforementioned technical issues, it is necessary to provide a switching module for a highly reliable clock synchronization system.
[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0007] The purpose of this invention is to provide a switching module for a high-reliability clock synchronization system, which can significantly reduce the risk of single-point failure, avoid synchronization failure due to single-path failure, meet the accuracy requirements of different scenarios, and improve the adaptability of the switching module.
[0008] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:
[0009] In a first aspect, this utility model provides a switching module for a high-reliability clock synchronization system, characterized in that it includes:
[0010] A signal processing module, comprising a receiving unit and a processing unit; the input terminal of the processing unit is connected to the output terminal of the receiving unit, and is used to perform level conversion on the time signal received by the receiving unit and determine the transmission path of the next hop of the time signal;
[0011] The PTP clock module has its input terminal connected to one output terminal of the processing unit to receive the time signal after level conversion.
[0012] A switching chip, one input terminal of which is connected to the output terminal of the PTP clock module via a PHY chip, and the other input terminal of which is connected to the other output terminal of the processing unit, is used for PTP clock synchronization based on the time signal after level conversion.
[0013] In one or more embodiments of this utility model, the PTP clock module integrates an NTP server.
[0014] In one or more embodiments of this utility model, the signal processing module includes a first signal processing module for receiving and processing 1PPS signals and a second signal processing module for receiving and processing TOD signals; the first signal processing module and the second signal processing module respectively form multiple independent time signal transmission links with the PTP clock module and the switching chip.
[0015] In one or more embodiments of this utility model, the receiving unit includes a first receiving unit and a second receiving unit, and the processing unit includes a first processing unit and a second processing unit;
[0016] The first signal processing module includes a first receiving unit and a first processing unit; the input terminal of the first processing unit is connected to the output terminal of the first receiving unit, and is used to perform level conversion on the 1PPS signal received by the first receiving unit and determine the transmission path of the next hop of the 1PPS signal.
[0017] The second signal processing module includes a second receiving unit and a second processing unit; the input terminal of the second processing unit is connected to the output terminal of the second receiving unit, and is used to perform level conversion on the TOD signal received by the second receiving unit and determine the transmission path of the next hop of the TOD signal.
[0018] In one or more embodiments of this utility model, the first processing unit is a CPLD; the second processing unit is an FPGA.
[0019] In one or more embodiments of this utility model, the first receiving unit is an RS422 receiver and the second receiving unit is an ARINC429 receiver.
[0020] In one or more embodiments of this utility model, the PTP clock module is configured with an SGMII interface and communicates with the PHY chip based on the SGMII interface.
[0021] The PHY chip communicates with the switching chip based on a preset Ethernet standard, enabling the switching chip to access the PTP clock module based on the PHY chip.
[0022] In one or more embodiments of this utility model, the processing unit is connected to the PTP clock module via differential line communication; the processing unit is connected to the switching chip via single-ended line communication.
[0023] In one or more embodiments of this utility model, the switching module further includes:
[0024] A VPX connector is used to receive an external clock signal and forward the external clock to the signal processing module.
[0025] In one or more embodiments of this utility model, the input end of the VPX connector is connected to the peer VPX module that emits the time signal.
[0026] Compared with existing technologies, the switching module of the high-reliability clock synchronization system provided by this invention significantly reduces the risk of single-point failure through redundant design of the master clock and backup clock. It simultaneously supports IEEE 1588 (PTP), NTP, 1PPS+TOD, and ARINC429 protocols, adapting to heterogeneous network environments. The master clock preferentially uses the PTP protocol, while the backup clock uses the NTP protocol; the two complement each other to improve system fault tolerance. Nanosecond-level synchronization is achieved based on the PTP unit built into the switching chip, meeting the high-precision requirements of aerospace, military communications, and other scenarios. Millisecond-level synchronization is achieved based on the NTP server built into the PTP clock module, meeting the synchronization requirements of lower precision applications. Furthermore, this invention, based on level-optimized signal paths, can also reduce the impact of electromagnetic interference on the clock signal. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic block diagram of the switching module of a high-reliability clock synchronization system in one embodiment of the present invention. Detailed Implementation
[0029] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.
[0030] This invention provides a switching module for a high-reliability clock synchronization system. Specifically, it includes a signal processing module, a PTP clock module, and a switching chip.
[0031] The signal processing module includes a receiving unit and a processing unit. Specifically, the input terminal of the processing unit is connected to the output terminal of the receiving unit. The receiving unit receives a time signal from the previous-level device / module for time synchronization within this switching module. The processing module performs level conversion on the time signal received by the receiving unit and determines the next-hop transmission path of the time signal.
[0032] It should be noted that this invention simultaneously supports IEEE 1588 (PTP), NTP, 1PPS+TOD, and ARINC429 protocols, adapting to heterogeneous network environments. Therefore, this invention does not impose restrictions on the time signal sent from the upstream, as long as the switching module can perform time synchronization based on the time signal. When the time signal is a combination of multiple signals, the number of signals corresponding to the time processing module should form multiple independent transmission paths.
[0033] like Figure 1 The image shows an exemplary embodiment of the present invention. In this exemplary embodiment, the signal processing module includes a first signal processing module for receiving and processing 1PPS signals and a second signal processing module for receiving and processing TOD signals; the first signal processing module and the second signal processing module respectively form two independent time signal transmission links with the PTP clock module and the switching chip.
[0034] Furthermore, the receiving unit includes a first receiving unit and a second receiving unit, and the processing unit includes a first processing unit and a second processing unit; the first signal processing module includes a first receiving unit and a first processing unit; the input terminal of the first processing unit is connected to the output terminal of the first receiving unit, and is used to perform level conversion on the 1PPS signal received by the first receiving unit, and determine the transmission path of the next hop of the 1PPS signal; the second signal processing module includes a second receiving unit and a second processing unit; the input terminal of the second processing unit is connected to the output terminal of the second receiving unit, and is used to perform level conversion on the TOD signal received by the second receiving unit, and determine the transmission path of the next hop of the TOD signal.
[0035] It is understood that the receiving unit and the processing unit can simply receive, forward, and convert the time signal. In the embodiments of this utility model, there are no restrictions on the specific selection of the receiving unit (first receiving unit and / or second receiving unit) and the processing unit (first processing unit and / or second processing unit). Since 1PPS is a precise timing signal, one pulse per second, it is used to provide a high-precision time reference point. TOD provides the current absolute time information, such as year, month, day, hour, minute, and second, and is usually transmitted via a serial port or other interface. Preferably, the first processing unit is a CPLD; the second processing unit is an FPGA; the first receiving unit is an RS422 receiver, and the second receiving unit is an ARINC429 receiver.
[0036] In this invention, the processing unit, in addition to performing functions such as time signal level conversion, determining the next-hop transmission path, and switching paths, can also achieve status monitoring and seamless switching through user-defined configurations.
[0037] In embodiments of this invention, the level conversion can be a conversion from traditional 5V TTL to 3.3V LVTTL. Dynamic power consumption is proportional to the square of the voltage; therefore, this level conversion by the processing unit can reduce transmission power consumption to some extent. Similarly, level conversion allows the synchronization system to adapt to a wider range of low-voltage devices, avoids multi-stage level conversion, and simplifies circuit design. Lower voltage swing reduces the electric field strength during signal transitions. LVTTL has a higher noise margin than traditional 5V TTL, and LVTTL is typically designed with moderate rise / fall times to avoid high-frequency harmonics (caused by excessively fast edges), reducing high-frequency noise on the signal path and minimizing signal path interference.
[0038] The switching chip of this invention has a built-in PTP unit, which can achieve nanosecond-level clock synchronization in conjunction with the level-converted time signal. To achieve this function, in terms of architecture, one input terminal of the switching chip is connected to one output terminal of the processing unit for PTP clock synchronization based on the level-converted time signal.
[0039] It is understandable that if there are multiple signal processing modules and multiple independent time signal transmission links are formed based on them, the output terminal of the processing module corresponding to each signal link should be connected to one input terminal of the switching chip so that the switching chip can completely receive the processed time signal from upstream for time synchronization.
[0040] Continue to use Figure 1 The embodiment shown. The output terminals of the first processing unit for processing the upstream 1PPS signal and the second processing unit for processing the upstream TOD signal should be connected to the input terminals of the switching chip, respectively, so that the switching chip can achieve clock synchronization based on the processed 1PPS+TOD signal.
[0041] The PTP clock module of this invention provides a new time synchronization link, which, in conjunction with the switching chip, reduces the risk of single point of failure. To achieve the above function, the PTP clock module of this invention integrates an NTP server. By receiving and processing the time signal, the switching chip can communicate with the PTP clock module, thus adding the function of a built-in NTP server to the existing time synchronization system, thereby enabling NTP clock synchronization.
[0042] Based on this, in terms of architecture, the input terminal of the PTP clock module needs to be connected to one of the output terminals of the processing unit to receive the time signal after level conversion; the output terminal of the PTP clock module is connected to the switching chip through a PHY chip to transmit the PTP clock signal to the switching chip for time synchronization.
[0043] Specifically, the output of the PTP clock module is equipped with an SGMII interface and communicates with the PHY chip based on the SGMII interface; the PHY chip communicates with the switching chip based on a preset Ethernet standard, so that the switching chip can access the PTP clock module based on the PHY chip.
[0044] Similar to the connection relationship between the aforementioned switching chip and processing unit, if there are multiple signal processing modules and multiple independent time signal transmission links are formed based on them, then the output terminal of the processing module corresponding to each signal link should be connected to one input terminal of the PTP clock module so that the PTP clock module can completely receive the processed time signal from upstream for time synchronization.
[0045] It should also be noted that the communication connection method between modules / units is not limited in the embodiments of this utility model. The communication connection only needs to meet the stable transmission of the corresponding signal under specific conditions. Preferably, to ensure the stability of signal transmission, the processing unit and the PTP clock module are connected via differential lines; the processing unit and the switching chip are connected via single-ended lines. Single-ended lines transmit using only one signal line, simplifying wiring and performing well in short-distance data transmission; differential lines transmit through a pair of signal lines with opposite phases (positive and negative ends), and the receiving end restores the signal through the difference. The impedance matching and symmetry design effectively suppress crosstalk and reflection, providing higher anti-interference capability and higher signal integrity.
[0046] Furthermore, the switching module of the high-reliability clock synchronization system provided by this invention also includes a VPX connector, which is used to receive external clock signals and forward the external clock signals to each of the signal processing modules. The input end of the VPX connector is connected to the VPX connector at the other end that sends the time signal.
[0047] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0048] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A switching module for a high-reliability clock synchronization system, characterized in that, include: A signal processing module, comprising a receiving unit and a processing unit; The input terminal of the processing unit is connected to the output terminal of the receiving unit, and is used to perform level conversion on the time signal received by the receiving unit and determine the transmission path of the next hop of the time signal. The PTP clock module has its input terminal connected to one output terminal of the processing unit to receive the time signal after level conversion. A switching chip, one input terminal of which is connected to the output terminal of the PTP clock module via a PHY chip, and the other input terminal of which is connected to the other output terminal of the processing unit, is used for PTP clock synchronization based on the time signal after level conversion.
2. The switching module of the high-reliability clock synchronization system according to claim 1, characterized in that, The PTP clock module integrates an NTP server.
3. The switching module of the high-reliability clock synchronization system according to claim 2, characterized in that, The signal processing module includes a first signal processing module for receiving and processing 1PPS signals and a second signal processing module for receiving and processing TOD signals; the first signal processing module and the second signal processing module respectively form multiple independent time signal transmission links with the PTP clock module and the switching chip.
4. The switching module of the high-reliability clock synchronization system according to claim 3, characterized in that, The receiving unit includes a first receiving unit and a second receiving unit, and the processing unit includes a first processing unit and a second processing unit; The first signal processing module includes a first receiving unit and a first processing unit; the input terminal of the first processing unit is connected to the output terminal of the first receiving unit, and is used to perform level conversion on the 1PPS signal received by the first receiving unit and determine the transmission path of the next hop of the 1PPS signal. The second signal processing module includes a second receiving unit and a second processing unit; the input terminal of the second processing unit is connected to the output terminal of the second receiving unit, and is used to perform level conversion on the TOD signal received by the second receiving unit and determine the transmission path of the next hop of the TOD signal.
5. The switching module of the high-reliability clock synchronization system according to claim 4, characterized in that, The first processing unit is a CPLD; the second processing unit is an FPGA.
6. The switching module of the high-reliability clock synchronization system according to claim 4, characterized in that, The first receiving unit is an RS422 receiver, and the second receiving unit is an ARINC429 receiver.
7. The switching module of the high-reliability clock synchronization system according to claim 3, characterized in that, The PTP clock module is equipped with an SGMII interface and communicates with the PHY chip based on the SGMII interface. The PHY chip communicates with the switching chip based on a preset Ethernet standard, enabling the switching chip to access the PTP clock module based on the PHY chip.
8. The switching module of the high-reliability clock synchronization system according to claim 3, characterized in that, The processing unit is connected to the PTP clock module via differential lines; the processing unit is connected to the switching chip via single-ended lines.
9. The switching module of the high-reliability clock synchronization system according to claim 3, characterized in that, The switching module further includes: A VPX connector is used to receive an external clock signal and forward the external clock to the signal processing module.
10. The switching module of the high-reliability clock synchronization system according to claim 9, characterized in that, The input end of the VPX connector is connected to the other end of the VPX connector that emits the time signal.