A solar display screen trailer

Abstract

The utility model discloses a solar display screen trailer, including car body and setting solar charging device, display screen, energy storage power supply and main control unit on the car body, solar charging device is connected with energy storage power supply electricity respectively, solar charging device with energy storage power supply all with main control unit electricity is connected, main control unit includes processor and power saving adjustment module, processor with display screen driver in display screen electricity is connected, power saving adjustment module is connected with display screen driver electricity, is used for controlling the power supply state of display drive chip in display screen driver, processor with power saving adjustment module electricity is connected, is used for controlling power saving adjustment module work. The utility model can adjust the power supply state of different display drive chip according to the display condition in real time, thereby saves energy consumption, reduces display screen power consumption, improves the endurance performance.

Description

Technical Field

[0001] This utility model relates to the field of display screen trailer technology, and in particular to a solar display screen trailer. Background Technology

[0002] With the increasing maturity of LED technology, the application of outdoor or portable displays is becoming more and more widespread, such as directional displays in municipal, traffic, advertising, and disaster relief scenarios, as well as decorations and background displays for large-scale outdoor celebrations, parties, and weddings. Outdoor solar-powered LED trailers, with their unique flexibility and convenience, can be used for advertising anytime, anywhere, and content can be updated promptly. Utilizing solar power, they are both convenient and cost-effective in terms of operating.

[0003] Traditional display trailers typically rely on external power sources for their displays. These external power sources are connected to the display trailer via power lines and sockets. However, if the power lines are long, the energy consumption is relatively high, and there are certain safety hazards. Furthermore, this limits the scope of use and increases operating costs.

[0004] Currently, some display trailers power the displays by installing solar panels and energy storage power supplies. However, the displays consume relatively high power. The aforementioned display trailers do not have corresponding power-saving circuits, resulting in high overall power consumption, which affects the display's battery life and cannot meet users' high battery life requirements, especially when users need to be in a sunless environment for a long time. Therefore, their practicality is low. Utility Model Content

[0005] The technical problem to be solved by this utility model is to provide a solar display trailer that can adjust the power supply status of different display driver chips in real time according to the display situation, thereby saving energy, reducing the power consumption of the display screen, and improving the battery life.

[0006] To address the aforementioned technical problems, this utility model provides a solar display trailer, comprising a vehicle body and a solar charging device, a display screen, an energy storage power supply, and a main controller mounted on the vehicle body. The solar charging device is electrically connected to the energy storage power supply, and both the solar charging device and the energy storage power supply are electrically connected to the main controller. The main controller includes a processor and a power-saving adjustment module. The processor is electrically connected to the display screen driver in the display screen. The power-saving adjustment module is electrically connected to the display screen driver and is used to control the power supply status of the display driver chip in the display screen driver. The processor is electrically connected to the power-saving adjustment module and is used to control the operation of the power-saving adjustment module.

[0007] As an improvement to the above solution, the power-saving adjustment module includes a control circuit and a switch adjustment circuit. The display driver includes an R-color display driver chip, a G-color display driver chip, and a B-color display driver chip. The switch adjustment circuit is electrically connected to the power supply terminals of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip, respectively, and is used to control the power supply status of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip, respectively. The control circuit is electrically connected to the processor and the switch adjustment circuit, respectively, and is used to receive control data sent by the processor and control the switching operation status of the switch adjustment circuit according to the control data.

[0008] As an improvement to the above solution, the solar charging device includes multiple solar panels connected in series and an MPPT solar controller. The input terminal of the MPPT solar controller is connected to the solar panels, and the output terminal of the MPPT solar controller is electrically connected to the energy storage power supply and the main controller, respectively.

[0009] As an improvement to the above solution, the vehicle body is equipped with a hydraulic lifting device electrically connected to the main controller, and the drive end of the hydraulic lifting device is connected to the display screen; the display screen is equipped with at least one photoelectric sensor, and the photoelectric sensor is electrically connected to the processor.

[0010] As an improvement to the above solution, the control circuit includes a clock state control circuit, a display state control circuit, and a power-saving processing circuit. The clock state control circuit is electrically connected to both the processor and the display state control circuit, and is used to perform clock validity determination processing based on the clock signal input by the processor, and output a clock state control signal to the display state control circuit. The display state control circuit is electrically connected to both the processor and the power-saving processing circuit, and is used to perform display validity determination processing based on the display signal input by the processor and the clock state control signal, and output a display state control signal to the power-saving processing circuit. The power-saving processing circuit is electrically connected to both the processor and the switch adjustment circuit, and is used to control the switching operation state of the switch adjustment circuit based on the power-saving switch signal input by the processor and the display state control signal.

[0011] As an improvement to the above solution, the clock state control circuit includes a clock judgment chip, a capacitor, and a first resistor. The clock judgment chip includes a first edge-triggered input pin, a second edge-triggered input pin, a first positive output pin, a first inverted output pin, a timing capacitor pin, and a timing resistor pin. The first edge-triggered input pin is electrically connected to the first clock output pin of the processor, the second edge-triggered input pin is electrically connected to the power supply voltage, the first positive output pin and the inverted output pin are both connected to the display state control circuit, the timing capacitor pin is electrically connected to the power supply voltage via the capacitor and the first resistor, and the timing resistor pin is electrically connected to the power supply voltage via the first resistor.

[0012] As an improvement to the above solution, the display state control circuit includes a first logic gate chip and a first latch chip. The first logic gate chip includes a first logic gate unit, a second logic gate unit, a third logic gate unit, and a fourth logic gate unit. The first input pin of the first logic gate unit, the first input pin of the second logic gate unit, and the first input pin of the third logic gate unit are all electrically connected to the first inverting output pin. The second input pin of the first logic gate unit is electrically connected to the first display signal output pin of the processor. The second input pin of the second logic gate unit is electrically connected to the second display signal output pin of the processor. The second input pin of the third logic gate unit is electrically connected to the third display signal output pin of the processor. The output pin of the first logic gate unit is electrically connected to the first set input pin of the first latch chip; the output pin of the second logic gate unit is electrically connected to the second set input pin of the first latch chip; the output pin of the third logic gate unit is electrically connected to the third set input pin of the first latch chip; both input pins of the fourth logic gate unit are grounded; and the output pin of the fourth logic gate unit is left floating. The first reset input pin, the second reset input pin, and the third reset input pin of the first latch chip are electrically connected to the first positive output pin, the enable pin of the first latch chip is electrically connected to the power supply voltage, and all three latch output pins of the first latch chip are electrically connected to the power-saving processing circuit.

[0013] As an improvement to the above solution, the power-saving processing circuit includes a second latch chip and a second logic gate chip. The second logic gate chip includes a fifth logic gate unit, a sixth logic gate unit, a seventh logic gate unit, and an eighth logic gate unit. The display status input pin of the second latch chip is electrically connected to the latch output pin of the first latch chip, and the power-saving status input pin of the second latch chip is electrically connected to the power-saving switch output pin of the processor. The three display status output pins of the second latch chip are respectively connected to the second input pin of the fifth logic gate unit, the second input pin of the sixth logic gate unit, and the first input pin of the seventh logic gate unit. Two input pins are electrically connected. The first input pins of the fifth logic gate unit, the sixth logic gate unit, and the seventh logic gate unit are all electrically connected to the power-saving output pin of the second latch chip. The output pins of the fifth logic gate unit, the sixth logic gate unit, and the seventh logic gate unit are respectively electrically connected to the corresponding control terminals of the switching adjustment circuit. The first input pin of the eighth logic gate unit is electrically connected to the second clock output pin of the processor. The second input pin of the eighth logic gate unit is grounded. The output pin of the eighth logic gate unit is electrically connected to the clock pin of the second latch chip.

[0014] As an improvement to the above solution, the switch adjustment circuit includes a switch control module. The three gate control pins of the switch control module are electrically connected to the corresponding output terminals of the control circuit, the three source pins of the switch control module are electrically connected to the power supply voltage, and the three drain output pins of the switch control module are electrically connected to the power supply terminals of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip, respectively.

[0015] As an improvement to the above solution, the main controller further includes a residual current elimination circuit, which includes a first transistor, a second transistor, and a third transistor. The bases of the first transistor, the second transistor, and the third transistor are electrically connected to the corresponding control output terminals of the control circuit via resistors. The emitters of the first transistor, the second transistor, and the third transistor are all grounded. The collectors of the first transistor, the second transistor, and the third transistor are electrically connected to the corresponding power supply terminals of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip via resistors.

[0016] The present invention has the following beneficial effects;

[0017] This invention can adjust the power supply status of different display driver chips in real time according to the display situation, so as to ensure that the display driver chip that needs to display content is powered on and works stably, and the display driver chip that does not need to display content is powered off, thereby saving energy, reducing the power consumption of the display screen, improving battery life, and meeting the user's demand for long battery life.

[0018] Secondly, the MPPT solar controller can adjust the output power, improving power generation efficiency. Simultaneously, the series-connected solar panels reduce heat loss, further enhancing the range of the solar display trailer. Additionally, the processor can adjust the display screen brightness based on the detection signals from the photoelectric sensor, improving the user viewing experience while reducing power consumption, thus further improving the range of the solar display trailer. Attached Figure Description

[0019] Figure 1 This is a structural schematic diagram of the solar display screen trailer of this utility model;

[0020] Figure 2 This is a schematic diagram of the electrical control structure of the solar display trailer of this utility model;

[0021] Figure 3 This is a schematic diagram of the structure of the solar charging device of this utility model;

[0022] Figure 4 This is a schematic diagram of the control circuit of this utility model;

[0023] Figure 5 This is a schematic diagram of the clock state control circuit of this utility model;

[0024] Figure 6 This is a schematic diagram of the display status control circuit and power-saving processing circuit of this utility model;

[0025] Figure 7 This is a schematic diagram of the switching adjustment circuit of this utility model;

[0026] Figure 8 This is a schematic diagram of the residual current elimination circuit of this utility model. Detailed Implementation

[0027] To make the objectives, technical solutions and advantages of this utility model clearer, the utility model will be described in further detail below with reference to the accompanying drawings.

[0028] like Figure 1 , 2 and Figure 4As shown in the figure, a specific embodiment of this utility model provides a solar display trailer, including a vehicle body 1 and a solar charging device 2, a display screen 3, an energy storage power supply 4 and a main controller 5 installed on the vehicle body 1. The solar charging device 2 is electrically connected to the energy storage power supply 4 to charge the energy storage power supply 4. Both the solar charging device 2 and the energy storage power supply 4 are electrically connected to the main controller 5 to supply power to the electrical components in the main controller 5.

[0029] The main controller 5 includes a processor 51 and a power-saving adjustment module 52. The processor 51 is electrically connected to the display driver 31 in the display screen 3 to enable the display screen 3 to display content. The power-saving adjustment module 52 is electrically connected to the display driver 31 and is used to control the power supply status of the display driver chip in the display driver. The processor 51 is also electrically connected to the power-saving adjustment module 52 and is used to control the operation of the power-saving adjustment module 52. Depending on the display content, the processor 51 can send control data to control the operation of the power-saving adjustment module 52. This power-saving adjustment circuit keeps the display driver chip that needs to display content powered on, while depriving the display driver chip that does not need to display content of power until the desired content is displayed, thus saving energy, reducing the power consumption of the display screen 3, improving battery life, and meeting the user's demand for long battery life.

[0030] The power-saving adjustment module 52 includes a control circuit 6 and a switch adjustment circuit 7. The display driver includes an R-color display driver chip 311, a G-color display driver chip 312, and a B-color display driver chip 313. The switch adjustment circuit 7 is electrically connected to the power supply terminals of the R-color display driver chip 311, G-color display driver chip 312, and B-color display driver chip 313, respectively, and is used to control the power supply status of the R-color display driver chip 311, G-color display driver chip 312, and B-color display driver chip 313. The control circuit 6 is electrically connected to the processor 51 and the switch adjustment circuit 7, respectively, and is used to receive control data sent by the processor 51 and control the switching operation status of the switch adjustment circuit 7 according to the control data.

[0031] For different display content, the control circuit 6 can control the switch adjustment circuit 7 to turn on the power supply circuit of the corresponding display driver chip according to the control data sent by the processor 51, thereby driving the corresponding display driver chip to power on and work, thus realizing the power saving function, improving the endurance performance of the solar display trailer, and meeting the user's high endurance usage needs.

[0032] Furthermore, such as Figures 1 to 3As shown, the solar charging device 2 includes multiple solar panels 21 connected in series and an MPPT solar controller 22. The input terminal of the MPPT solar controller 22 is connected to the solar panels 21, and the output terminal of the MPPT solar controller 22 is electrically connected to the energy storage power supply 4 and the main controller 5, respectively. By using a step-down MPPT controller with a high input voltage, the solar panels 21 can be connected in series. Compared with parallel connection, this reduces the current in the cables and lowers heat loss for the same power generation. Furthermore, the MPPT solar controller 22 can adjust the output power, improving power generation efficiency and further enhancing the range of the solar display trailer.

[0033] When there is sunlight, the MPPT solar controller 22 charges the battery module and supplies power to the various electronic devices in the main controller 5. When there is no sunlight, the energy storage power supply 4 supplies power to the various electronic devices in the main controller 5. Furthermore, the MPPT solar controller 22 automatically enters a sleep mode when the input voltage is lower than the battery voltage of the energy storage power supply 4, during which time power consumption is low. When the input voltage is higher than the battery voltage of the energy storage power supply 4, the MPPT solar controller 22 automatically wakes up and charges the energy storage power supply 4, automatically stopping when fully charged.

[0034] Preferably, the energy storage power supply 4 includes a battery management module and a battery module. The battery module is preferably a lithium iron phosphate battery pack, which is lighter, smaller, and has a longer battery life compared to general battery modules. Moreover, lithium iron phosphate batteries only smoke and do not catch fire, and the battery management module has a battery protection function, thereby greatly improving the safety performance of battery use.

[0035] To enable the display screen 3 to move up and down, the vehicle body 1 is equipped with a hydraulic lifting device 8 electrically connected to the main controller 5. The drive end of the hydraulic lifting device 8 is connected to the display screen 3. When the user needs to move the display screen 3 up and down, they can input a control signal to the processor 51 through the control panel on the vehicle body 1 or a remote control terminal connected to the processor 51. The processor 51 then controls the hydraulic lifting device 8 to drive the display screen 3 to move up and down on the vehicle body 1 to meet the user's needs.

[0036] To further reduce the power consumption of the display screen 3, at least one photoelectric sensor 32 is provided on the display screen 3, and the photoelectric sensor 32 is electrically connected to the processor 51. The photoelectric sensor 32 can detect the ambient brightness around the display screen 3 in real time and send the detection signal to the processor 51. The processor 51 can automatically adjust the brightness of the display screen 3 according to the detection signal, thereby achieving power saving.

[0037] Specifically, the specific circuit structure of the control circuit 6 of this utility model is shown in the figure below:

[0038] like Figure 2 and Figure 4 As shown, the control circuit 6 includes a clock state control circuit 61, a display state control circuit 62, and a power-saving processing circuit 63. The clock state control circuit is electrically connected to the processor 51 and the display state control circuit 62, respectively, and is used to perform clock validity judgment processing based on the clock signal input by the processor 51, and output a clock state control signal to the display state control circuit 62. The display state control circuit 62 is electrically connected to the processor 51 and the power-saving processing circuit 63, respectively, and is used to perform display validity judgment processing based on the display signal input by the processor 51 and the clock state control signal, and output a display state control signal to the power-saving processing circuit 63. The power-saving processing circuit 63 is electrically connected to the processor 51 and the switch adjustment circuit 7, respectively, and is used to control the switching operation state of the switch adjustment circuit 7 based on the power-saving switch signal input by the processor 51 and the display state control signal.

[0039] The display status control signals include R, G, and B color display status control signals. When the power-saving switch signal is valid and the display status control signals are partially valid, the power-saving processing circuit 63 controls the switch adjustment circuit 7 to turn on the power supply circuit of the corresponding display driver chip according to the valid signals, while the invalid signals disconnect the power supply circuit of the corresponding display driver chip. If the power-saving switch signal, R color, and G color display status control signals are valid, but the B display status control signal is invalid, the R color display driver chip 311 and the G color display driver chip 312 are powered on, while the B color display driver chip 313 is powered off. This allows control of the power-on operation of the corresponding display driver chip according to different display content, effectively reducing the power consumption of the display screen 3.

[0040] Preferably, the processor 51 can send a power-saving switch signal to the power-saving processing circuit 63 to activate the power-saving function based on the power-saving control signal input from the control panel or remote terminal.

[0041] like Figure 2 , 4As shown in Figure 5, the clock state control circuit 61 includes a clock judgment chip USP1, a capacitor CPS6, and a first resistor RPS1. The clock judgment chip USP1 includes a first edge-triggered input pin (pin 1), a second edge-triggered input pin (pin 2), a first positive output pin (pin 13), a first inverted output pin (pin 4), a timing capacitor pin (pin 14), and a timing resistor pin (pin 15). The first edge-triggered input pin is electrically connected to the first clock output pin (LAT_B2) of the processor 51, and the second edge-triggered input pin is electrically connected to the power supply voltage VCC. Both the first positive output pin and the inverted output pin are connected to the display state control circuit 62. The timing capacitor pin is electrically connected to the power supply voltage VCC via the capacitor CPS6 and the first resistor RPS1 in sequence, and the timing resistor pin is electrically connected to the power supply voltage VCC via the first resistor RPS1.

[0042] It should be noted that when the processor 51 outputs a display clock signal to the clock judgment chip USP1, the clock judgment chip USP1 determines whether the display clock signal is valid, i.e., whether it is a working clock signal, based on the input display clock signal. When the display clock signal is valid, the first positive output pin and the inverted output pin output a first clock level signal and a first inverted clock level signal to the display state control circuit 62, respectively, so that the display state control circuit 62 can further determine whether the display is working effectively, thereby controlling the corresponding display driver chip to power on or power off.

[0043] Preferably, the processor 51 includes a microcontroller control chip.

[0044] Preferably, the clock detection chip USP1 is a monostable multivibrator, and its chip model is preferably 74HCT123PW, but this is not a limitation.

[0045] like Figure 2 , 4 As shown in Figure 6, the display state control circuit 62 includes a first logic gate chip 621 and a first latch chip UPS2. The first logic gate chip 621 includes a first logic gate unit XPS1A, a second logic gate unit XPS1B, a third logic gate unit XPS1C, and a fourth logic gate unit XPS1D.

[0046] The first input pin of the first logic gate unit XPS1A, the first input pin of the second logic gate unit XPS1B, and the first input pin of the third logic gate unit XPS1C are all electrically connected to the first inverting output pin. The second input pin of the first logic gate unit XPS1A is electrically connected to the first display signal output pin R1_I of the processor 51. The second input pin of the second logic gate unit XPS1B is electrically connected to the second display signal output pin G1_II of the processor 51. The second input pin of the third logic gate unit XPS1C is electrically connected to the third display signal output pin B1_I of the processor 51.

[0047] The output pin of the first logic gate unit XPS1A is electrically connected to the first set input pin (1S) of the first latch chip UPS2; the output pin of the second logic gate unit XPS1B is electrically connected to the second set input pin (2S) of the first latch chip UPS2; the output pin of the third logic gate unit XPS1C is electrically connected to the third set input pin (3S) of the first latch chip UPS2; both input pins of the fourth logic gate unit XPS1D are grounded; and the output pin of the fourth logic gate unit XPS1D is left floating. The first reset input pin (1R), the second reset input pin (2R), and the third reset input pin (3R) of the first latch chip UPS2 are electrically connected to the first positive output pin, the enable pin (OE) of the first latch chip UPS2 is electrically connected to the supply voltage VCC, and the three latch output pins (1Q, 2Q, and 3Q) of the first latch chip UPS2 are all electrically connected to the power saving circuit 63.

[0048] It should be noted that the processor 51 outputs R-color display signals, G-color display signals, and B-color display signals to the first logic gate unit XPS1A, the second logic gate unit XPS1B, and the third logic gate unit XPS1C, respectively. Only when the received corresponding display signal and the first inverse clock signal are both high-level signals does the corresponding logic gate unit output a high-level signal to the first latch chip UPS2, indicating that the display signal is valid; otherwise, it outputs a low-level signal to the first latch. When any set input pin of the first latch chip UPS2 receives a high-level signal and its corresponding first reset input pin receives a low-level first clock signal, it outputs the corresponding R, G, or B-color display status control signal to the power-saving processing circuit 63. This allows the power-saving processing circuit 63 to control the switch adjustment circuit 7 based on the power-saving switch signal and the R, G, and B-color display status control signals.

[0049] Preferably, the first logic gate chip 621 is a four-way two-input positive AND gate logic chip, and its chip model is preferably SN74HC08PWR, but is not limited thereto.

[0050] Preferably, the first latch chip UPS2 is HEF4043BT, but this is not a limitation.

[0051] like Figure 2 , 4 As shown in Figure 6, the power-saving processing circuit 63 includes a second latch chip UPS3 and a second logic gate chip 631. The second logic gate chip 631 includes a fifth logic gate unit XPS2A, a sixth logic gate unit XPS2B, a seventh logic gate unit XPS2C, and an eighth logic gate unit XPS2D.

[0052] The display status input pins (D1, D3, and D5) of the second latch chip UPS3 are electrically connected to the latch output pins (1Q, 2Q, and 3Q) of the first latch chip UPS2, respectively. The power-saving status input pin (D0) of the second latch chip UPS3 is electrically connected to the power-saving switch output pin (POWCTL) of the processor 51. The three display status output pins (Q1, Q3, and Q5) of the second latch chip UPS3 are respectively connected to the second input pin of the fifth logic gate unit XPS2A and the sixth logic gate unit XPS2B. The second input pin of the fifth logic gate unit XPS2A and the second input pin of the seventh logic gate unit XPS2C are electrically connected. The first input pin of the fifth logic gate unit XPS2A, the first input pin of the sixth logic gate unit XPS2B and the first input pin of the seventh logic gate unit XPS2C are all electrically connected to the power-saving output pin (Q0) of the second latch chip UPS3. The output pins of the fifth logic gate unit XPS2A, the sixth logic gate unit XPS2B and the seventh logic gate unit XPS2C are respectively electrically connected to the corresponding control terminals of the switch regulating circuit 7.

[0053] The first input pin of the eighth logic gate unit XPS2D is electrically connected to the second clock output pin of the processor 51, the second input pin of the eighth logic gate unit XPS2D is grounded, and the output pin of the eighth logic gate unit XPS2D is electrically connected to the clock pin (CP) of the second latch chip UPS3.

[0054] It should be noted that the second latch chip UPS3 latches the input power-saving switch signal and the R, G and B color display status control signals and outputs stable signals to the second logic gate chip 631. The power-saving switch signal and the R, G and B color display status control signals are logically processed by multiple logic gate units in the second logic gate chip 631 to obtain the corresponding switch control signals, and thereby control the operation of the switch adjustment circuit 7.

[0055] Preferably, the second logic gate chip 631 is a four-way two-input positive AND gate logic chip, and its chip model is preferably SN74HC02PWR, but not limited thereto.

[0056] Preferably, the second latch chip UPS3 is model SN74HC374PWR, but this is not a limitation.

[0057] like Figure 7 As shown, the switch adjustment circuit 7 includes a switch control module. The three gate control pins of the switch control module (G1 and G2 in SPS3, and G1 in SPS4) are electrically connected to the corresponding output terminals of the power saving circuit. The three source pins of the switch control module (S1 and S2 in SPS3, and S1 in SPS4) are electrically connected to the power supply voltage VCC. The three drain output pins of the switch control module (D1 and D2 in SPS3, and D1 in SPS4) are electrically connected to the power supply terminals (VCC_UR, VCC_UG, and VCC_UB) of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip, respectively.

[0058] It should be noted that the three switch control signals (POWCTL_UR, POWCTL_UG, and POWCTL_UB) output by the power-saving processing circuit in the control circuit can respectively control the power supply status of the R-color display driver chip, G-color display driver chip, and B-color display driver chip. This allows for power-on or power-off control of the corresponding display driver chip based on different display content, thereby achieving power saving and improving the range of the solar display trailer. For example, when the R-color display signal is invalid, its corresponding switch control signal is a high-level signal, the power supply circuit of the corresponding R-color display driver chip is disconnected, the R-color display driver chip is powered off, and the remaining G-color and B-color display driver chips are powered on and operate normally.

[0059] Preferably, the switch control module includes two switch control chips (SPS3 and SPS4), each of which includes two PMOS transistors. The preferred model of the switch control chip is BR4953, but this is not a limitation.

[0060] Because the power-on and power-off process of the display driver chip is very rapid and brief, when the MOSFET in the switching control module is de-energized, it takes the display driver chip a certain amount of time to dissipate the remaining power, which can affect the normal operation of the display driver chip. Therefore, as... Figure 8 As shown, the main controller further includes a residual current elimination circuit, which includes a first transistor ATRPS1, a second transistor ATRPS2, and a third transistor ATRPS2. The bases of the first transistor ATRPS1, the second transistor ATRPS2, and the third transistor ATRPS2 are electrically connected to the corresponding control output terminals of the control circuit through corresponding resistors (RPS2, RPS3, and RPS4). The emitters of the first transistor ATRPS1, the second transistor ATRPS2, and the third transistor ATRPS2 are all grounded. The collectors of the first transistor ATRPS1, the second transistor ATRPS2, and the third transistor ATRPS2 are electrically connected to the power supply terminals (VCC_UR, VCC_UG, and VCC_UB) of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip through corresponding resistors (RPS5, RPS6, and RPS7).

[0061] It should be noted that the resistors in the above circuit structure can quickly eliminate residual electricity on the R-color display driver chip, G-color display driver chip, and B-color display driver chip, thereby eliminating induced electricity and interference, and ensuring that the power on and off of the display driver chips is rapid, stable, and reliable.

[0062] In summary, this utility model can adjust the power supply status of different display driver chips in real time according to the display situation, so as to ensure that the display driver chip that needs to display content is powered on and working stably, and the display driver chip that does not need to display content is powered off, thereby saving energy, reducing the power consumption of the display screen, improving battery life performance, and meeting the user's demand for long battery life.

[0063] Secondly, the MPPT solar controller can adjust the output power, improving power generation efficiency. Simultaneously, the series-connected solar panels reduce heat loss, further enhancing the range of the solar display trailer. Additionally, the processor can adjust the display screen brightness based on the detection signals from the photoelectric sensor, improving the user viewing experience while reducing power consumption, thus further improving the range of the solar display trailer.

[0064] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the claims of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A solar-powered display trailer, characterized in that, The system includes a vehicle body and a solar charging device, a display screen, an energy storage power supply, and a main controller installed on the vehicle body. The solar charging device is electrically connected to the energy storage power supply, and both the solar charging device and the energy storage power supply are electrically connected to the main controller. The main controller includes a processor and a power-saving adjustment module, and the processor is electrically connected to the display driver in the display screen. The power-saving adjustment module is electrically connected to the display driver and is used to control the power supply status of the display driver chip in the display driver. The processor is electrically connected to the power-saving adjustment module and is used to control the operation of the power-saving adjustment module.

2. The solar display trailer according to claim 1, characterized in that, The power-saving adjustment module includes a control circuit and a switch adjustment circuit, and the display driver includes an R-color display driver chip, a G-color display driver chip and a B-color display driver chip. The switching adjustment circuit is electrically connected to the power supply terminals of the R-color display driver chip, G-color display driver chip and B-color display driver chip respectively, and is used to control the power supply status of the R-color display driver chip, G-color display driver chip and B-color display driver chip respectively. The control circuit is electrically connected to both the processor and the switch adjustment circuit, and is used to receive control data sent by the processor and control the switching operation state of the switch adjustment circuit according to the control data.

3. The solar display trailer according to claim 1, characterized in that, The solar charging device includes a solar panel and an MPPT solar controller. The input terminal of the MPPT solar controller is connected to the solar panel, and the output terminal of the MPPT solar controller is electrically connected to the energy storage power supply and the main controller, respectively.

4. The solar display trailer according to claim 1, characterized in that, The vehicle body is equipped with a hydraulic lifting device that is electrically connected to the main controller, and the drive end of the hydraulic lifting device is connected to the display screen. The display screen is equipped with at least one photoelectric sensor, which is electrically connected to the processor.

5. The solar display trailer according to claim 2, characterized in that, The control circuit includes a clock status control circuit, a display status control circuit, and a power-saving processing circuit. The clock state control circuit is electrically connected to the processor and the display state control circuit respectively, and is used to perform clock validity judgment processing according to the clock signal input by the processor, and output a clock state control signal to the display state control circuit. The display status control circuit is electrically connected to the processor and the power-saving processing circuit respectively, and is used to perform display validity judgment processing based on the display signal input by the processor and the clock status control signal, and output the display status control signal to the power-saving processing circuit. The power-saving processing circuit is electrically connected to the processor and the switch adjustment circuit respectively, and is used to control the switching operation state of the switch adjustment circuit according to the power-saving switch signal input by the processor and the display status control signal.

6. The solar display trailer according to claim 5, characterized in that, The clock state control circuit includes a clock judgment chip, a capacitor, and a first resistor. The clock judgment chip includes a first edge-triggered input pin, a second edge-triggered input pin, a first positive output pin, a first inverted output pin, a timing capacitor pin, and a timing resistor pin. The first edge-triggered input pin is electrically connected to the first clock output pin of the processor, the second edge-triggered input pin is electrically connected to the power supply voltage, the first positive output pin and the inverted output pin are both connected to the display state control circuit, the timing capacitor pin is electrically connected to the power supply voltage via the capacitor and the first resistor in sequence, and the timing resistor pin is electrically connected to the power supply voltage via the first resistor.

7. The solar display trailer according to claim 6, characterized in that, The display state control circuit includes a first logic gate chip and a first latch chip. The first logic gate chip includes a first logic gate unit, a second logic gate unit, a third logic gate unit, and a fourth logic gate unit. The first input pin of the first logic gate unit, the first input pin of the second logic gate unit, and the first input pin of the third logic gate unit are all electrically connected to the first inverting output pin. The second input pin of the first logic gate unit is electrically connected to the first display signal output pin of the processor. The second input pin of the second logic gate unit is electrically connected to the second display signal output pin of the processor. The second input pin of the third logic gate unit is electrically connected to the third display signal output pin of the processor. The output pin of the first logic gate unit is electrically connected to the first set input pin of the first latch chip, the output pin of the second logic gate unit is electrically connected to the second set input pin of the first latch chip, the output pin of the third logic gate unit is electrically connected to the third set input pin of the first latch chip, both input pins of the fourth logic gate unit are grounded, and the output pin of the fourth logic gate unit is left floating. The first reset input pin, the second reset input pin, and the third reset input pin of the first latch chip are electrically connected to the first positive output pin, the enable pin of the first latch chip is electrically connected to the power supply voltage, and the three latch output pins of the first latch chip are all electrically connected to the power saving processing circuit.

8. The solar display trailer according to claim 7, characterized in that, The power-saving processing circuit includes a second latch chip and a second logic gate chip. The second logic gate chip includes a fifth logic gate unit, a sixth logic gate unit, a seventh logic gate unit, and an eighth logic gate unit. The display status input pin of the second latch chip is electrically connected to the latch output pin of the first latch chip in a one-to-one correspondence, and the power saving status input pin of the second latch chip is electrically connected to the power saving switch output pin of the processor. The three display status output pins of the second latch chip are electrically connected to the second input pins of the fifth logic gate unit, the sixth logic gate unit, and the seventh logic gate unit, respectively. The first input pins of the fifth logic gate unit, the sixth logic gate unit, and the seventh logic gate unit are all electrically connected to the power-saving output pins of the second latch chip. The output pins of the fifth logic gate unit, the sixth logic gate unit, and the seventh logic gate unit are electrically connected to the corresponding control terminals of the switch adjustment circuit. The first input pin of the eighth logic gate unit is electrically connected to the second clock output pin of the processor, the second input pin of the eighth logic gate unit is grounded, and the output pin of the eighth logic gate unit is electrically connected to the clock pin of the second latch chip.

9. The solar display trailer according to claim 2, characterized in that, The switch adjustment circuit includes a switch control module. The three gate control pins of the switch control module are electrically connected to the corresponding output terminals of the control circuit. The three source pins of the switch control module are electrically connected to the power supply voltage. The three drain output pins of the switch control module are electrically connected to the power supply terminals of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip, respectively.

10. The solar display trailer according to claim 2, characterized in that, The main controller further includes a residual current elimination circuit, which includes a first transistor, a second transistor, and a third transistor. The bases of the first transistor, the second transistor, and the third transistor are electrically connected to the corresponding control output terminals of the control circuit via resistors. The emitters of the first transistor, the second transistor, and the third transistor are all grounded. The collectors of the first transistor, the second transistor, and the third transistor are electrically connected to the corresponding power supply terminals of the R-color display driver chip, the G-color display driver chip, and the B-color display driver chip via resistors.

Images