A new digital composite signal generator

Abstract

The utility model provides a novel digital composite signal generator, specifically related to data composite signal technical field, including single-chip microcomputer and digital synthesis circuit, single-chip microcomputer inside integrated DAC, and DAC generates fundamental wave sinusoidal signal, and digital synthesis circuit includes operational amplifier module and low pass filter module, and the fundamental wave sinusoidal signal of DAC generation, through operational amplifier module promotes fundamental wave amplitude, and low pass filter restrains high -frequency noise, ensures the output smooth pure sinusoidal wave. Buffer amplifier enhances signal drive ability and adapts 100 omega load, and adjustable gain module realizes output amplitude accurate control. The on -chip VDD monitor real -time monitoring power supply anomaly, watchdog timer prevents program failure, and JTAG debugging circuit supports non -invasive full -speed in system debugging. The scheme fuses signal processing, voltage monitoring and fault protection function, realizes the novel digital composite signal generator of frequency and amplitude programmable control, guarantees output stable and reliable in industrial environment and long -term unattended operation.

Description

Technical Field

[0001] This utility model belongs to the field of data synthesis signal technology, and specifically relates to a novel digital synthesis signal generator. Background Technology

[0002] Digital synthesized signal generators (DDS), as important signal source devices, are widely used in communications, electronic measurement, and audio testing. However, traditional DDS still have significant shortcomings in practical applications. Their frequency range is narrow, especially in the low-frequency band (20Hz-1kHz) where the adjustment steps are large (typically ≥100Hz), resulting in insufficient signal generation precision and difficulty in achieving precise control with small steps such as 20Hz and 50Hz. Simultaneously, the amplitude adjustment range is limited (e.g., 0.4V-2V), making it difficult to meet the requirements of wide dynamic range signals. Furthermore, traditional DDS suffers from fixed modulation functions. Although they support basic modulation forms such as amplitude modulation (AM) and frequency modulation (FM), the modulation signal frequency and modulation depth (e.g., AM modulation depth is fixed at 50%) cannot be flexibly adjusted. The reliance on pure digital synthesis further limits the adaptability to dynamic testing. In terms of user interaction, traditional solutions often use a combination of LCD display and keyboard input, which not only has high hardware costs but is also susceptible to interference in high-noise industrial environments, resulting in low operating efficiency. These issues collectively limit the improvement of traditional DDS equipment in terms of accuracy, flexibility, and adaptability to industrial scenarios, making it difficult to meet the stringent requirements of modern electronic testing for high precision, dynamic adjustability, and environmental adaptability. Utility Model Content

[0003] The purpose of this invention is to provide a novel digital synthesized signal generator to solve the problems of traditional DDS in the prior art, such as narrow frequency range, large adjustment steps in the low frequency band, limited amplitude adjustment range, fixed modulation function, high hardware cost at the user interaction level and susceptibility to interference in industrial environments, and low operating efficiency, which make it difficult to meet the requirements of high precision, dynamic adjustability and environmental adaptability.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A novel digital synthesized signal generator includes a microcontroller and a digital synthesis circuit. The microcontroller integrates a DAC, which generates a fundamental sine wave signal. The digital synthesis circuit includes an operational amplifier module and a low-pass filter module. The output of the DAC is connected in sequence to the operational amplifier and the low-pass filter.

[0006] The input terminal of the digital synthesis circuit is an input coupling, which consists of a first capacitor C1 and a first resistor R1 connected in series.

[0007] The first resistor R1 is connected to the input terminal of the operational amplifier. The operational amplifier includes a third resistor R3 and a fourth resistor R4 connected in parallel. The fourth resistor R4 is the input terminal of the operational amplifier. The second capacitor C2 is shorted to the third resistor R3 and the fourth resistor R4. The third capacitor C3, the fourth capacitor C4 and the fourth resistor R4 are connected in series. The second resistor R2 is shorted across the fourth capacitor C4. The second resistor R2 and the third resistor R3 are connected to the input terminal of the power amplifier U1:A. The output terminal of the power amplifier U1:A is the output stage of the operational amplifier.

[0008] The fourth capacitor C4 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to a 50KΩ resistor with +12V to provide DC bias voltage for the operational amplifier.

[0009] The low-pass filter includes a sixth capacitor C6, an eighth capacitor C8, and a ninth capacitor C9 connected in parallel. A seventh resistor R7 and an eighth resistor R8 are connected in parallel between the sixth capacitor C6 and the eighth capacitor C8. The ninth capacitor C9 is the output stage of the low-pass filter.

[0010] One end of the seventh resistor R7 and the eighth resistor R8 is shorted to the seventh capacitor C7. One end of the seventh capacitor C7 is connected to the emitter of the NPN transistor Q1. The base of the NPN transistor Q1 is connected to the sixth capacitor C6. The seventh capacitor C7 and the NPN transistor Q1 form an emitter follower.

[0011] A buffer amplifier is shorted between the base and collector of the NPN transistor Q1. The buffer amplifier consists of a sixth resistor R6 connected in series and a potentiometer P1. The sliding end of the potentiometer P1 is shorted to one of its fixed ends. One of the shorted ends of the potentiometer P1 is connected to the current resistor R6. The other fixed end of the potentiometer P1 is connected to the base of the NPN transistor Q1.

[0012] The microcontroller has a built-in timer. When the microcontroller executes the program flow, the timer needs to be cleared periodically. If it is not cleared in time, the system will be automatically reset.

[0013] The microcontroller integrates a JTAG debugging circuit, allowing all functions within the microcontroller to be debugged non-intrusively, at full speed, and in-system via the JTAG debugging interface.

[0014] The microcontroller integrates a VDD monitor, which monitors the power supply voltage in real time to ensure that the microcontroller responds promptly when the voltage is abnormal.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] This invention proposes a novel digital synthesized signal generator that replaces the discrete modules (such as phase accumulators and waveform memory) of traditional DDS with a fully integrated mixed-signal system (including a VDD monitor, watchdog timer, and JTAG debugging interface). The fundamental signal is directly generated by the internal DAC, reducing external components and system complexity. A low-pass filter combined with an operational amplifier suppresses the step effect in the DAC-generated fundamental signal. A potentiometer P1 in the amplifier circuit enables continuously adjustable gain to adapt to different load requirements. A stable bias voltage is provided by connecting a +12V 50KΩ resistor to the other end of the fifth resistor R5, ensuring normal operation of the operational amplifier under a single power supply and preventing signal distortion.

[0017] Furthermore, the microcontroller integrates a VDD monitor and timer to monitor the power supply voltage in real time. In case of anomalies, it triggers protection logic (such as frequency reduction or module shutdown) to prevent system crashes caused by power fluctuations. The timer is periodically reset to prevent program crashes, making it suitable for long-term unattended operation. The microcontroller also integrates a JTAG interface to support full-speed online debugging, allowing real-time observation of register and memory status without affecting normal functionality, thus shortening the development cycle. The waveform generation algorithm can be remotely updated via the JTAG interface (such as adding FSK modulation) without hardware replacement, extending the device's lifespan.

[0018] Furthermore, the sixth capacitor C6, the eighth capacitor C8, and the ninth capacitor C9 in the low-pass filter form a multi-stage capacitor decoupling to suppress power supply noise. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the hardware principle of a novel digital synthesized signal generator according to the present invention. Detailed Implementation

[0020] To further understand the content of this utility model, the following describes it in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting. To further illustrate the technical means and effects adopted by this utility model to achieve its intended purpose, the specific implementation methods, structural features, and effects of this utility model are described in detail below with reference to the accompanying drawings and embodiments.

[0021] This embodiment uses a C8051F020 microcontroller to design a digital synthesized signal generator, including the microcontroller and a digital synthesis circuit. The microcontroller integrates a DAC (Digital-to-Analog Converter), which generates a fundamental sine wave signal. The digital synthesis circuit includes an operational amplifier module and a low-pass filter module. The output of the DAC is connected to the operational amplifier and the low-pass filter in sequence. The specific implementation method is as follows:

[0022] The C8051F020 microcontroller is a fully integrated mixed-signal system-on-a-chip (SoC) with 64 digital I / O pins (C8051F020 / 2) or 32 digital I / O pins (C8051F021 / 3). It integrates a VDD monitor, watchdog timer, and JTAG debug circuitry, making it a standalone system-on-a-chip. All analog and digital peripherals on the chip can be enabled / disabled and configured by the user firmware. The microcontroller has built-in FLASH memory with in-system reprogramming capability, which can be used for non-volatile data storage and allows field updates of the 8051 firmware. The on-chip JTAG debug circuitry allows non-intrusive (without consuming on-chip resources), full-speed, in-system debugging using the product MCU installed on the final application system. This debug system supports viewing and modifying memory and registers, and supports breakpoints, watchpoints, single-stepping, and run and stop commands. When using the JTAG debug circuitry, all analog and digital peripherals operate at full functionality. Each MCU can operate within the industrial temperature range (-45°C to +85°C) with a voltage of 2.7V - 3.6V. The port I / O, / RST, and JTAG pins all allow input signal voltages of 5V.

[0023] The C8051F020 microcontroller integrates a DAC. This DAC generates a fundamental sine wave signal, which is then input to a digital synthesis circuit for signal processing. The input of the digital synthesis circuit is input-coupled, consisting of a first capacitor C1 and a first resistor R1 connected in series. Capacitor C1 acts as a high-pass filter, blocking any DC component and allowing only AC signals to pass. Resistor R1 is connected to the input of an operational amplifier. The operational amplifier includes a third resistor R3 and a fourth resistor R4 connected in parallel. Resistor R4 provides a DC bias voltage to the non-inverting input of the operational amplifier. This bias voltage ensures the operational amplifier operates at its optimal state and prevents signal distortion. The fourth resistor R4 is the input terminal of the operational amplifier. The second capacitor C2 is shorted to the third resistor R3 and the fourth resistor R4. The third capacitor C3, the fourth capacitor C4, and the fourth resistor R4 are connected in series. The third capacitor C3 = 100nF. The second resistor R2 is shorted across the fourth capacitor C4. The second resistor R2 and the third resistor R3 are connected to the input terminal of the power amplifier U1:A. The output terminal of the power amplifier U1:A is the output stage of the operational amplifier. The fundamental sine wave signal is input into the operational amplifier through the first resistor R1. Through the gain mechanism inside the operational amplifier, the amplitude of the signal is amplified.

[0024] In a further preferred embodiment, the fourth capacitor C4 in the operational amplifier is connected to one end of the fifth resistor R5, which has a value of 1KΩ. The other end of the fifth resistor R5 is connected to a 50KΩ resistor with a value of +12V to provide a DC bias voltage for the operational amplifier, thereby ensuring that the operational amplifier operates stably under a single power supply.

[0025] After the fundamental sine wave signal is amplified by the operational amplifier, some high-frequency noise is introduced into the signal. Therefore, in this invention, a low-pass filter is connected after the output stage of the operational amplifier. The low-pass filter includes a sixth capacitor C6, an eighth capacitor C8, and a ninth capacitor C9 connected in parallel. A seventh resistor R7 and an eighth resistor R8 are connected in parallel between the sixth capacitor C6 and the eighth capacitor C8. The ninth capacitor C9 is the output stage of the low-pass filter. The operational amplifier, resistors R1 and R2, and capacitor C1 form a feedback network. This network determines the frequency response of the filter, that is, the filtering effect of the filter on signals of different frequencies. At the same time, due to the existence of the feedback network, the circuit amplifies low-frequency signals and attenuates high-frequency signals, thereby realizing the function of low-pass filtering. The cutoff frequency of the low-pass filter is set to 5-10 times the fundamental frequency (a 1kHz sine wave corresponds to a 5kHz cutoff frequency) to ensure that high-frequency noise attenuation is ≥ 20dB, thereby outputting a smooth sine wave. The amplified signal is further filtered by a low-pass filter to remove high-frequency noise, smooth the signal curve, and make the output fundamental sine wave signal purer.

[0026] In a further preferred embodiment, a buffer amplifier is added to the filtered signal to better drive the load. One end of the seventh resistor R7 and the eighth resistor R8 is shorted to the seventh capacitor C7. One end of the seventh capacitor C7 is connected to the emitter of the NPN transistor Q1. The base of the NPN transistor Q1 is connected to the sixth capacitor C6. The seventh capacitor C7 and the NPN transistor Q1 form an emitter follower. Utilizing the high input impedance and low output impedance characteristics of the emitter follower, the signal driving capability is enhanced, the output impedance is reduced, and the signal can be stably transmitted to the load.

[0027] Furthermore, to achieve more precise signal amplitude adjustment, an adjustable gain section is added. A sixth resistor R6 and a potentiometer P1 are connected in series between the base and collector of the NPN transistor Q1. The sliding terminal of potentiometer P1 is shorted to one of its fixed terminals. One shorted terminal of potentiometer P1 is connected to the current-carrying resistor R6, and the other fixed terminal of potentiometer P1 is connected to the base of the NPN transistor Q1. By adjusting potentiometer P1, the voltage division ratio of the circuit is changed, thereby adjusting the signal amplitude to meet the requirements of subsequent processing. Through the buffer amplifier and adjustable gain section, the digital synthesized signal generator can adapt to the current drive requirements of a 100Ω load and achieve programmable control of frequency and amplitude.

[0028] Furthermore, the C8051F020 microcontroller integrates a JTAG (Joint Test Action Group) debugging circuit, timer function, and VDD monitor. During signal generator operation, the on-chip VDD monitor continuously monitors the supply voltage. If the supply voltage exceeds or falls below a set threshold, the VDD monitor immediately triggers a corresponding interrupt signal, alerting the system to take protective measures, such as reducing the output amplitude, lowering the operating frequency, or directly shutting down some non-critical modules. This prevents signal distortion and chip damage caused by abnormal voltage, ensuring reliable system operation in complex power supply environments. The timer plays a crucial program monitoring role in this invention. During normal program execution, the timer needs to be periodically cleared. If a program malfunction (such as an infinite loop or being trapped in an invalid code segment) prevents timely clearing, the watchdog timer will automatically trigger a system reset upon timeout, causing the microcontroller to restart from its initial state. This effectively prevents program crashes and ensures stable signal generator output, significantly improving system reliability, especially during long-term unattended operation or in complex industrial environments with interference. The integrated JTAG debugging circuit allows technicians to install the microcontroller on the actual application circuit board during the signal generator's R&D and debugging phase. By connecting a debugger via the JTAG interface, non-intrusive, full-speed, in-system debugging is achieved. During debugging, data in memory and register values ​​can be observed and modified in real time. Breakpoints and observation points can be flexibly set, and single-step execution or run / stop operations can be performed. Comprehensive and detailed testing and optimization of various functions, such as signal generation algorithms, modulation functions, and parameter control, can be conducted, allowing for timely identification and resolution of potential problems. This significantly shortens the R&D cycle and improves product performance and stability. Furthermore, since JTAG debugging does not consume on-chip resources, it ensures that all analog and digital peripherals operate fully during debugging without affecting the normal operation mode simulation of the signal generator. The fundamental sine wave signal generated by the microcontroller's DAC is amplified and filtered before being output through capacitor C9. The on-chip VDD monitor monitors the supply voltage in real time, ensuring timely response to voltage anomalies. A watchdog timer prevents program crashes, enhancing system stability. All functions can be debugged non-intrusively, at full speed, and in-system via the JTAG debugging interface.

[0029] The above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this utility model. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this utility model should be covered within the protection scope of the claims of this utility model.

Claims

1. A novel digital composite signal generator characterized in that, It includes a microcontroller and a digital synthesis circuit. The microcontroller integrates a DAC, which generates a fundamental sine wave signal. The digital synthesis circuit includes an operational amplifier module and a low-pass filter module. The output of the DAC is connected to the operational amplifier and the low-pass filter in sequence.

2. A novel digital composite signal generator as claimed in claim 1, wherein, The input terminal of the digital synthesis circuit is an input coupling, which consists of a first capacitor C1 and a first resistor R1 connected in series.

3. A novel digital synthesized signal generator according to claim 1, characterized in that, The first resistor R1 is connected to the input terminal of the operational amplifier. The operational amplifier includes a third resistor R3 and a fourth resistor R4 connected in parallel. The fourth resistor R4 is the input terminal of the operational amplifier. The second capacitor C2 is shorted to the third resistor R3 and the fourth resistor R4. The third capacitor C3, the fourth capacitor C4 and the fourth resistor R4 are connected in series. The second resistor R2 is shorted across the fourth capacitor C4. The second resistor R2 and the third resistor R3 are connected to the input terminal of the power amplifier U1:A. The output terminal of the power amplifier U1:A is the output stage of the operational amplifier.

4. A novel digital synthesized signal generator according to claim 3, characterized in that, The fourth capacitor C4 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to a +12V 50V power supply. The resistor provides DC bias voltage to the operational amplifier.

5. A novel digital synthesized signal generator according to claim 1, characterized in that, The low-pass filter includes a sixth capacitor C6, an eighth capacitor C8, and a ninth capacitor C9 connected in parallel. A seventh resistor R7 and an eighth resistor R8 are connected in parallel between the sixth capacitor C6 and the eighth capacitor C8. The ninth capacitor C9 is the output stage of the low-pass filter.

6. A novel digital synthesized signal generator according to claim 5, characterized in that, One end of the seventh resistor R7 and the eighth resistor R8 is shorted to the seventh capacitor C7. One end of the seventh capacitor C7 is connected to the emitter of the NPN transistor Q1. The base of the NPN transistor Q1 is connected to the sixth capacitor C6. The seventh capacitor C7 and the NPN transistor Q1 form an emitter follower.

7. A novel digital synthesized signal generator according to claim 6, characterized in that, The NPN transistor Q1 is connected to the base and collector by a sixth resistor R6 and a potentiometer P1 connected in series. The sliding end of the potentiometer P1 is shorted to one of its fixed ends. One of the shorted ends of the potentiometer P1 is connected to the current resistor R6. The other fixed end of the potentiometer P1 is connected to the base of the NPN transistor Q1.

8. A novel digital synthesized signal generator according to claim 1, characterized in that, The microcontroller integrates a timer. When the microcontroller executes the program flow, the timer needs to be cleared periodically. If it is not cleared in time, the system will be automatically reset.

9. A novel digital synthesized signal generator according to claim 1, characterized in that, The microcontroller integrates a JTAG debugging circuit, and all functions within the microcontroller are debugged non-intrusively, at full speed, and in-system via the JTAG debugging interface.

10. A novel digital synthesized signal generator according to claim 1, characterized in that, The microcontroller integrates a VDD monitor, which monitors the power supply voltage in real time to ensure that the microcontroller responds promptly when the voltage is abnormal.

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