Smart watch and PCB mainboard thereof

Abstract

The utility model discloses an intelligent watch and PCB mainboard thereof. The PCB mainboard comprises: a mainboard main body; a plurality of functional circuit areas arranged on the mainboard main body, electronic components and / or metal wiring being arranged in the functional circuit areas; a plurality of signal isolation areas arranged on the mainboard main body, a plurality of first through holes penetrating through the mainboard main body being arranged in the signal isolation areas; and the plurality of first through holes are arranged in sequence at the edges of the signal isolation areas, so as to reduce signal interference and loss between different functional circuit areas.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, and in particular to a smartwatch and its PCB motherboard. Background Technology

[0002] With technological advancements and improved living standards, smartwatches are becoming increasingly accepted by consumers. Correspondingly, people have higher expectations for the functionality of smartwatches. However, existing smartwatches are limited by size, requiring very small spacing between electronic components on the PCB motherboard, which leads to signal interference and signal loss. Utility Model Content

[0003] This invention provides a smartwatch and its PCB motherboard to optimize the design of the PCB motherboard and reduce signal interference and loss.

[0004] According to one aspect of this utility model, a PCB motherboard for a smartwatch is provided, comprising:

[0005] Mainboard body;

[0006] Multiple functional circuit areas are provided on the main body of the motherboard, and electronic components and / or metal traces are provided in the functional circuit areas.

[0007] Multiple signal isolation areas are disposed on the main body of the motherboard, and multiple first through holes are disposed in the signal isolation areas, penetrating the main body of the motherboard; the multiple first through holes are arranged sequentially at the edge of the signal isolation areas to reduce signal interference and loss between different functional circuit areas.

[0008] Furthermore, the multiple first through holes form an edge isolation zone.

[0009] Furthermore, the edge isolation strip has at least two loops.

[0010] Furthermore, the first through holes in adjacent edge isolation strips are misaligned.

[0011] Furthermore, a plurality of second through holes penetrating the main body of the motherboard are also provided in the signal isolation area;

[0012] The plurality of second through holes are distributed between adjacent areas formed by the first through holes; or, the plurality of second through holes surround the area formed by the first through holes.

[0013] Furthermore, the density of the plurality of second through holes is less than the density of the plurality of first through holes;

[0014] Alternatively, the density of the plurality of second through holes is the same as the density of the plurality of first through holes.

[0015] Furthermore, both the first through hole and the second through hole are grounded.

[0016] Furthermore, the signal isolation area is an exposed conductive layer.

[0017] Furthermore, the functional circuit region includes at least one of a chip region and an antenna region.

[0018] According to another aspect of the present invention, a smartwatch is provided, comprising: a PCB motherboard as described in any embodiment of the present invention.

[0019] This embodiment of the invention utilizes the intervals between functional circuit regions, and sets first through-holes in these intervals to form signal isolation regions, thereby reducing signal interference and loss between different functional circuit regions. Specifically, the first through-hole is a through-hole that opens through both the front and back of the motherboard body, forming a two-sided interconnected structure, reducing the conduction paths between different functional circuit regions and increasing transmission barriers between them. Furthermore, this embodiment of the invention arranges the first through-holes sequentially at the edge of the signal isolation region, which can effectively block interference signals and losses generated by cross-modulation between different functional circuit regions, improving the integrity and efficiency of signal transmission. On the other hand, the setting of the first through-hole is equivalent to setting a heat dissipation channel on the motherboard body, which is beneficial to improving the heat dissipation performance of the PCB motherboard. In summary, the PCB motherboard provided by this embodiment of the invention can improve the integrity and efficiency of signal transmission and improve the heat dissipation performance of the PCB motherboard within a limited space, thereby adapting to the miniaturization development of smartwatches.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the PCB motherboard of a smartwatch provided in this embodiment of the present invention;

[0023] Figure 2 A schematic diagram of the PCB motherboard of another smartwatch provided in an embodiment of this utility model;

[0024] Figure 3 This is a schematic diagram of the PCB motherboard of another smartwatch provided in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] Figure 1 This is a schematic diagram of the PCB motherboard of a smartwatch provided as an embodiment of the present invention. See also... Figure 1 The PCB motherboard of this smartwatch includes:

[0028] Motherboard body 100;

[0029] Multiple functional circuit areas 200 are provided on the main body 100 of the motherboard, and electronic components and / or metal traces are provided in the functional circuit areas 200.

[0030] Multiple signal isolation areas 300 are provided on the main body 100 of the motherboard. Multiple first through holes 310 are provided in the signal isolation areas 300 to penetrate the main body 100 of the motherboard. The multiple first through holes 310 are arranged sequentially at the edge of the signal isolation areas 300 to reduce signal interference and loss between different functional circuit areas 200.

[0031] The motherboard 100 is used in a smartwatch. To enable the smartwatch's display, call, communication, and playback functions, the motherboard 100 needs to be equipped with various electronic components such as chips, resistors, capacitors, and inductors. For example, some chips, resistors, capacitors, and inductors constitute a display driving circuit. These electronic components are usually grouped together to form a functional circuit area 200, which drives the display screen. In some embodiments, an antenna structure capable of signal transmission and reception is also required. This antenna structure can use the same copper layer as the wires. Thus, the area where the antenna structure is set constitutes another functional circuit area 200, which is capable of signal transmission and reception.

[0032] Since the motherboard body 100 is used in smartwatches, its size is generally small, and the spacing between these functional circuit areas 200 is generally small. Specifically, the motherboard body 100 can be a single-sided board, a double-sided board, or a multi-layer board, etc. Regardless of the type, the motherboard body 100 is usually a whole unit. Different functional circuit areas 200 can transmit signals through the motherboard body 100 as a medium, which leads to signal interference and loss problems.

[0033] This embodiment of the invention utilizes the intervals between functional circuit regions 200, and sets first through holes 310 in these intervals to form signal isolation regions 300, thereby reducing signal interference and loss between different functional circuit regions 200. Specifically, the first through hole 310 is a through hole that opens through the front and back of the motherboard body 100, forming a two-sided interconnected structure, reducing the conduction path between different functional circuit regions 200 and increasing the transmission obstacles between different functional circuit regions 200. Furthermore, this embodiment of the invention arranges the first through holes 310 sequentially at the edge of the signal isolation region 300, which can effectively block interference signals and losses generated by cross-modulation between different functional circuit regions 200, improving the integrity and efficiency of signal transmission. On the other hand, the setting of the first through hole 310 is equivalent to setting a heat dissipation channel on the motherboard body 100, which is beneficial to improving the heat dissipation performance of the PCB motherboard. In summary, the PCB motherboard provided by this embodiment of the invention can improve the integrity and efficiency of signal transmission and improve the heat dissipation performance of the PCB motherboard within a limited space, thereby adapting to the miniaturization development of smartwatches.

[0034] Optionally, the functional circuit region 200 includes at least one of a chip region and an antenna region. The chip region contains a chip and peripheral circuits composed of other electronic components; the antenna region contains an antenna structure. Since the chip region and antenna region are prone to signal interference, providing signal isolation regions 300 at intervals around the chip region or antenna region helps to specifically reduce signal interference.

[0035] See also Figure 1 Based on the above embodiments, optionally, multiple first through holes 310 form an edge isolation zone. This arrangement facilitates signal isolation from all sides of the functional circuit region 200, increasing transmission barriers between different functional circuit regions 200.

[0036] Figure 2 A schematic diagram of the PCB motherboard of another smartwatch provided as an embodiment of this utility model. See also... Figure 2 Based on the above embodiments, optionally, at least some of the edge isolation strips have at least two turns. This configuration is equivalent to increasing the number of first through holes 310, thereby enhancing the signal isolation effect.

[0037] See also Figure 2 Based on the above embodiments, optionally, the first through holes 310 in adjacent edge isolation strips are staggered. For example, there are two edge isolation strips, with the first through hole 310 in the outer edge isolation strip located between two adjacent first through holes 310 in the inner edge isolation strip. This arrangement compensates for the weakened isolation effect caused by the need for a certain interval between adjacent first through holes 310. Specifically, when a signal passes through the gap between two adjacent first through holes 310 in the inner edge isolation strip, it will be blocked by the first through hole 310 in the outer edge isolation strip. Therefore, the staggered arrangement of the first through holes 310 in adjacent edge isolation strips in this embodiment further improves the anti-signal interference effect.

[0038] Figure 3 A schematic diagram of the PCB motherboard of another smartwatch provided as an embodiment of this utility model. See also... Figure 3 Based on the above embodiments, optionally, a plurality of second through holes 320 penetrating the motherboard body 100 are further provided in the signal isolation area 300. Similar to the first through hole 310, the second through hole 320 is a through hole that opens up the front and back of the motherboard body 100, forming a two-sided interconnected structure. This assists the first through hole 310 in reducing the conduction path between different functional circuit areas 200 and increases the transmission barrier between different functional circuit areas 200. On the other hand, the setting of the second through hole 320 assists the first through hole 310 in setting up a heat dissipation channel on the motherboard body 100, which is beneficial to further improve the heat dissipation performance of the PCB motherboard.

[0039] See also Figure 3 In one embodiment, optionally, a plurality of second vias 320 are distributed between the areas (i.e., edge isolation zones) formed by adjacent first vias 310. This arrangement helps to further improve the integrity and efficiency of signal transmission, as well as further enhance the heat dissipation performance of the PCB motherboard.

[0040] See also Figure 3 In another embodiment, optionally, a plurality of second through holes 320 surround the area (i.e., the edge isolation strip) formed by the first through hole 310. This arrangement helps to further improve the heat dissipation performance of the PCB motherboard.

[0041] See also Figure 3 Based on the above embodiments, optionally, the density of the plurality of second vias 320 is less than the density of the plurality of first vias 310. The first vias 310 are vias closer to the functional circuit region 200, and are the main structures for reducing signal interference and loss between different functional circuit regions 200. Therefore, the density of the first vias 310 needs to be set relatively high, and correspondingly, the density of the second vias 320 can be set relatively low.

[0042] It should be noted that, in Figure 3 The example illustrates that the density of the second through-hole 320 is less than the density of the first through-hole 310, but this is not intended to limit the present invention. In another embodiment, optionally, the density of the plurality of second through-holes 320 is the same as the density of the plurality of first through-holes 310.

[0043] Based on the above embodiments, optionally, both the first through-hole 310 and the second through-hole 320 are grounded. This configuration ensures that the signals from the first through-hole 310 and the second through-hole 320 are stabilized as grounded signals, thereby preventing the potentials on the first through-hole 310 and the second through-hole 320 from changing with signal fluctuations received on the functional circuit region 200, thus further reducing signal interference and loss between different functional circuit regions 200.

[0044] Based on the above embodiments, optionally, the signal isolation region 300 is an exposed conductive layer. The PCB motherboard includes a substrate and conductive layers. For a single-sided board, the number of conductive layers is one; for a double-sided board, the number of conductive layers is two; and for a multi-layer board, the number of conductive layers is multiple. In the functional circuit area 200, a solder mask layer is typically coated on the conductive layer, while in the signal isolation region 300, this conductive layer is exposed. This configuration helps with heat dissipation of the PCB motherboard.

[0045] Based on the above embodiments, optionally, by improving the manufacturing process of the first through-hole 310 and the second through-hole 320 on the PCB motherboard, it is beneficial to improve the manufacturing precision and reliability of the first through-hole 310 and the second through-hole 320, thereby enhancing product quality and stability. Specifically, by improving the manufacturing process, the manufacturing precision and hole wall quality of the first through-hole 310 and the second through-hole 320 can be improved, making the dimensions of the first through-hole 310 and the second through-hole 320 more accurate and the hole walls smoother; at the same time, adopting an optimized metallization process helps to ensure the uniformity and density of the metallization layer. This configuration helps to enhance the stability and long-term reliability of the electrical connection of the first through-hole 310 and the second through-hole 320, reduce the probability of product failure due to through-hole problems, and thus help to improve the product quality and service life of smartwatches.

[0046] Furthermore, the technical solution provided by this utility model embodiment has good compatibility with existing PCB manufacturing processes. Without changing the main framework of existing manufacturing equipment and processes, only some process parameters and equipment need to be appropriately adjusted and upgraded to realize the production and manufacturing of the PCB motherboard provided by this utility model embodiment, which is convenient for promotion and application in actual production and reduces the cost and difficulty of technical implementation.

[0047] This utility model also provides a smartwatch, which includes a PCB motherboard as provided in any embodiment of this utility model. The smartwatch also includes components such as a display screen, camera, microphone, and speaker, which are electrically connected to the PCB motherboard and can interact with and control the PCB motherboard via signals.

[0048] This embodiment of the invention utilizes the spacing between functional circuit areas 200 on a PCB motherboard, and sets first through-holes 310 in these spacings to form a signal isolation area 300, thereby reducing signal interference and loss between different functional circuit areas 200. Specifically, the first through-hole 310 is a through-hole that opens through both the front and back of the motherboard body 100, forming a two-sided interconnected structure, reducing the conduction path between different functional circuit areas 200 and increasing the transmission obstacles between them. Furthermore, this embodiment of the invention arranges the first through-holes 310 sequentially at the edge of the signal isolation area 300, which can effectively block interference signals and losses generated by cross-modulation between different functional circuit areas 200, improving the integrity and efficiency of signal transmission. On the other hand, the setting of the first through-holes 310 is equivalent to setting a heat dissipation channel on the motherboard body 100, which is beneficial to improving the heat dissipation performance of the PCB motherboard. In summary, the PCB motherboard provided by this embodiment of the invention can improve the integrity and efficiency of signal transmission and improve the heat dissipation performance of the PCB motherboard within a limited space, thereby adapting to the miniaturization development of smartwatches.

[0049] Tests have shown that by adopting the technical solution provided in this embodiment of the invention, the attenuation of high-frequency signals on the PCB motherboard of the smartwatch is reduced by more than 30%, and the signal transmission delay is reduced by more than 20%, thereby improving the overall performance of the smartwatch.

[0050] Furthermore, this utility model embodiment significantly reduces the space occupied by the first through hole 310 and the second through hole 320 while satisfying the electrical connection function, thereby improving the space utilization of the PCB motherboard. Specifically, it can save about 20%-30% of the PCB motherboard space, making it possible to integrate more functional modules into smartwatches and helping smartwatches achieve miniaturization and multifunctionality.

[0051] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0052] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A PCB motherboard for a smartwatch, characterized in that, include: Mainboard body; Multiple functional circuit areas are provided on the main body of the motherboard, and electronic components and / or metal traces are provided in the functional circuit areas. Multiple signal isolation areas are disposed on the main body of the motherboard, and multiple first through holes are disposed in the signal isolation areas, penetrating the main body of the motherboard; the multiple first through holes are arranged sequentially at the edge of the signal isolation areas to reduce signal interference and loss between different functional circuit areas.

2. The PCB motherboard of the smartwatch according to claim 1, characterized in that, Multiple first through holes form an edge isolation zone.

3. The PCB motherboard of the smartwatch according to claim 2, characterized in that, The edge isolation strip has at least two loops.

4. The PCB motherboard of the smartwatch according to claim 3, characterized in that, The first through holes in adjacent edge isolation strips are misaligned.

5. The PCB motherboard of the smartwatch according to claim 1, characterized in that, The signal isolation area is also provided with a plurality of second through holes penetrating the main body of the motherboard; The plurality of second through holes are distributed between adjacent areas formed by the first through holes; or, the plurality of second through holes surround the area formed by the first through holes.

6. The PCB motherboard of the smartwatch according to claim 5, characterized in that, The density of the plurality of second through holes is less than the density of the plurality of first through holes; Alternatively, the density of the plurality of second through holes is the same as the density of the plurality of first through holes.

7. The PCB motherboard of the smartwatch according to claim 5, characterized in that, Both the first through hole and the second through hole are grounded.

8. The PCB motherboard of the smartwatch according to claim 1, characterized in that, The signal isolation area is an exposed conductive layer.

9. The PCB motherboard of the smartwatch according to claim 1, characterized in that, The functional circuit region includes at least one of the chip region and the antenna region.

10. A smartwatch, characterized in that, include: The PCB motherboard as described in any one of claims 1-9.

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