Chip structure and chip package
By setting an independent first PI layer and an edge-filled second PI layer on the functional surface of the chip body, combined with an underfill layer, the warpage problem in 2.5D packaging is solved, the reliability of the chip structure and the interface bonding strength are improved, and the cost is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU TF AMD SEMICON CO LTD
- Filing Date
- 2025-06-25
- Publication Date
- 2026-06-23
AI Technical Summary
In 2.5D packaging, the large differences in CTE between materials such as silicon interposer, organic substrate, and solder balls cause thermal stress concentration at the four corners or four sides of the chip when the temperature changes, leading to warping and interface delamination, which affects the reliability of the device.
An independent first PI layer is set around the bump on the functional surface of the chip body, and a second PI layer is filled in the edge area and connected to the first PI layer. Combined with the underfill adhesive layer, a buffer structure is formed to improve the interface bonding strength and stress transmission.
It reduces package warpage, improves the long-term reliability and economic efficiency of the chip structure, and enhances interface bonding strength by buffering stress, thus saving costs.
Smart Images
Figure CN224402111U_ABST
Abstract
Description
Technical Field
[0001] This disclosure pertains to the field of semiconductor packaging technology, specifically relating to a chip structure and a chip package. Background Technology
[0002] Polyimide (PI) is widely used in semiconductor packaging due to its excellent high-temperature resistance, mechanical strength, dielectric properties, and chemical stability. The PI layer effectively inhibits electron migration and prevents corrosion. The PI layer also acts as a buffer, effectively reducing circuit breakage caused by thermal stress and minimizing damage to components during subsequent processing, packaging, and post-processing.
[0003] Driven by demands from fields such as AI, high-performance computing, and automotive electronics, 2.5D packaging technology has developed rapidly in recent years. In 2.5D packaging, polyimide (PI) is typically laid around the chip's bumps, which increases the device's mechanical properties, prevents chemical corrosion, and effectively enhances the component's moisture resistance. However, the CTE (Coefficient of Thermal Expansion) of materials such as silicon interposers, organic substrates, and solder balls varies significantly. When temperatures change, thermal stress concentrates at the corners or edges of the chip, leading to package warpage. This warpage can cause interface delamination, posing a challenge to device reliability.
[0004] To address the aforementioned issues, it is necessary to propose a reasonably designed chip structure and chip package that can effectively improve these problems. Utility Model Content
[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a chip structure and chip package.
[0006] This disclosure provides a chip structure, including a chip body, multiple bumps, multiple first PI layers and second PI layers;
[0007] Multiple bumps are disposed on the functional surface of the chip body;
[0008] Each of the first PI layers is independently disposed on the functional surface of the chip body and surrounds the corresponding bump, wherein the height of the first PI layer is lower than the height of the bump;
[0009] The second PI layer is located at the edge region of the functional surface of the chip body, and fills the gap between the first PI layers corresponding to some of the bumps, and is connected to the corresponding first PI layer.
[0010] Optionally, the second PI layer is disposed in the outermost region of the functional surface of the chip body, and is connected to the first PI layer corresponding to the outermost rows of bumps.
[0011] Optionally, the number of the second PI layers is four, and the four second PI layers are arranged end to end in the outermost region of the functional surface of the chip body.
[0012] Optionally, the second PI layer is in the form of strips.
[0013] Optionally, the second PI layer is disposed at the corner of the functional surface of the chip body.
[0014] Optionally, the number of the second PI layers is four, and the four second PI layers are respectively disposed at the four corners of the functional surface of the chip body.
[0015] Optionally, the second PI layer is triangular in shape.
[0016] Optionally, the height of the first PI layer is the same as the height of the second PI layer.
[0017] Optionally, the first PI layer and the second PI layer are made of the same material.
[0018] Another aspect of this disclosure provides a chip package, including a substrate, a chip structure, and an underfill layer; wherein the chip structure adopts the chip structure described above;
[0019] The chip body is flip-mounted onto the substrate via the bumps;
[0020] The underfill layer is disposed between the chip body and the substrate, wherein the underfill layer wraps the bump and is connected to the second PI layer.
[0021] The chip structure and chip package of this disclosure embodiment include a second PI layer located at the edge region of the chip body's functional surface. This second PI layer fills the gaps between first PI layers corresponding to some of the bumps and is connected to the corresponding first PI layers. Compared to covering the entire chip functional surface with a second PI layer, this method only provides the second PI layer at the edge region of the chip body's functional surface, reducing technical difficulty and saving economic costs. After plasma cleaning, the roughness of the chip body's functional surface increases, increasing the bonding area between the chip body's edge region and the underfill adhesive, improving the bonding effect and enhancing the interface bonding strength, thus reducing package warpage. Stress can be transmitted through the relatively weak stress-resistant interface layer to the second PI layer located at the edge region of the chip's functional surface, buffering the stress and improving the chip's stress resistance, which helps improve the long-term reliability of the chip structure. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of a chip structure according to one embodiment of the present disclosure;
[0023] Figure 2 for Figure 1 An enlarged view of position A in the middle;
[0024] Figure 3 This is a schematic diagram of a chip structure according to another embodiment of the present disclosure;
[0025] Figure 4 for Figure 3 Enlarged schematic diagram of position B in the middle;
[0026] Figure 5 This is a schematic diagram of the structure of a chip package according to another embodiment of this disclosure. Detailed Implementation
[0027] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation methods.
[0028] like Figures 1 to 4 As shown, one aspect of this disclosure provides a chip structure 100, including a chip body 110, a plurality of bumps 120, and a plurality of first PI layers and second PI layers 130;
[0029] Multiple bumps 120 are disposed on the functional surface of the chip body 110. The chip body 110 can be flip-chip mounted on the substrate using the multiple bumps 120.
[0030] Each first PI layer is independently disposed on the functional surface of the chip body 110 and surrounds the corresponding bump 120, wherein the height of the first PI layer is lower than the height of the bump 120. The structure of the first PI layer is a PI layer structure commonly used in the prior art that surrounds the chip bump.
[0031] The second PI layer 130 is located at the edge region of the functional surface of the chip body, and fills the gaps between the first PI layers corresponding to some of the bumps 120, and is connected to the corresponding first PI layers. The height of the first PI layer is the same as the height of the second PI layer 130.
[0032] Since the first PI layers distributed around the bumps 120 are independently configured, there are gaps between adjacent first PI layers. The second PI layer 130 is located at the edge region of the functional surface of the chip body and fills the gaps between the first PI layers corresponding to some of the bumps 120, so that the first PI layers are connected to the corresponding second PI layers 130, and the height of the filled second PI layer 130 is the same as the height of the first PI layer. In other words, the first PI layer is located in the gap between adjacent first PI layers and is connected to the second PI layer 130 as a whole, and the height is the same.
[0033] Specifically, a chip structure with a second PI layer is mounted onto a substrate via reflow soldering. After plasma cleaning, the chip surface roughness increases, and the second PI layer at the edge of the functional surface of the chip exhibits an uneven structure. An underfill is injected beneath the chip body, ensuring sufficient wetting between the underfill and the second PI layer, thus optimizing their bonding. After high-temperature curing, the interfacial bonding strength between the second PI layer and the underfill is enhanced, allowing stress at the edge of the chip body to be effectively and evenly transmitted through the relatively weaker stress-resistant interfacial layer to the second PI layer at the chip body edge, thus acting as a stress buffer.
[0034] The chip structure and chip package of this disclosure embodiment include a second PI layer located at the edge region of the chip body's functional surface. This second PI layer fills the gaps between first PI layers corresponding to some of the bumps and is connected to the corresponding first PI layers. Compared to covering the entire chip functional surface with a second PI layer, this method only provides the second PI layer at the edge region of the chip body's functional surface, reducing technical difficulty and saving economic costs. After plasma cleaning, the roughness of the chip body's functional surface increases, increasing the bonding area between the chip body's edge region and the underfill adhesive, improving the bonding effect and enhancing the interface bonding strength, thus reducing package warpage. Stress can be transmitted through the relatively weak stress-resistant interface layer to the second PI layer located at the edge region of the chip's functional surface, buffering the stress and improving the chip's stress resistance, which helps improve the long-term reliability of the chip structure.
[0035] For example, such as Figure 1 and Figure 2 As shown, in one embodiment, the second PI layer 130 is disposed in the outermost region of the functional surface of the chip body and is connected to the first PI layer corresponding to the outermost several rows of bumps 120.
[0036] Specifically, such as Figure 1 As shown, there are four second PI layers 130, which are connected end-to-end and located at the outermost edge of the functional surface of the chip body. Figure 2 As shown, the second PI layer 130 located in the outermost region of the chip body fills the gap between the first PI layers corresponding to the outermost three rows of bumps 120, and is connected to the corresponding first PI layers.
[0037] It should be noted that in this embodiment, the number of rows of the outermost protrusion 120 is not specifically limited and can be selected according to actual needs.
[0038] Furthermore, in this embodiment, the second PI layer 130 is strip-shaped. The strip-shaped second PI layer 130 is connected end to end and disposed in the outermost region of the functional surface of the chip body.
[0039] In this embodiment, the second PI layer 130 is disposed in the outermost region of the functional surface of the chip body and is connected to the first PI layer corresponding to the outermost rows of bumps. This reduces technical difficulty and saves economic costs. After plasma cleaning, the roughness of the functional surface of the chip body increases, the area of the outermost region of the chip body bonded to the underfill increases, the bonding effect between the two is improved, the interface bonding strength is enhanced, and the package warpage is reduced. Stress can be transmitted through the relatively weak interface layer to the second PI layer located in the outermost region of the functional surface of the chip, the stress is buffered, the chip's ability to resist stress is enhanced, and it helps to improve the long-term reliability of the chip structure.
[0040] like Figure 3 and Figure 4 As shown, in another embodiment, the second PI layer 130 is disposed in the corner region of the functional surface of the chip body and is connected to the first PI layer corresponding to the bump 120.
[0041] Specifically, such as Figure 3 As shown, in this embodiment, there are four second PI layers 130, which are respectively disposed at the four corners of the functional surface of the chip body. Figure 4 As shown, the second PI layer 130 fills and is disposed on the first PI layer corresponding to the outermost rows of protrusions 120 partially distributed at the corners, and is connected to the corresponding first PI layer. In this embodiment, the number of rows of the outermost protrusions 120 is not specifically limited and can be selected according to actual needs.
[0042] Furthermore, in this embodiment, the second PI layer 130 is triangular in shape. The triangular second PI layer 130 corresponds to the four corners of the chip body 110.
[0043] In this embodiment, the second PI layer 130 is disposed at the four corner regions of the functional surface of the chip body, and the connecting portion is distributed in the first PI layer corresponding to the outermost rows of bumps at the corners. This reduces technical difficulty and saves economic costs. After plasma cleaning, the roughness of the functional surface of the chip body increases, the area of bonding between the four corner regions of the chip body and the underfill adhesive increases, the bonding effect between the two is improved, the interface bonding strength is increased, and the package warpage is reduced. Stress can be transmitted through the relatively weak interface layer to the second PI layer located at the four corner regions of the functional surface of the chip, the stress is buffered, the chip's ability to resist stress is improved, and it helps to improve the long-term reliability of the chip structure.
[0044] For example, the first PI layer and the second PI layer 130 are made of the same material, both of which are polyimide.
[0045] For example, the height of the first PI layer and the second PI layer 130 is 5μm to 7μm, which is lower than the height of the bump 120, thus exposing the connection surface between the bump 120 and the substrate.
[0046] like Figure 5 As shown, another aspect of this disclosure provides a chip package 200, including a substrate 210, a chip structure 100, and an underfill layer 220; wherein the chip structure 100 adopts the chip structure 100 described above. The specific structural features of the chip structure 100 have been described in detail above and will not be repeated here.
[0047] The chip body 110 is flip-mounted onto the substrate 210 via bumps 120.
[0048] The underfill layer 220 is disposed between the chip body 110 and the substrate 210, wherein the underfill layer 220 covers the bump 120 and is connected to the second PI layer 130.
[0049] The chip package of this embodiment adopts the chip package structure described above. After plasma cleaning, the roughness of the chip body increases, the bonding area between the chip body edge region and the underfill layer increases, the bonding effect between the two is improved, the interface bonding strength is increased, and the package warpage is reduced. Stress can be transmitted to the second PI layer located in the chip body edge region through the relatively weak interface layer, the stress is buffered, the chip structure's ability to resist stress is improved, and it helps to improve the long-term reliability of the chip package.
[0050] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the embodiments of this disclosure, and the embodiments of this disclosure are not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of this disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of this disclosure.
Claims
1. A chip structure, characterized in that, Includes the chip body, multiple bumps, multiple first PI layers and second PI layers; Multiple bumps are disposed on the functional surface of the chip body; Each of the first PI layers is independently disposed on the functional surface of the chip body and surrounds the corresponding bump, wherein the height of the first PI layer is lower than the height of the bump; The second PI layer is located at the edge region of the functional surface of the chip body, and fills the gap between the first PI layers corresponding to some of the bumps, and is connected to the corresponding first PI layer.
2. The chip structure according to claim 1, characterized in that, The second PI layer is disposed in the outermost region of the functional surface of the chip body and is connected to the first PI layer corresponding to the outermost rows of bumps.
3. The chip structure according to claim 2, characterized in that, There are four second PI layers, which are connected end to end and located at the outermost edge of the functional surface of the chip body.
4. The chip structure according to claim 3, characterized in that, The second PI layer is in the form of strips.
5. The chip structure according to claim 1, characterized in that, The second PI layer is disposed at the corner of the functional surface of the chip body.
6. The chip structure according to claim 5, characterized in that, The number of the second PI layers is four, and the four second PI layers are respectively disposed at the four corners of the functional surface of the chip body.
7. The chip structure according to claim 6, characterized in that, The second PI layer is triangular in shape.
8. The chip structure according to any one of claims 1 to 7, characterized in that, The height of the first PI layer is the same as the height of the second PI layer.
9. The chip structure according to any one of claims 1 to 7, characterized in that, The first PI layer and the second PI layer are made of the same material.
10. A chip package, characterized in that, It includes a substrate, a chip structure, and an underfill layer; wherein the chip structure adopts the chip structure according to any one of claims 1 to 9; The chip body is flip-mounted onto the substrate via the bumps; The underfill layer is disposed between the chip body and the substrate, wherein the underfill layer wraps the bump and is connected to the second PI layer.