A packaging structure, chip and electronic device

Abstract

This disclosure relates to a packaging structure, a chip, and an electronic device. The packaging structure includes a first semiconductor unit, a second semiconductor unit, and at least one set of functional modules. The second semiconductor unit is stacked with the first semiconductor unit, and the size of the first semiconductor unit is smaller than the size of the second semiconductor unit. Along the stacking direction, the projection of the first semiconductor unit onto the second semiconductor unit falls into a first region of the second semiconductor unit. The second semiconductor unit includes a second region, which is offset from the first region. At least one set of functional modules is stacked with the second semiconductor unit. Along the stacking direction, the functional modules are disposed in the second region, and the functional modules are used to implement preset functions. By adopting the solution of this disclosure, the excess physical space formed between the stacked semiconductor units of different sizes can be effectively utilized. Functional modules with preset functions can be disposed in the empty area, thereby improving the space utilization rate inside the packaging structure while keeping the size of the packaging structure unchanged.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a packaging structure, a chip, and an electronic device. Background Technology

[0002] With the development of semiconductor technology, chip manufacturing has approached its physical limits. At the same time, with the rise of artificial intelligence applications, the demand for high bandwidth, high computing power, low latency, and low power consumption in application scenarios is becoming increasingly strong.

[0003] One advanced packaging method in related technologies (such as chiplet) is based on the principle of "separate first, then combine." This means that chips with a specific function are first separated out, and then different manufacturing processes are used to process and manufacture them according to their different functions. Finally, multiple chips are integrated and packaged into an integrated chip through advanced packaging technology. Utility Model Content

[0004] To overcome the problems existing in related technologies, this disclosure provides a packaging structure, a chip, and an electronic device.

[0005] According to a first aspect of this disclosure, a packaging structure is provided, comprising:

[0006] First semiconductor unit;

[0007] A second semiconductor unit is stacked with the first semiconductor unit. The size of the first semiconductor unit is smaller than the size of the second semiconductor unit. Along the stacking direction, the projection of the first semiconductor unit onto the second semiconductor unit falls into a first region of the second semiconductor unit. The second semiconductor unit includes a second region, which is offset from the first region.

[0008] At least one set of functional modules is stacked with the second semiconductor unit. Along the stacking direction, the functional modules are disposed in the second region, and the functional modules are used to implement a preset function.

[0009] In the packaging structure provided in this embodiment, there is a size difference between the two stacked semiconductor units. The size difference will create some empty physical space between the two semiconductor units. By setting a functional module with preset function in the empty physical space, it is possible to avoid the adverse effects of the empty physical space on the packaging structure and improve the space utilization rate inside the packaging structure.

[0010] In some embodiments of this disclosure, the packaging structure includes multiple sets of the functional modules, including at least one set of storage modules for implementing storage functions, and the storage module includes at least one third semiconductor unit.

[0011] The encapsulation structure provided in this embodiment can include multiple sets of functional modules, which can be used to implement different functions, thereby improving the functionality of the encapsulation structure from multiple aspects simultaneously. At least one set of functional modules is a storage module used to implement storage functions, thereby ensuring the functionality of the encapsulation structure while increasing the bandwidth and storage performance of the encapsulation structure.

[0012] In some embodiments of this disclosure, multiple sets of functional modules are disposed at different locations in the second region, and the multiple sets of functional modules are staggered.

[0013] In this embodiment, multiple sets of functional modules can be arranged in various different distribution patterns according to the shape of the free physical space, which improves the diversity of the internal layout of the packaging structure. At the same time, the staggered arrangement of multiple sets of functional modules can reduce interference through physical isolation and optimize space utilization.

[0014] In some embodiments of this disclosure, the storage module includes a plurality of the third semiconductor units, which are stacked and adjacent third semiconductor units are insulated from each other.

[0015] In this embodiment, the storage module may include multiple third semiconductor units stacked together, so that the number of third semiconductor units can be selected according to the amount of available physical space and the storage performance to be expanded, thus making reasonable use of the internal space of the functional module.

[0016] In some embodiments of this disclosure, adjacent third semiconductor units are bonded together.

[0017] In this embodiment, multiple third semiconductor units are bonded together, which is a simple and reliable connection method that does not require complex processes. This not only results in high integration but also low cost.

[0018] In some embodiments of this disclosure, the packaging structure further includes a substrate and memory chips, wherein the substrate and the memory chips are stacked together, the second semiconductor unit is stacked together with the substrate, and the second semiconductor unit is staggered from the memory chips.

[0019] In the packaging structure provided in this embodiment, the memory chip and the second semiconductor unit are both disposed on the substrate. They are staggered and distributed in different areas of the substrate, which effectively utilizes the space utilization inside the packaging structure and enables the packaging structure to have a variety of different functions.

[0020] In some embodiments of this disclosure, the third semiconductor unit is bonded to the second semiconductor unit through a first adhesive layer, and adjacent third semiconductor units are connected through a second adhesive layer.

[0021] The third semiconductor unit is connected to the substrate by wire bonding, and the thickness of the second adhesive layer is greater than the thickness of the first adhesive layer.

[0022] In this embodiment, the third semiconductor unit is connected to the substrate and the second semiconductor unit by adhesive bonding, which not only ensures high connection reliability but also reduces cost and facilitates processing. Meanwhile, since the third semiconductor unit is connected to the substrate by wire bonding, in order to ensure that there is enough space between two adjacent third semiconductor units for the wiring, the thickness of the second adhesive layer is set to be larger, thereby improving the reliability of the entire packaging structure.

[0023] In some embodiments of this disclosure, the second semiconductor unit and the memory chip are flip-chip packaged on the substrate.

[0024] In this embodiment, the flip-chip mounting of the second semiconductor unit and the memory chip helps to improve the integration of the package structure and reduce the overall size of the package structure.

[0025] In some embodiments of this disclosure, the stacking height of the second semiconductor unit and the functional module is less than or equal to the height of the memory chip.

[0026] In the packaging structure provided in this embodiment, by setting the stacking height of the second semiconductor unit and the functional module to be less than or equal to the height of the memory chip, the space utilization rate inside the packaging structure can be improved on the basis of the same packaging size, while increasing the memory bandwidth.

[0027] According to a second aspect of this disclosure, a chip is provided, including the packaging structure described in the first aspect.

[0028] The chip in this embodiment is provided with the packaging structure described in the first aspect, which can improve the internal utilization rate of the chip while keeping the chip size unchanged, thereby improving chip performance.

[0029] According to a third aspect of this disclosure, an electronic device is provided, including a packaging structure as described in the first aspect or a chip as described in the second aspect.

[0030] The electronic device in this embodiment is provided with a first-aspect packaging structure or a second-aspect chip. Since more functions are integrated without increasing the chip size, it is beneficial to the miniaturization of the electronic device, reducing costs and improving device performance.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the present invention.

[0033] Figure 1 This is a top view of an encapsulation structure provided in an exemplary embodiment of this disclosure;

[0034] Figure 2 yes Figure 1 A side view of one type of packaging structure;

[0035] Figure 3 This is a top view of an encapsulation structure provided in another exemplary embodiment of this disclosure;

[0036] Figure 4 yes Figure 3 A side view of one type of packaging structure;

[0037] Figure 5 This is a top view of an encapsulation structure provided in another exemplary embodiment of this disclosure;

[0038] Figure 6 yes Figure 5 A side view of one type of packaging structure;

[0039] Figure 7 This is a side view of a storage module provided in an exemplary embodiment of this disclosure;

[0040] Figure 8 This is a top view of an encapsulation structure provided in another exemplary embodiment of this disclosure;

[0041] Figure 9 yes Figure 8 A side view of one type of packaging structure;

[0042] Figure 10 This is a top view of an encapsulation structure provided in another exemplary embodiment of this disclosure;

[0043] Figure 11 yes Figure 10 A side view of one type of packaging structure.

[0044] In the picture:

[0045] 100. Packaging structure; 101. First semiconductor unit; 102. Second semiconductor unit; 103. Functional module; 104. Storage module; 105. Third semiconductor unit; 106. Substrate; 107. Memory chip; 108. First adhesive layer; 109. Second adhesive layer. Detailed Implementation

[0046] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims. It should also be understood that the term “and / or” as used herein refers to any or all possible combinations including one or more of the associated listed items.

[0047] With the development of semiconductor technology, chip manufacturing has approached its physical limits. Simultaneously, with the rise of artificial intelligence applications, the demand for high bandwidth, high computing power, low latency, and low power consumption is becoming increasingly stringent. One advanced packaging method in related technologies (such as chiplets) is based on a "separate-then-assemble" approach. This involves first separating chips with specific functions, then processing them using different manufacturing processes based on their functions, and finally integrating these multiple chips into a single integrated chip using advanced packaging technology.

[0048] In a chiplet architecture, a chip that originally performed multiple functions is typically broken down into several smaller chips with independent functions. These chips may include a central processing unit (CPU), a graphics processing unit (GPU), a physical layer (PHY), and input / output (I / O) interfaces, each manufactured using different processing technologies. For example, CPU and GPU chips can be manufactured using advanced processes to ensure better performance. After these multiple independent chips have been manufactured separately, they are then packaged together.

[0049] During the packaging process, chips are sometimes stacked. When the dimensions of two stacked chips differ significantly, excess physical space appears in the package structure. This excess space can negatively impact the packaging process, affecting yield. Furthermore, this extra space can make the packaged chip more susceptible to deformation and damage under external forces during subsequent use. To avoid these problems, dummy dies (devices without circuitry) are placed in the unused physical space to fill the gaps, resulting in low space utilization.

[0050] Based on this, this disclosure provides a packaging structure including a first semiconductor unit, a second semiconductor unit, and at least one set of functional modules. The second semiconductor unit is stacked with the first semiconductor unit, and the size of the first semiconductor unit is smaller than the size of the second semiconductor unit. Along the stacking direction, the projection of the first semiconductor unit onto the second semiconductor unit falls into a first region of the second semiconductor unit. The second semiconductor unit includes a second region, which is offset from the first region. At least one set of functional modules is stacked with the second semiconductor unit. Along the stacking direction, the functional modules are disposed in the second region, and the functional modules are used to implement preset functions. In the packaging structure provided in this embodiment, the size difference between the two stacked semiconductor units creates some unused physical space between them. By placing functional modules with preset functions in this unused physical space, the adverse effects of the unused physical space on the packaging structure can be avoided, and the space utilization rate inside the packaging structure can be improved.

[0051] like Figures 1-4 As shown, an exemplary embodiment of this disclosure provides a packaging structure 100, including a first semiconductor unit 101, a second semiconductor unit 102, and at least one set of functional modules 103. In one example, the first and second semiconductor units can be bare dies, that is, semiconductor structures (i.e., dies) cut from a wafer and configured with integrated circuit functions but not yet packaged. These are then packaged using the packaging structure of this embodiment to form a finished chip. In another example, the first and second semiconductor units can be packaged finished chips, each with different independent functions. These are then packaged using the packaging structure of this embodiment to form a system-on-a-chip (SOC), which can integrate multiple independent functions. The functional modules can be bare dies or chips with preset functions, such as storage functions, power supply functions, passive electrical modules, etc.

[0052] The second semiconductor unit 102 is stacked with the first semiconductor unit 101. The size of the first semiconductor unit 101 is smaller than the size of the second semiconductor unit 102. Along the stacking direction, the projection of the first semiconductor unit 101 onto the second semiconductor unit 102 falls into a first region of the second semiconductor unit 102. The second semiconductor unit 102 includes a second region, which is offset from the first region. At least one set of functional modules 103 is stacked with the second semiconductor unit 102. Along the stacking direction, the functional modules 103 are disposed in the second region, and the functional modules 103 are used to implement preset functions.

[0053] In one embodiment, both the first semiconductor unit and the second semiconductor unit are bare dies. The first semiconductor unit 101 can be a Top Die (i.e., a bare die disposed on the top layer), and the second semiconductor unit 102 can be a Bottom Die (i.e., a bare die disposed on the bottom layer). Figure 1 and Figure 2 The diagram shows a first semiconductor unit 101 as a top die and a second semiconductor unit 102 as a bottom die. Figure 1 and Figure 2 In the middle, along the stacking direction, that is Figure 2 In the vertical direction, at least one set of functional modules 103 is disposed above the second semiconductor unit 102.

[0054] In another embodiment, the second semiconductor unit 102 can be a top die, and the first semiconductor unit 101 can be a bottom die. Figure 3 and Figure 4 The diagram shows a second semiconductor unit 102 as a top die and a first semiconductor unit 101 as a bottom die. Figure 3 and Figure 4 In the middle, along the stacking direction, that is Figure 4 In the vertical direction, at least one set of functional modules 103 is disposed below the second semiconductor unit 102.

[0055] The projection of the first semiconductor unit 101 onto the second semiconductor unit 102 falls into the first region of the second semiconductor unit 102. Other chips or dies may be disposed between the first semiconductor unit 101 and the second semiconductor unit 102, or no other chips or dies may be disposed. This disclosure does not impose any limitations.

[0056] In the packaging structure provided in this embodiment, there is a size difference between the two stacked semiconductor units. The size difference will create some empty physical space between the two semiconductor units. By setting a functional module with preset function in the empty physical space, it is possible to avoid the adverse effects of the empty physical space on the packaging structure and improve the space utilization rate inside the packaging structure.

[0057] In some embodiments, the packaging structure 100 may include a set of functional modules 103, see [link to documentation]. Figure 1-4 As shown. Based on the design requirements of the packaging structure 100, a set of functional modules 103 can be set up, and virtual dies can be used to physically fill the remaining space in the empty physical space formed by the size difference between the first semiconductor unit 101 and the second semiconductor unit 102. The functional modules 103 may include a storage module 104 for implementing storage functions, a power supply module, or a passive electrical module, etc.

[0058] In other embodiments, the encapsulation structure 100 may include multiple sets of functional modules 103, see [link to relevant documentation]. Figures 5-9 As shown. (Refer to...) Figure 5 As shown, a set of functional modules 103 is arranged below the first semiconductor unit 101, and two sets of functional modules 103 are arranged vertically on the right side of the first semiconductor unit 101. (Refer to...) Figure 8 As shown, a set of functional modules 103 is arranged below the first semiconductor unit 101, and another set of functional modules 103 is arranged to the right of the first semiconductor unit 101. The functions of the multiple sets of functional modules 103 may be the same or different. For example, the functional modules 103 may be a storage module 104, a power supply module, or a passive electrical module, etc.

[0059] Multiple functional modules 103 can be configured according to the design requirements of the packaging structure 100. These multiple functional modules 103 can fill the empty physical space formed by the size difference between the first semiconductor unit 101 and the second semiconductor unit 102, or they can use virtual dies to physically fill the remaining space in the empty physical space formed by the size difference between the first semiconductor unit 101 and the second semiconductor unit 102. The number of functional modules 103 can be determined according to the design requirements and the size of the empty physical space formed by the size difference between the first semiconductor unit 101 and the second semiconductor unit 102, as well as the design size of the functional modules 103; this disclosure does not impose specific limitations.

[0060] The multiple functional modules 103 include at least one set of storage modules 104 for implementing storage functions. The storage modules 104 can be disposed at any position on the second region of the second semiconductor unit 102. The storage module 104 includes at least one third semiconductor unit 105, as shown in Figure 7. The third semiconductor unit 105 may, for example, include a DDR (Double Data Rate) DIE for enhancing the storage function of the package structure 100.

[0061] Figures 5-11 The diagram schematically illustrates a configuration where the first semiconductor unit 101 is a top die, the second semiconductor unit 102 is a bottom die, and multiple functional modules 103 are positioned above the second semiconductor unit 102. It can be understood that the second semiconductor unit 102 can be a top die, the first semiconductor unit 101 can be a bottom die, and the multiple functional modules 103 can be positioned below the second semiconductor unit 102.

[0062] The encapsulation structure provided in this embodiment can include multiple sets of functional modules, which can be used to implement different functions, thereby improving the functionality of the encapsulation structure from multiple aspects simultaneously. At least one set of functional modules is a storage module used to implement storage functions, thereby ensuring the functionality of the encapsulation structure while increasing the bandwidth and storage performance of the encapsulation structure.

[0063] In some embodiments, the storage module 104 includes a third semiconductor unit 105, which may include a DDR die. One DDR die corresponds to one channel of the DDR chip formed by the storage module 104.

[0064] In other embodiments, reference is made to... Figure 7 The storage module 104 includes a plurality of third semiconductor units 105, which are stacked and adjacent third semiconductor units 105 are insulated from each other. Each third semiconductor unit 105 may include a DDR die, which are insulated from each other and stacked. The number of DDR dies in the storage module 104 corresponds to the number of channels in the DDR chips formed by the storage module 104. Therefore, the inclusion of a plurality of third semiconductor units 105 in the storage module 104 can expand the storage performance of the storage module 104 and improve the bandwidth of the package structure 100. Figure 7 The diagram schematically illustrates three third semiconductor units 105. The number of third semiconductor units 105 can be determined according to design requirements and the design dimensions of the functional module 103 and the dimensions of the third semiconductor units 105; this disclosure does not impose specific limitations. It is understood that the functional module 103 can be designed based on the number of memory channels.

[0065] In this embodiment, the storage module may include multiple third semiconductor units stacked together, so that the number of third semiconductor units can be selected according to the amount of available physical space and the storage performance to be expanded, thus making reasonable use of the internal space of the functional module.

[0066] In some embodiments, adjacent third semiconductor units are bonded together. Adjacent third semiconductor units may be bonded together, for example, by a die-attach film (DAF), or by other means, which are not limited herein.

[0067] In this embodiment, multiple third semiconductor units are bonded together, which is a simple and reliable connection method that does not require complex processes. This not only results in high integration but also low cost.

[0068] In some embodiments, reference Figure 5 and Figure 8 As shown, multiple sets of functional modules 103 are disposed at different positions in the second region, and the multiple sets of functional modules 103 are staggered. The multiple sets of functional modules 103 are staggered in the second region of the second semiconductor unit 102. The functions of the multiple sets of functional modules 103 can be the same or different. For example, the functional module 103 can be a storage module 104, a power supply module, or a passive electrical module, etc.

[0069] In this embodiment, other chips or dies may be set between multiple groups of functional modules 103, or no other chips or dies may be set; this disclosure does not impose any limitations.

[0070] In this embodiment, multiple sets of functional modules can be arranged in various different distribution patterns according to the shape of the free physical space, which improves the diversity of the internal layout of the packaging structure. At the same time, the staggered arrangement of multiple sets of functional modules can reduce interference through physical isolation and optimize space utilization.

[0071] According to an exemplary embodiment, such as Figures 8-11 As shown, the packaging structure 100 also includes a substrate 106 and a memory chip 107, the substrate 106 and the memory chip 107 are stacked, the second semiconductor unit 102 is stacked with the substrate 106, and the second semiconductor unit 102 and the memory chip 107 are staggered.

[0072] Reference Figure 9 As shown, the second semiconductor unit 102 is offset from the memory chip 107 and positioned above the substrate 106. The substrate 106 is the core carrier of the package structure, responsible for the electrical interconnection, mechanical support, and heat dissipation functions of the package structure. The memory chip 107 may include, for example, a DDR chip to enhance the storage function of the package structure.

[0073] In this embodiment, other chips or dies may be disposed between the second semiconductor unit 102 and the memory chip 107, or no other chips or dies may be disposed; this disclosure does not impose any limitations.

[0074] Understandably, when the second semiconductor unit 102 is a top die and the first semiconductor unit 101 is a bottom die, at least one set of functional modules 103 is disposed below the second semiconductor unit 102 and between it and the substrate 105. Since the size of the second semiconductor unit 102 is larger than the size of the first semiconductor unit 101, when the second semiconductor unit 102 is a top die and the first semiconductor unit 101 is a bottom die, the first semiconductor unit 101 is located between the second semiconductor unit 102 and the substrate 105. Therefore, the spare physical space caused by the size difference between the first semiconductor unit 101 and the second semiconductor unit 102 is also between the second semiconductor unit 102 and the substrate 105, and is located on one side of the first semiconductor unit 101. Disposing of at least one set of functional modules 103 in this spare physical space can expand the functionality of the packaging structure.

[0075] In the packaging structure provided in this embodiment, the memory chip and the second semiconductor unit are both disposed on the substrate. They are staggered and distributed in different areas of the substrate, which effectively utilizes the space utilization inside the packaging structure and enables the packaging structure to have a variety of different functions.

[0076] According to an exemplary embodiment, such as Figure 11 As shown, the third semiconductor unit 105 is bonded to the second semiconductor unit 102 via the first adhesive layer 108, and adjacent third semiconductor units 105 are connected via the second adhesive layer 109. The third semiconductor unit 105 is connected to the substrate 106 by wire bonding, and the thickness h1 of the second adhesive layer 109 is greater than the thickness h2 of the first adhesive layer 108.

[0077] The first adhesive layer 108 and the second adhesive layer 109 may both include DAF, and the first adhesive layer 108 and the second adhesive layer 109 may also be other adhesive materials. This embodiment does not impose specific limitations.

[0078] The third semiconductor unit 105 can be connected to the substrate 106 by wire bonding or other means, which is not limited in this disclosure. When the third semiconductor unit 105 is connected to the substrate 106 by wire bonding, the thickness h1 of the second adhesive layer 109 is set to be greater than the thickness h2 of the first adhesive layer 108, so that sufficient space can be reserved for the wiring between two adjacent third semiconductor units 105.

[0079] Figure 11 The diagram schematically shows two layers of third semiconductor units 105. In the packaging structure of this disclosure, multiple layers of third semiconductor units 105 can be provided. The number of third semiconductor units 105 can be determined according to the size of the storage module 104 and the size of the third semiconductor units 105. This disclosure does not make any specific limitation.

[0080] In this embodiment, the third semiconductor unit is connected to the substrate and the second semiconductor unit by adhesive bonding, which not only ensures high connection reliability but also reduces cost and facilitates processing. Meanwhile, since the third semiconductor unit is connected to the substrate by wire bonding, in order to ensure that there is enough space between two adjacent third semiconductor units for the wiring, the thickness of the second adhesive layer is set to be larger, thereby improving the reliability of the entire packaging structure.

[0081] According to an exemplary embodiment, the second semiconductor unit 102 and the memory chip 107 are flip-chip packaged on the substrate 106, wherein the flip-chip method includes either bonding or bump soldering. Alternatively, the second semiconductor unit 102 and the memory chip 107 can be packaged on the substrate 106 using a through-silicon via (TSV) method.

[0082] In this embodiment, the second semiconductor unit and memory chip can be packaged on the substrate in various ways. Bonding connection method is low-cost, highly flexible, and widely compatible. Bump soldering method can achieve high-density interconnection, excellent electrical performance, and facilitates heat dissipation. Furthermore, flip-chip mounting helps to improve the integration of the package structure and reduce the overall size of the package structure.

[0083] According to an exemplary embodiment, the stacking height H1 of the second semiconductor unit 102 and the functional module 103 is less than or equal to the height H2 of the memory chip 107.

[0084] In the packaging structure provided in this embodiment, by setting the stacking height of the second semiconductor unit and the functional module to be less than or equal to the height of the memory chip, the space utilization rate inside the packaging structure can be improved on the basis of the same packaging size, while increasing the memory bandwidth.

[0085] In some embodiments, the stacking height H1 of the second semiconductor unit 102 and the functional module 103 can be greater than the height H2 of the memory chip 107. This increases memory bandwidth by expanding the package size.

[0086] In one specific embodiment, refer to Figures 10-11 A packaging structure 100 is provided, including: a first semiconductor unit 101, a second semiconductor unit 102, three sets of functional modules 103, a substrate 106, and a memory chip 107. One set of functional modules 103 includes a storage module 104. The first semiconductor unit 101 is a top die, and the second semiconductor unit 102 is a bottom die.

[0087] For details, please refer to the following: Figure 11The storage module 104 includes two third semiconductor units 105, each containing a DDR die. The two DDR dies are connected by a DAF (Dielectric Atomizer), and the DDR dies are connected to the second semiconductor unit 102 by the DAF. Since the DDR dies are connected to the substrate 106 via wire bonding, the thickness h1 of the second adhesive layer 109 is greater than the thickness h2 of the first adhesive layer 108.

[0088] The number of DDR dies in storage module 104 corresponds to the number of channels in the DDR chips formed by storage module 104. In this embodiment, memory chip 107 is a 4-channel DDR chip. Therefore, by setting 2 DDR dies, it is equivalent to setting 2 channels of DDR chips, which can increase the DDR bandwidth by 50%.

[0089] Therefore, by setting up the DDR die within the space of the dummy die, space utilization can be improved while DDR bandwidth can be increased.

[0090] An exemplary embodiment of this disclosure also provides a chip including the above-described packaging structure.

[0091] The chip in this embodiment is provided with the above-mentioned packaging structure, which can improve the internal utilization rate of the chip while keeping the chip size unchanged, thus improving chip performance.

[0092] An exemplary embodiment of this disclosure also provides an electronic device, which includes the above-described packaging structure or the above-described chip. Examples of electronic devices include robots, mobile phones, laptops, tablets, wearable devices, servers, etc.

[0093] The electronic device in this embodiment is equipped with the above-mentioned packaging structure or the above-mentioned chip. Since more functions are integrated without increasing the chip size, it is beneficial to the miniaturization of electronic devices, reducing costs and improving device performance.

[0094] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0095] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0096] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the utility models disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0097] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A package structure, characterized by, include: First semiconductor unit; A second semiconductor unit is stacked with the first semiconductor unit. The size of the first semiconductor unit is smaller than the size of the second semiconductor unit. Along the stacking direction, the projection of the first semiconductor unit onto the second semiconductor unit falls into a first region of the second semiconductor unit. The second semiconductor unit includes a second region, which is offset from the first region. At least one set of functional modules is stacked with the second semiconductor unit. Along the stacking direction, the functional modules are disposed in the second region, and the functional modules are used to implement a preset function.

2. The package structure of claim 1, wherein, The packaging structure includes multiple sets of functional modules, including at least one set of storage modules for implementing storage functions, and the storage module includes at least one third semiconductor unit.

3. The package structure of claim 2, wherein, Multiple sets of the functional modules are set in different positions in the second area, and the multiple sets of the functional modules are staggered.

4. The package structure of claim 2, wherein, The storage module includes a plurality of third semiconductor units, which are stacked and adjacent third semiconductor units are insulated from each other.

5. The package structure of claim 4, wherein, Adjacent third semiconductor units are bonded together.

6. The package structure of claim 2, wherein, The packaging structure further includes a substrate and memory chips, wherein the substrate and the memory chips are stacked together, the second semiconductor unit is stacked together with the substrate, and the second semiconductor unit is staggered from the memory chips.

7. The package structure of claim 6, wherein, The third semiconductor unit is bonded to the second semiconductor unit through a first adhesive layer, and adjacent third semiconductor units are connected through a second adhesive layer. The third semiconductor unit is connected to the substrate by wire bonding, and the thickness of the second adhesive layer is greater than the thickness of the first adhesive layer.

8. The package structure of claim 6, wherein, The second semiconductor unit and the memory chip are packaged on the substrate using a flip-chip method.

9. The packaging structure according to claim 6, characterized in that, The stacking height of the second semiconductor unit and the functional module is less than or equal to the height of the memory chip.

10. A chip, characterized by Includes the packaging structure as described in any one of claims 1 to 9.

11. An electronic device, comprising: Includes the packaging structure as described in any one of claims 1 to 9, or the chip as described in claim 10.

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