A drive overvoltage and undervoltage protection circuit applied to an IGBT

Abstract

The utility model discloses a kind of drive overvoltage undervoltage protection circuit applied to IGBT, the emitter of the triode Q1 of this circuit, the first end of voltage division network circuit, the first end of stabilivolt D3 and the source of MOS tube Q2 are all commonly connected to VCC, the base of triode Q1, the first end of stabilivolt D1 and the first end of stabilivolt D2 are all commonly connected to VCC by protection resistance;The collector of triode Q1 is connected with the second end of voltage division network circuit, the second end of stabilivolt D3 and the gate of MOS tube Q2;The second end of stabilivolt D2 is connected with the base of triode Q3 by protection resistance;The drain of MOS tube Q2 is connected with the collector of triode Q3, the base of triode Q4, the collector of triode Q4 and the fourth pin of photocoupler isolation chip U1 by protection resistance, the second end of stabilivolt D1 is connected with the third end of voltage division network circuit, the emitter of triode Q3 and the emitter of triode Q4, and all ground connection.This application integrates overvoltage, undervoltage protection circuit, and drive voltage is too high or too low, and drive output is all closed.

Description

Technical Field

[0001] This utility model relates to the field of electronic device protection technology, and in particular to an overvoltage and undervoltage protection circuit for IGBTs. Background Technology

[0002] In power electronic systems, the drive voltage (typically +15V ± 10%) of an IGBT (Insulated Gate Bipolar Transistor) must be kept stable. Otherwise, undervoltage may occur, meaning that if the drive voltage is insufficient, the IGBT cannot be fully turned on, leading to increased conduction losses and even damage to the device due to overheating. Unstable IGBT drive voltage can also lead to overvoltage, meaning that if the drive voltage is too high, it may break down the IGBT gate oxide layer, causing permanent damage.

[0003] In practical applications, IGBTs are equipped with corresponding overvoltage and undervoltage protection circuits to prevent IGBT failure. However, existing protection circuits typically employ dedicated driver IC solutions, relying on specialized chips, which are costly and lack flexibility because some chips have fixed protection thresholds and cannot adapt to the driving requirements of different IGBTs. Alternatively, discrete comparator solutions can be used, but these require an additional reference voltage source, resulting in more complex circuitry and slower response times, making them ill-suited for handling transient voltage fluctuations. Furthermore, while the Zener diode in the protection circuit can clamp the circuit when the drive voltage is too high, excessively high power supplies can easily damage the Zener diode, rendering the protection circuit ineffective.

[0004] In the process of developing this utility model, the applicant discovered at least the following problems in the prior art:

[0005] The existing protection circuits cannot adequately meet the user's needs. Utility Model Content

[0006] The purpose of this invention is to provide an overvoltage and undervoltage protection circuit for IGBTs, thereby solving the technical problem that existing protection circuits cannot adequately meet user needs. The preferred technical solutions provided by this invention offer numerous advantages, which are detailed below.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] This utility model provides an overvoltage and undervoltage protection circuit for IGBTs, including a MOSFET Q2, a Zener diode D1, a Zener diode D2, a Zener diode D3, a transistor Q1, a transistor Q3, a transistor Q4, an optocoupler isolation chip U1, a voltage divider network circuit, and multiple protection resistors.

[0009] The emitter of transistor Q1, the first terminal of the voltage divider network circuit, the first terminal of Zener diode D3, and the source of MOSFET Q2 are all connected to VCC. The base of transistor Q1, the first terminal of Zener diode D1, and the first terminal of Zener diode D2 are all connected to VCC through the protection resistor. The collector of transistor Q1 is connected to the second terminal of the voltage divider network circuit, the second terminal of Zener diode D3, and the gate of MOSFET Q2. The second terminal of Zener diode D2 is connected to the base of transistor Q3 through the protection resistor. The drain of MOSFET Q2 is connected to the collector of transistor Q3, the base of transistor Q4, the collector of transistor Q4, and the fourth pin of optocoupler isolation chip U1 through the protection resistor. The second terminal of Zener diode D1 is connected to the third terminal of the voltage divider network circuit, the emitter of transistor Q3, and the emitter of transistor Q4, and all are grounded.

[0010] The optocoupler isolation chip U1 is connected to the PWM signal output terminal and the PWM signal input terminal. The optocoupler isolation chip U1 is used to isolate the control signal and the drive voltage.

[0011] Optionally, it also includes a transistor Q5 and a resistor R9. The base of the transistor Q5 is connected to the first end of the resistor R9, the second end of the resistor R9 is connected to the PWM signal input terminal, the collector of the transistor Q5 is connected to the second pin of the optocoupler isolation chip U1, and the emitter of the transistor Q5 is grounded.

[0012] Optionally, the first pin of the optocoupler isolation chip U1 is connected to a 5V voltage, the third pin of the optocoupler isolation chip U1 is grounded, and the fourth pin of the optocoupler isolation chip U1 is connected to the PWM signal output terminal.

[0013] Optionally, the plurality of protection resistors include resistors R1, R4, R5, R6, and R7. The first end of resistor R1 is connected to the emitter of transistor Q1, the first end of the voltage divider network circuit, the first end of the Zener diode D3, the source of MOSFET Q2, and VCC. The second end of resistor R1 is connected to the base of transistor Q1, the first end of Zener diode D1, and the first end of Zener diode D2. Resistor R4 is connected in series between the second end of Zener diode D2 and the base of transistor Q3. The first end of resistor R5 is connected to the drain of MOSFET Q2 and the first end of resistor R7. The second end of resistor R5 is connected to the collector of transistor Q3 and the first end of resistor R6. The second end of resistor R6 is connected to the base of transistor Q4. The second end of resistor R7 is connected to the collector of transistor Q4 and the fourth pin of the optocoupler isolation chip U1.

[0014] Optionally, the plurality of protection resistors further includes resistor R8, the first end of which is connected to the collector of transistor Q4 and the second end of resistor R7, and the second end of resistor R8 is connected to the fourth pin of optocoupler isolation chip U1 and the PWM signal output terminal.

[0015] Optionally, the voltage divider network circuit includes resistors R2 and R3 connected in series. The first terminal of the voltage divider network circuit is the first terminal of resistor R2. The second terminal of the voltage divider network circuit includes the second terminal of resistor R2 and the first terminal of resistor R3. The third terminal of the voltage divider network circuit is the second terminal of resistor R3.

[0016] Optionally, when the VCC is less than the set undervoltage threshold, the Zener diodes D1 and D2, transistor Q1 and Q3 are all off, and the MOSFET Q2 is either on or off. When the MOSFET Q2 is on, the transistor Q4 is on.

[0017] Optionally, when the VCC is between a preset undervoltage threshold and an overvoltage threshold, the Zener diode D1 is in the off state, the Zener diode D2, the MOSFET Q2 and the transistor Q3 are all turned on, and the transistor Q1 and the transistor Q4 are not turned on.

[0018] Meanwhile, when the PWM signal input terminal is high, both the transistor Q5 and the optocoupler isolation chip U1 are turned on; when the PWM signal input terminal is low, both the transistor Q5 and the optocoupler isolation chip U1 are not turned on.

[0019] Optionally, when the VCC is higher than a preset overvoltage threshold, the Zener diode D1, Zener diode D2, transistor Q1, and transistor Q3 are all turned on, while the MOSFET Q2 and transistor Q4 are turned off.

[0020] Optionally, transistor Q1 is a PNP transistor, and transistors Q3, Q4 and Q5 are all NPN transistors.

[0021] Implementing one of the above-described technical solutions of this utility model has the following advantages or beneficial effects:

[0022] This invention uses a protection circuit composed of multiple transistors, multiple Zener diodes, and MOSFETs to shut down the drive output when the drive voltage is too high or too low, thus preventing damage to the Zener diodes and achieving a more comprehensive protection effect. It also reduces the complexity of circuit design and manufacturing costs, and improves the reliability, safety, and flexibility of the protection circuit. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0024] Figure 1 This is a circuit schematic diagram of an embodiment of the present invention;

[0025] Figure 2 This is a circuit diagram of the undervoltage operating state according to an embodiment of the present invention;

[0026] Figure 3 This is a circuit diagram of the normal operating state of an embodiment of this utility model;

[0027] Figure 4 This is a circuit diagram of the overvoltage working state according to an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be adopted to implement this utility model. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of this utility model disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of this utility model.

[0029] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0030] To illustrate the technical solution described in this utility model, specific embodiments are described below, showing only the parts related to the embodiments of this utility model.

[0031] Example 1:

[0032] like Figure 1As shown, this utility model provides an overvoltage and undervoltage protection circuit for IGBTs, including a MOSFET Q2, a Zener diode D1, a Zener diode D2, a Zener diode D3, a transistor Q1, a transistor Q3, a transistor Q4, an optocoupler isolation chip U1, a voltage divider network circuit, and multiple protection resistors. The emitter of transistor Q1, the first terminal of the voltage divider network, the first terminal of Zener diode D3, and the source of MOSFET Q2 are all connected to VCC. The base of transistor Q1, the first terminal of Zener diode D1, and the first terminal of Zener diode D2 are all connected to VCC through a protective resistor. The collector of transistor Q1 is connected to the second terminal of the voltage divider network, the second terminal of Zener diode D3, and the gate of MOSFET Q2. The second terminal of Zener diode D2 is connected to the base of transistor Q3 through a protective resistor. The drain of MOSFET Q2 is connected to the collector of transistor Q3, the base of transistor Q4, the collector of transistor Q4, and the fourth pin of optocoupler chip U1 through a protective resistor. The second terminal of Zener diode D1 is connected to the third terminal of the voltage divider network, the emitter of transistor Q3, and the emitter of transistor Q4, and all are grounded. Optocoupler chip U1 is connected to both the PWM signal output and input terminals, and is used for isolation between the control signal and the drive voltage. Specifically, Zener diode D1 is used to set the overvoltage protection voltage threshold, which depends on the Zener voltage VZ of Zener diode D1. Zener diode D2 is used to set the undervoltage protection voltage threshold, and the lower voltage limit that allows the circuit to operate depends on the Zener voltage VZ of D2. In this embodiment, the Zener voltage VZ of Zener diode D1 is 17V, and the Zener voltage VZ of Zener diode D2 is 11.3V, thus setting the undervoltage threshold to 12V and the overvoltage threshold to 17V. The voltage divider network circuit is used to provide current limiting protection for Zener diode D3. The voltage difference between the gate and source of MOSFET Q2 is determined by the Zener voltage VZ of Zener diode D3. When the Zener voltage VZ of Zener diode D3 is 10V, the voltage difference VGS between the gate and source of MOSFET Q2 can be maintained at around 10V. Transistor Q1 is in the conducting state when the circuit is overvoltaged, thereby connecting the gate and source of MOSFET Q2 and turning off MOSFET Q2. The optocoupler isolation chip U1 is used to isolate the control signal and drive voltage to prevent VCC fluctuations from affecting the control signal circuit.

[0033] This invention uses a protection circuit composed of multiple transistors, multiple Zener diodes, and MOSFETs to shut down the drive output when the drive voltage is too high or too low, thus preventing damage to the Zener diodes and achieving a more comprehensive protection effect. It also reduces the complexity of circuit design and manufacturing costs, and improves the reliability, safety, and flexibility of the protection circuit.

[0034] As an optional implementation method, such as Figure 1As shown, the system also includes a transistor Q5 and a resistor R9. The base of transistor Q5 is connected to the first terminal of resistor R9, the second terminal of resistor R9 is connected to the PWM signal input terminal, the collector of transistor Q5 is connected to the second pin of optocoupler isolation chip U1, and the emitter of transistor Q5 is grounded. Specifically, resistor R9 is placed between the base of transistor Q5 and the PWM signal input terminal to limit the base current of transistor Q5.

[0035] As an optional implementation method, such as Figure 1 As shown, the first pin of the optocoupler isolation chip U1 is connected to a 5V voltage, the third pin is grounded, and the fourth pin is connected to the PWM signal output terminal. Specifically, the optocoupler isolation chip U1 receives the control signal through the PWM signal input terminal and outputs the control signal through the PWM signal output terminal. The optocoupler isolation chip U1 is used to isolate the control signal and the drive voltage to prevent VCC fluctuations from affecting the control signal circuit.

[0036] As an optional implementation method, such as Figure 1 As shown, multiple protection resistors include resistors R1, R4, R5, R6, and R7. The first end of resistor R1 is connected to the emitter of transistor Q1, the first end of the voltage divider network circuit, the first end of Zener diode D3, the source of MOSFET Q2, and VCC. The second end of resistor R1 is connected to the base of transistor Q1, the first end of Zener diode D1, and the first end of Zener diode D2. Resistor R4 is connected in series between the second end of Zener diode D2 and the base of transistor Q3. The first end of resistor R5 is connected to the drain of MOSFET Q2 and the first end of resistor R7. The second end of resistor R5 is connected to the collector of transistor Q3 and the first end of resistor R6. The second end of resistor R6 is connected to the base of transistor Q4. The second end of resistor R7 is connected to the collector of transistor Q4 and the fourth pin of optocoupler isolation chip U1. Specifically, resistor R1 is connected in series between the base of transistor Q1 and VCC. Resistor R1 limits the base current of transistor Q1, preventing excessive base current from damaging Q1. The formula for calculating the resistance value of resistor R1 is: Where VCC is the driving voltage, VZ is the Zener voltage of the Zener diode D1, and IB is the base current required by the transistor Q1. Resistor R4 is connected in series between the second terminal of the Zener diode D2 and the base of the transistor Q3. Resistor R4 is used to limit the base current of the transistor Q3, so that the transistor Q3 does not conduct when the driving voltage is too low, and conducts when the driving voltage reaches the undervoltage threshold. Resistor R5 is used for protection circuit when the transistor Q3 is conducting, resistor R7 is used for protection circuit when the transistor Q4 is conducting, and resistor R6 is used to limit the base current of the transistor Q4.

[0037] As an optional implementation method, such as Figure 1As shown, the multiple protection resistors also include resistor R8. The first terminal of resistor R8 is connected to the collector of transistor Q4 and the second terminal of resistor R7. The second terminal of resistor R8 is connected to the fourth pin of optocoupler isolation chip U1 and the PWM signal output terminal. Specifically, resistor R8 is used for current limiting to protect optocoupler isolation chip U1.

[0038] As an optional implementation method, such as Figure 1 As shown, the voltage divider network circuit includes resistors R2 and R3 connected in series. The first terminal of the voltage divider network circuit is the first terminal of resistor R2. The second terminal of the voltage divider network circuit includes the second terminal of resistor R2 and the first terminal of resistor R3. The third terminal of the voltage divider network circuit is the second terminal of resistor R3. Specifically, when the Zener diode D3 is not conducting, the voltage divider network circuit can divide the voltage proportionally. The formula for calculating the voltage difference VGS between the gate and source of MOSFET Q2 is: Where R2 is the resistance value of resistor R2 and R3 is the resistance value of resistor R3. By setting the ratio of resistor R2 and resistor R3, the voltage difference VGS between the gate and source of MOSFET Q2 is kept stable at around 10V.

[0039] As an optional implementation method, such as Figure 2As shown, when VCC is less than the set undervoltage threshold, Zener diodes D1 and D2, transistors Q1 and Q3 are all off, while MOSFET Q2 is either on or off. When MOSFET Q2 is on, transistor Q4 is on. Specifically, when VCC is less than the set undervoltage threshold of 12V, the IGBT is in an undervoltage operating state. Zener diode D2 is off, the base-emitter voltage VBE of transistor Q3 is less than 0.7V, there is no current at the base of transistor Q3, and transistor Q3 is off. Simultaneously, Zener diode D1 is also off, and the base and emitter potentials of transistor Q1 are the same, so transistor Q1 is off. The voltage difference VGS between the gate and source of MOSFET Q2 is determined by Zener diode D2, and when the voltage difference VGS between the gate and source of MOSFET Q2 is stable at 10V, MOSFET Q2 remains on. VCC reaches the base of transistor Q4 via MOSFET Q2, turning on Q4. VCC is grounded through resistor R7, and the PWM signal output is low, thus shutting down the drive output and protecting the IGBT. When VCC is less than 10V, Zener diodes D1 and D2, transistors Q1 and Q3 are all off, as are MOSFET Q2 and Zener diode D3. The voltage difference VGS between the gate and source of MOSFET Q2 depends on the voltage divider network. When resistor R2 is set to 1KΩ and resistor R3 to 500Ω, the voltage difference VGS between the gate and source of MOSFET Q2 is greater than VGS(th). When VCC is too low, the voltage difference VGS between the gate and source of MOSFET Q2 is too low to turn on Q2, turning it off and cutting off the power supply to the circuit. The PWM signal output is low.

[0040] As an optional implementation method, such as Figure 3As shown, when VCC is between the preset undervoltage threshold and overvoltage threshold, Zener diode D1 is in the off state, Zener diode D2, MOSFET Q2 and transistor Q3 are all turned on, and transistors Q1 and Q4 are not turned on. At the same time, when the PWM signal input terminal is high, transistor Q5 and optocoupler chip U1 are both turned on; when the PWM signal input terminal is low, transistor Q5 and optocoupler chip U1 are both turned off. Specifically, when VCC is between 12V and 17V, the IGBT is in normal operating condition. Zener diode D1 is cut off, and Zener diode D2 is turned on, with a voltage of 11.3V across it. When VCC is higher than 11.3V, the base-emitter voltage VBE of transistor Q3 gradually increases. Resistors R1 and R4 are chosen with relatively small resistance values, and their voltages are ignored. Current will only flow through the base of transistor Q3 when VCC is at least 12V, thus turning on Q3. The conduction of transistor Q3 pulls down the base potential of transistor Q4, thus preventing Q4 from conducting. Transistor Q1 is not conducting. Zener diode D3 maintains the voltage difference VGS between the gate and source of MOSFET Q2 at around 10V. MOSFET Q2 is continuously conducting. VCC passes through MOSFET Q2, resistor R7, and resistor R8 to the PWM signal output terminal. The PWM signal output terminal outputs a control signal with the same frequency as the PWM signal input terminal, and the voltage is maintained between 12V and 17V.

[0041] As an optional implementation method, such as Figure 4 As shown, when VCC exceeds the preset overvoltage threshold, Zener diodes D1 and D2, transistors Q1 and Q3 are all turned on, while MOSFETs Q2 and Q4 are turned off. Specifically, when VCC exceeds 17V, the IGBT is in overvoltage operation. Zener diodes D1 and D2 are both turned on, increasing the base current of transistor Q1. The emitter potential of transistor Q1 is higher than its base potential, causing Q1 to turn on. Because Q1 is turned on, the voltage difference VGS between the gate and source of MOSFET Q2 is zero, so MOSFET Q2 is turned off, and the protection current is not powered by VCC. At this time, transistor Q3 is turned on, and transistor Q4 is not turned on. However, since MOSFET Q2 is not turned on, the circuit still has no voltage output, and the PWM signal output terminal outputs a low level, disabling the drive output.

[0042] As an optional implementation, transistors Q1, Q3, Q4, Q5 and MOSFET Q2 can be selected from different types of transistors as needed. MOSFET Q2 can be a P-type MOSFET, transistor Q1 can be a PNP type transistor, and transistors Q3, Q4 and Q5 can all be NPN type transistors.

[0043] The embodiment is merely a special case and does not indicate that this utility model is implemented in such a way.

[0044] The above description is merely a preferred embodiment of the present utility model. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present utility model. Furthermore, under the teachings of the present utility model, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present utility model. Therefore, the present utility model is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present utility model.

Claims

1. A drive overvoltage and undervoltage protection circuit applied to an IGBT, characterized by, Includes MOSFET Q2, Zener diodes D1, D2, and D3, transistors Q1, Q3, and Q4, optocoupler isolation chip U1, voltage divider network circuit, and multiple protection resistors; The emitter of transistor Q1, the first terminal of the voltage divider network circuit, the first terminal of Zener diode D3, and the source of MOSFET Q2 are all connected to VCC. The base of transistor Q1, the first terminal of Zener diode D1, and the first terminal of Zener diode D2 are all connected to VCC through the protection resistor. The collector of transistor Q1 is connected to the second terminal of the voltage divider network circuit, the second terminal of Zener diode D3, and the gate of MOSFET Q2. The second terminal of Zener diode D2 is connected to the base of transistor Q3 through the protection resistor. The drain of MOSFET Q2 is connected to the collector of transistor Q3, the base of transistor Q4, the collector of transistor Q4, and the fourth pin of optocoupler isolation chip U1 through the protection resistor. The second terminal of Zener diode D1 is connected to the third terminal of the voltage divider network circuit, the emitter of transistor Q3, and the emitter of transistor Q4, and all are grounded. The optocoupler isolation chip U1 is connected to the PWM signal output terminal and the PWM signal input terminal. The optocoupler isolation chip U1 is used to isolate the control signal and the drive voltage.

2. The drive overvoltage and undervoltage protection circuit for an IGBT according to claim 1, characterized by, It also includes a transistor Q5 and a resistor R9. The base of the transistor Q5 is connected to the first end of the resistor R9, the second end of the resistor R9 is connected to the PWM signal input terminal, the collector of the transistor Q5 is connected to the second pin of the optocoupler isolation chip U1, and the emitter of the transistor Q5 is grounded.

3. The drive overvoltage and undervoltage protection circuit for an IGBT according to claim 2, characterized by, The first pin of the optocoupler isolation chip U1 is connected to a 5V voltage, the third pin of the optocoupler isolation chip U1 is grounded, and the fourth pin of the optocoupler isolation chip U1 is connected to the PWM signal output terminal.

4. The drive overvoltage undervoltage protection circuit for an IGBT according to claim 1, characterized by, The plurality of protection resistors include resistors R1, R4, R5, R6, and R7. The first end of resistor R1 is connected to the emitter of transistor Q1, the first end of the voltage divider network circuit, the first end of the Zener diode D3, the source of MOSFET Q2, and VCC. The second end of resistor R1 is connected to the base of transistor Q1, the first end of Zener diode D1, and the first end of Zener diode D2. Resistor R4 is connected in series between the second end of Zener diode D2 and the base of transistor Q3. The first end of resistor R5 is connected to the drain of MOSFET Q2 and the first end of resistor R7. The second end of resistor R5 is connected to the collector of transistor Q3 and the first end of resistor R6. The second end of resistor R6 is connected to the base of transistor Q4. The second end of resistor R7 is connected to the collector of transistor Q4 and the fourth pin of the optocoupler isolation chip U1.

5. The drive overvoltage undervoltage protection circuit for an IGBT according to claim 4, characterized by, The plurality of protection resistors also include resistor R8, the first end of which is connected to the collector of transistor Q4 and the second end of resistor R7, and the second end of resistor R8 is connected to the fourth pin of optocoupler isolation chip U1 and the PWM signal output terminal.

6. The drive overvoltage undervoltage protection circuit for IGBT according to claim 1, characterized by, The voltage divider network circuit includes resistors R2 and R3 connected in series. The first terminal of the voltage divider network circuit is the first terminal of resistor R2. The second terminal of the voltage divider network circuit includes the second terminal of resistor R2 and the first terminal of resistor R3. The third terminal of the voltage divider network circuit is the second terminal of resistor R3.

7. The drive overvoltage undervoltage protection circuit for IGBT according to claim 1, characterized by, When VCC is less than the set undervoltage threshold, Zener diodes D1, D2, Q1, and Q3 are all off, and MOSFET Q2 is either on or off. When MOSFET Q2 is on, MOSFET Q4 is on.

8. The drive overvoltage undervoltage protection circuit for IGBT according to claim 1, characterized by, When VCC is between the preset undervoltage threshold and overvoltage threshold, the Zener diode D1 is in the off state, the Zener diode D2, MOSFET Q2 and transistor Q3 are all turned on, and transistors Q1 and Q4 are not turned on. Meanwhile, when the PWM signal input terminal is high, both the transistor Q5 and the optocoupler isolation chip U1 are turned on; when the PWM signal input terminal is low, both the transistor Q5 and the optocoupler isolation chip U1 are not turned on.

9. The drive overvoltage undervoltage protection circuit for IGBT according to claim 1, wherein When the VCC is higher than the preset overvoltage threshold, the Zener diodes D1 and D2, transistor Q1 and Q3 are all turned on, while the MOSFET Q2 and transistor Q4 are turned off.

10. The drive overvoltage and undervoltage protection circuit for an IGBT according to any one of claims 1 to 9, characterized by, Transistor Q1 is a PNP type transistor, while transistors Q3, Q4, and Q5 are all NPN type transistors.

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