A low-voltage TVS with a deep groove structure

Abstract

This invention relates to the field of TVS fabrication technology, specifically a low-voltage TVS with a deep trench structure, comprising a silicon wafer with a front electrode and a back electrode on two sides. The front electrode includes two independently arranged sub-electrodes, each with a deep trench structure between them. An N-doped region is provided between the sub-electrodes and the silicon wafer, with an isolation layer on the top and outer periphery of the N-doped region. A lead hole is located at the center of the isolation layer, and a metal layer is provided on the lead hole. This invention uses deep trench isolation technology to fabricate the TVS, which can significantly reduce the chip area and lower the PN junction side capacitance. Simultaneously, it uses LPCVD silicon nitride as a passivation layer, which has higher density and stronger protection against metal and sodium ion contamination, greatly improving the reliability of the packaged chip. Furthermore, the reverse leakage current (IR) of this invention is reduced, the PN junction capacitance is lowered, and the temperature coefficient and radiation resistance are improved.

Description

Technical Field

[0001] This invention relates to the field of TVS preparation technology, specifically a low-pressure TVS with a deep groove structure. Background Technology

[0002] A TVS diode (Transient Voltage Suppressor Diode) is a semiconductor device used to protect electronic equipment from instantaneous high-voltage surges. With technological advancements, TVS diodes have been continuously improved, leading to the development of TVS diodes with deep-groove structures. Deep-groove TVS diodes, through deep-groove etching and filling doping processes, form a vertical and three-dimensional junction area, significantly increasing the junction area and discharge capability compared to traditional planar TVS diodes. Deep-groove TVS diodes are suitable for applications requiring high protection performance, such as high-frequency communication interfaces, high-speed data transmission lines, and low-voltage integrated circuit protection.

[0003] The existing technology has the following problems: 1. The isolation effect of the deep trench isolation structure is not good, and there are problems such as leakage and insufficient safety performance; 2. Traditional processes usually require four etchings when preparing TVS with deep trench isolation structures, which is a long process and has high operating costs. Utility Model Content

[0004] The purpose of this invention is to solve the existing problems and provide a low-voltage TVS with a deep trench structure, which can form a deep trench structure with an isolation layer at the negative electrode position, effectively reducing the chip area and reducing the side capacitance of the PN junction.

[0005] To solve the above-mentioned technical problems, the technical solution provided by this utility model is as follows:

[0006] A low-voltage TVS with a deep trench structure includes a silicon wafer, wherein the two sides of the silicon wafer are a front electrode and a back electrode, respectively.

[0007] The front electrode includes two independently arranged sub-electrodes, and a deep groove structure is provided between each sub-electrode.

[0008] An N-doped region is provided between the electrode and the silicon wafer. An isolation layer is provided on the top and outer periphery of the N-doped region. A lead hole is provided at the center of the isolation layer, and a metal layer is provided on the lead hole.

[0009] As an improvement, the back electrode covers the entire back side of the silicon wafer and is made of silver; the metal layer is made of aluminum alloy, and the isolation layer consists of a silicon dioxide layer and a silicon nitride layer from bottom to top.

[0010] As an improvement, the thickness of the silicon dioxide layer is 0.5 μm.

[0011] As an improvement, the silicon nitride layer has a thickness of 0.1 μm.

[0012] As an improvement, the thickness of the metal layer is 2.5 micrometers.

[0013] As an improvement, the depth of the deep groove structure is 2-4 μm.

[0014] The advantages of this utility model are:

[0015] This invention employs deep trench isolation technology to fabricate TVS, resulting in a smaller chip footprint and significantly reduced chip area and PN junction side capacitance. Simultaneously, it utilizes LPCVD silicon nitride as a passivation layer. Compared to PECVD silicon nitride protective layers, LPCVD silicon nitride films have higher density and stronger protection against metal and sodium ion contamination, greatly improving the reliability of the packaged chip. Furthermore, this invention reduces reverse leakage current (IR), lowers PN junction capacitance, and improves temperature coefficient and radiation resistance. Attached Figure Description

[0016] Figure 1 This is a structural diagram of a low-pressure TVS with a deep groove structure in Example 1.

[0017] Figure 2 This is a flowchart of the preparation process of this utility model.

[0018] Figure 3 This is a structural diagram of the product after step S3 of the preparation process of this utility model.

[0019] Figure 4 This is a structural diagram of the product after step S4 of the preparation process of this utility model.

[0020] Figure 5 This is a structural diagram of the product after step S5 of the preparation process of this utility model.

[0021] Figure 6 This is a structural diagram of the product after step S6 of the preparation process of this utility model.

[0022] Figure 7 This is a structural diagram of the product after step S7 of the preparation process of this utility model.

[0023] Figure 8 This is a structural diagram of the product after step S8 of the preparation process of this utility model.

[0024] Figure 9 This is a structural diagram of the product after step S10 of the preparation process of this utility model.

[0025] Figure 10 This is a structural diagram of the product after step S12 of the preparation process of this utility model.

[0026] The image shows:

[0027] 1-Silicon wafer, 2-Back electrode, 3-Sub-electrode, 4-Deep trench structure, 4-N-doped region, 5-Isolation layer, 51-Silicon dioxide layer, 52-Silicon nitride layer, 6-Lead hole, 7-Metal layer. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Example 1

[0030] This embodiment discloses a low-voltage TVS with a deep trench structure, including a silicon wafer 1, with a front electrode and a back electrode 2 on both sides of the silicon wafer 1.

[0031] The front electrode includes two independently arranged sub-electrodes 3, with a deep groove structure 4 between each sub-electrode 3.

[0032] An N-doped region 4 is provided between the electrode 3 and the silicon wafer 1. An isolation layer 5 is provided on the top and outer periphery of the N-doped region 4. A lead hole 6 is provided at the center of the isolation layer 5. A metal layer 7 is provided on the lead hole 6.

[0033] The back electrode 2 covers the entire back side of the silicon wafer 1 and is made of silver; the metal layer 7 is made of aluminum alloy; and the isolation layer 5 consists of a silicon dioxide layer 51 and a silicon nitride layer 52 from bottom to top.

[0034] To facilitate full understanding, this utility model also discloses a method for manufacturing a low-voltage TVS with a deep groove structure, as a structural manufacturability supplement to this utility model, comprising the following steps:

[0035] S1. Provide a P substrate; the P substrate has a crystal orientation of P(100), a resistivity of 4 mΩ·cm, and a thickness of 675 μm; the surface of the P substrate is cleaned.

[0036] S2. A silicon dioxide layer is grown on the front side of the P substrate; the thickness of the silicon dioxide layer is 0.05 μm.

[0037] S3. An N+ phosphorus diffusion layer is grown on the front side with an implantation energy of 90 KeV and an implantation dose of E15 / cm2 to form an N-type doped region;

[0038] S4. Using the first photomask, perform deep trench etching on the photolithographic area on the front side of the silicon wafer using wet etching. The N-doped negative electrode in the TVS diode is formed through deep trench etching. The etching targets are silicon dioxide, N+ phosphorus diffusion layer and silicon on the surface of the silicon wafer. The etching steps include: coating, photolithography, development, hardening, wet etching and resist removal. The depth of etching the oxide layer is 0.15μm and the depth of etching the silicon is 2-4μm. At the same time, the dicing groove positions are etched to form independent N-doped regions on the surface of the silicon wafer.

[0039] S5. After removing the adhesive from the silicon wafer obtained in S4, use a wet etching process to remove all oxide layers; the etching solution used for wet etching is hydrofluoric acid.

[0040] S6. After removing the oxide layer, a silicon dioxide layer is grown on the silicon wafer surface to cover the deep trench structure and the N-doped region; the thickness of the silicon dioxide layer is 0.5 μm.

[0041] S7. A silicon nitride layer is formed on the surface of the silicon dioxide layer generated in S6 using a vapor deposition method; in this embodiment, a low-pressure chemical vapor deposition method is used, and the thickness of the deposited silicon nitride layer is 0.1 μm.

[0042] S8. Using a second photomask, etch the silicon nitride and silicon dioxide layers to create scribe lines and lead holes, so that the N-doped region is isolated by the silicon nitride and silicon dioxide layers; the etching method is dry etching.

[0043] S9. Deposit aluminum metal at the lead hole using a metal deposition process;

[0044] S10. Using the third mask, wet etching is performed on the aluminum layer deposited in S9. The aluminum layer is 2.5 μm thick, and wet etching is used. After etching, the aluminum is placed on the front side of the silicon wafer and used as the front electrode.

[0045] S11. Perform an alloying process on the front side of the silicon wafer. The specific method of the alloying process is as follows: raise the furnace temperature to 430°C, introduce a synthesis gas of nitrogen and hydrogen into the diffusion furnace, and form an alloy on the surface of the silicon wafer. The ratio of nitrogen to hydrogen in the synthesis gas is 9:1.

[0046] S12. After the silicon wafer is thinned by 100-150μm, metallic silver is evaporated onto the back side of the silicon wafer using an evaporation stage to form a back electrode.

[0047] The above are merely preferred embodiments of this utility model, but the scope of protection of this utility model is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this utility model, based on the technical solution and inventive concept of this utility model, should be included within the scope of protection of this utility model.

Claims

1. A low-voltage TVS with a deep groove structure, characterized in that, Includes a silicon wafer, wherein the two sides of the silicon wafer are a front electrode and a back electrode, respectively; The front electrode includes two independently arranged sub-electrodes, and a deep groove structure is provided between each sub-electrode. An N-doped region is provided between the electrode and the silicon wafer. An isolation layer is provided on the top and outer periphery of the N-doped region. A lead hole is provided at the center of the isolation layer, and a metal layer is provided on the lead hole.

2. A low-voltage TVS with a deep groove structure according to claim 1, characterized in that, The back electrode covers the entire back side of the silicon wafer and is made of silver; the metal layer is made of aluminum alloy; and the isolation layer consists of a silicon dioxide layer and a silicon nitride layer from bottom to top.

3. A low-voltage TVS with a deep groove structure according to claim 2, characterized in that, The thickness of the silicon dioxide layer is 0.5 μm.

4. A low-voltage TVS with a deep groove structure according to claim 2, characterized in that, The silicon nitride layer is 0.1 μm thick.

5. A low-voltage TVS with a deep groove structure according to claim 2, characterized in that, The thickness of the metal layer is 2.5 micrometers.

6. A low-voltage TVS with a deep groove structure according to claim 2, characterized in that, The depth of the deep groove structure is 2-4 μm.

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