Vehicle-mounted high-definition video transmission high-power charging circuit

Abstract

The utility model discloses a kind of vehicle-mounted high-definition video transmission high-power charging circuit, it includes: MQS connector;LED driver, with LED being connected, and LED driver connects MQS connector;Power surge protection module, it connects MQS connector;Anti-reverse circuit module, it connects the output end of power surge protection module;DC-DC controller module, it connects the output end of anti-reverse circuit module;TYPE-C interface, it is connected with DC-DC controller module;USB signal demultiplexer, it connects TYPE-C interface;ADI high-speed differential transceiver module, it connects USB signal demultiplexer and is used to convert parallel video signal into serial differential signal;DC-DC power module, it is connected between MQS connector and ADI high-speed differential transceiver module;Fakra connector, it connects ADI high-speed differential transceiver module to output serial differential signal.

Description

Technical fields:

[0001] This utility model relates to the field of vehicle electronic circuit technology, and specifically to a vehicle-mounted high-definition video transmission high-power charging circuit. Background technology:

[0002] Patent application number 202422297479.1 discloses a USB charging module for in-vehicle fast charging, belonging to the technical field of charging module technology. To solve the technical problem of damage to the fast charging module due to the lack of input protection during charging and the risk of damage if the positive and negative terminals are reversed, the technical solution includes a power input terminal, a rectifier and filter module, a step-down converter module, and an output interface. The power input terminal obtains external AC power and inputs it to the rectifier and filter module, which outputs a first DC power. The step-down converter module receives the first DC power and is connected to the output interface to provide charging power. The step-down converter module is also connected to the first DC power through an input power protection module. This design offers the following advantages: installation of the charging module does not require consideration of positive and negative terminals, improving the reliability of assembly and connection; and it provides multiple interfaces for easy adaptation.

[0003] However, the aforementioned USB charging module for in-vehicle fast charging has the following shortcomings:

[0004] At the moment the power input is connected, a transient high voltage will appear at the front end of the rectifier and filter module, causing a large surge current to flow through the rectifier and filter module and the buck converter module, which can easily damage the power devices downstream of the buck converter module. Furthermore, the USB charging module in the aforementioned vehicle fast charger only has charging functionality and cannot achieve high-definition video transmission, thus failing to meet consumer requirements.

[0005] In view of the above, the inventors propose the following technical solution. Utility Model Content:

[0006] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a vehicle-mounted high-definition video transmission and high-power charging circuit.

[0007] To solve the above-mentioned technical problems, this utility model adopts the following technical solution: The vehicle-mounted high-definition video transmission high-power charging circuit includes: an MQS connector; an LED driver connected to an LED, and the LED driver is connected to the PWM terminal of the MQS connector; a power surge protection module connected to the MQS connector; a reverse protection circuit module connected to the output terminal of the power surge protection module; a DC-DC controller module connected to the output terminal of the reverse protection circuit module and used to output high-power charging voltage and current; and a TYPE-C interface for inputting and outputting video signals and for high-power charging, which is connected to the DC-DC controller module. The Type-C controller module connects to and receives the high-power charging voltage and current output from the DC-DC controller module; the USB signal demultiplexer connects to the Type-C interface and is used to receive video signals input from the Type-C interface; the ADI high-speed differential transceiver module connects to the USB signal demultiplexer and is used to convert parallel video signals into serial differential signals; the DC-DC power supply module connects between the MQS connector and the ADI high-speed differential transceiver module and is used to power the ADI high-speed differential transceiver module; and the Fakra connector connects to the ADI high-speed differential transceiver module to output serial differential signals.

[0008] Furthermore, in the above technical solution, the LED driver includes a resistor R11, a capacitor C20, a dual-series-connected switching diode D3, a resistor R8, a resistor R9, a resistor R13, and a resistor R14. The LEDs include LED1 and LED2. One end of the resistor R11, the capacitor C20, and the dual-series-connected switching diode D3 are all connected to the PWM terminal of the MQS connector. The other end of the resistor R11 and the capacitor C20 is grounded. The other end of the dual-series-connected switching diode D3 is connected to the resistor R8 and the resistor R9. The resistor R8, the resistor R9, and LED1 are connected in series and then grounded. The resistor R13, the resistor R14, and LED2 are connected in series and then grounded.

[0009] Furthermore, in the above technical solution, the power surge protection module includes a TVS diode D2, whose two ends are respectively connected to the VI+ terminal and GND terminal of the MQS connector, and connected to the input terminal of the anti-reverse circuit module.

[0010] Furthermore, in the above technical solution, the anti-reverse circuit module includes a Schottky barrier rectifier D1, an inductor L2 connected to the cathode of the Schottky barrier rectifier D1, filter capacitors C8 and C9 connected in parallel, and filter capacitor C3 connected to the inductor L2. The anode of the Schottky barrier rectifier D1 is connected to the power surge protection module, and one end of the filter capacitors C8 and C9 is connected to the GND terminal of the MQS connector.

[0011] Furthermore, in the above technical solution, the DC-DC controller module includes a DC-DC controller and a filter network circuit and a charging output circuit connected to the DC-DC controller; the filter network circuit includes capacitors C4, C5, C6, and C7 connected in parallel, and a resistor R13 connected to capacitor C7. Resistor R13 is connected to the EN terminal of the DC-DC controller, and one end of capacitor C7 connected to resistor R13 is also connected to the VIN pin of the DC-DC controller; capacitor C4 is connected to the reverse protection circuit module; the charging output circuit includes a circuit connected to the OUT pin of the DC-DC controller. Resistor R7 and VBUS1 connected to resistor R7, capacitor C15 connected to the OUT pin of DC-DC controller, capacitors C16, C18, and C19 connected in parallel with both ends of resistor C15, capacitor C17 connected to the connection line between resistor R7 and VBUS1, and capacitors C13 and C14 connected in parallel with both ends of capacitor C17. One end of capacitors C16, C18, C19, C17, C13, and C14 connected in parallel with both ends of resistor C15 is connected to ground. VBUS1 is also connected to TVS diode D4 for overvoltage protection and then grounded.

[0012] Furthermore, in the above technical solution, the DC-DC controller is a DC-DC control chip of model MPQ4243. The DC-DC control chip internally has an alternately conducting high-side switch SW1 and a low-side switch SW2. The high-side switch SW1 is connected to ground after being connected to resistor R2 and capacitor C2, and the low-side switch SW2 is connected to ground after being connected to resistor R5 and capacitor C10. The high-side switch SW1 is also connected to inductor L1 and then to resistor R5. The BST1 pin of the DC-DC control chip is also connected to a first bootstrap circuit composed of resistor R1 and capacitor C1. The capacitor C1 also... Connecting resistor R2, pin BST2 of the DC-DC control chip is also connected to a second bootstrap circuit consisting of resistor R6 and capacitor C11, which is also connected to resistor R5. When the high-side switch SW1 is on, the input voltage VIN stores magnetic energy through inductor L1, and at this time, the low-side switch SW2 is off. When the high-side switch SW1 is off and the low-side switch SW2 is on, inductor L1 releases magnetic energy, which is filtered into a smooth voltage by capacitors C19, C18, C16, C15, C17, C13, and C14, providing a stable output to the VBUS1 terminal.

[0013] Furthermore, in the above technical solution, the DC-DC control chip is also connected to a current feedback overcurrent protection circuit. This current feedback overcurrent protection circuit includes resistors R15 and R16, as well as capacitors C12 and C23. One end of resistor R15 is connected to one end of resistor R7, and one end of resistor R16 is connected to the other end of resistor R7. Capacitor C12 is connected in parallel to one end of resistors R15 and R16, and capacitor C23 is connected in parallel to the other end of resistors R15 and R16. The other ends of resistors R15 and R16 are respectively connected to the ISENS+ and ISENS- pins of the DC-DC control chip.

[0014] Furthermore, in the above technical solution, the DC-DC power module includes a synchronous buck converter and a multi-channel synchronous buck converter. The input terminal of the synchronous buck converter is connected to the output terminal of the anti-reverse circuit module, and the synchronous buck converter has a 3V3 terminal that outputs 3.3V. The input terminal of the multi-channel synchronous buck converter is connected to the 3V3 terminal, and the multi-channel synchronous buck converter has a 1V8 terminal that outputs 1.8V respectively. Both the 3V3 terminal and the 1V8 terminal are connected to the ADI high-speed differential transceiver module to provide 3.3V and 1.8V voltages to the ADI high-speed differential transceiver module.

[0015] Furthermore, in the above technical solution, the ADI high-speed differential transceiver module includes an ADI high-speed differential transceiver chip of model MAX96749APGTN / VY+T. The ADI high-speed differential transceiver chip is connected to a single-channel XOR gate circuit, an interface ESD protection circuit, a low-frequency ripple circuit for suppressing power supply ripple, and a high-frequency ripple circuit for filtering high-frequency noise. The interface ESD protection circuit is connected to a Fakra connector, and the low-frequency ripple circuit and the high-frequency ripple circuit are respectively connected to the VDD terminal and the 1V8 terminal of the DC-DC power module.

[0016] Furthermore, in the above technical solution, there are multiple low-frequency ripple circuits, and each low-frequency ripple circuit includes a first ceramic capacitor and a second ceramic capacitor connected in parallel. One end of the first ceramic capacitor is connected to both the VDD terminal and a pin of the ADI high-speed differential transceiver chip, and the other end is grounded. There are also multiple high-frequency ripple circuits, and each high-frequency ripple circuit includes a third ceramic capacitor and a fourth ceramic capacitor connected in parallel. One end of the third ceramic capacitor is connected to both the VDD terminal and a pin of the ADI high-speed differential transceiver chip, and the other end is grounded. The interface ESD protection circuit includes an ESD protection diode D7. The cathode of the ESD protection diode D7 is connected to the MFP19 / LMN2 terminal of the ADI high-speed differential transceiver chip after connecting to resistor R48. The cathode of the ESD protection diode D7 is also connected to the SIOAN / SIOA terminal of the ADI high-speed differential transceiver chip after connecting to capacitor C28. The cathode of the ESD protection diode D7 is also connected to a Fakra connection. The device; the number of the single-channel XOR gate circuits is two, wherein the first single-channel XOR gate circuit includes a first single-channel XOR gate chip, the Y pin of the first single-channel XOR gate chip is connected to the 3V3 terminal after connecting to the resistor R23, the A pin of the first single-channel XOR gate chip is grounded, the B pin of the first single-channel XOR gate chip is connected to the MFP9 pin of the ADI high-speed differential transceiver chip, and the B pin of the first single-channel XOR gate chip is also connected to the VDDIO terminal after connecting to the resistor R21, and the VDDIO terminal is connected to the ADI high-speed differential transceiver chip. The high-speed differential transceiver chip; the second single-channel XOR gate circuit includes a second single-channel XOR gate chip. The Y pin of the second single-channel XOR gate chip is connected to the 3V3 terminal after being connected to the resistor R27. The A pin of the second single-channel XOR gate chip is connected to the MFP8 pin of the ADI high-speed differential transceiver chip. The B pin of the second single-channel XOR gate chip is connected to the VDDIO terminal. The VDDIO terminal is connected to the ADI high-speed differential transceiver chip. A resistor R25 is also connected between the B pin and the A pin of the second single-channel XOR gate chip.

[0017] By adopting the above technical solution, this utility model has the following beneficial effects compared with the prior art:

[0018] 1. This utility model adds a power surge protection module and a reverse circuit protection module. The power surge protection module can provide surge protection for the entire circuit, i.e., resist surge current and prevent downstream circuits from being damaged by reverse high voltage. The reverse circuit protection module is connected to the output terminal of the power surge protection module. This reverse circuit protection module is used to block reverse current and prevent damage to downstream circuits. In addition, this utility model can output high-power charging voltage and current to the TYPE-C interface through the DC-DC controller module to provide high-power charging for external devices connected to the TYPE-C interface.

[0019] 2. The USB signal demultiplexer dynamically switches the channel direction internally via an analog switch array to match the DFP / UFP role negotiation of Type-C, thereby meeting different usage requirements. For example, this invention can access video data through a TYPE-C interface. The USB signal demultiplexer dynamically switches the channel direction internally via an analog switch array, controlling the USB signal demultiplexer to receive the video signal input from the TYPE-C interface and send it to the ADI high-speed differential transceiver module. This ADI high-speed differential transceiver module is used to convert the parallel video signal into a serial differential signal and output the serial differential signal through the Fakra connector to meet different usage requirements. Attached image description:

[0020] Figure 1 This is a schematic diagram of the block diagram of this utility model;

[0021] Figure 2 This is the circuit diagram of the first part of this utility model;

[0022] Figure 3 This is the circuit diagram of the second part of this utility model;

[0023] Figure 4 This is the circuit diagram of the third part of this utility model;

[0024] Figure 5 This is the circuit diagram of the fourth part of this utility model;

[0025] Figure 6 This is the circuit diagram of the fifth part of this utility model. Detailed implementation method:

[0026] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0027] See Figure 1-6The diagram shows a high-power charging circuit for in-vehicle high-definition video transmission, comprising: an MQS connector 1 for connecting to a control box or other control device, used to output PWM signals and 12V DC voltage; an LED driver 2 connected to an LED, and connected to the PWM terminal of the MQS connector 1 to receive PWM signals, controlling the LED driver 2 to illuminate the LED; a power surge protection module 3 connected to the MQS connector 1, specifically to the 12VDC pin (VI+) of the MQS connector 1; this power surge protection module 3 protects the entire circuit from damage caused by reverse high voltage; and a reverse current protection module 4 connected to the output of the power surge protection module 3, used to block reverse current and prevent damage to downstream circuits. DC-DC controller module 5, connected to the output of anti-reverse circuit module 4, is used to output high-power charging voltage and current; TYPE-C interface 6, used for inputting and outputting video signals and external high-power charging, is connected to DC-DC controller module 5 and receives the high-power charging voltage and current output by DC-DC controller module 5; USB signal demultiplexer 7, connected to TYPE-C interface 6, is used to receive video signals input from TYPE-C interface 6; ADI high-speed differential transceiver module 8, connected to USB signal demultiplexer 7, is used to convert parallel video signals into serial differential signals; DC-DC power module 9, connected between MQS connector 1 and ADI high-speed differential transceiver module 8, is used to power ADI high-speed differential transceiver module 8; Fakra connector 10, connected to ADI high-speed differential transceiver module 8, outputs serial differential signals. This invention adds a power surge protection module 3 and a reverse protection circuit module 4. The power surge protection module 3 can provide surge protection for the entire circuit, that is, resist surge current and prevent downstream circuits from being damaged by reverse high voltage. The reverse protection circuit module 4 is connected to the output terminal of the power surge protection module 3. The reverse protection circuit module 4 is used to block reverse current and prevent damage to downstream circuits.Furthermore, this invention can output high-power charging voltage and current to the TYPE-C interface 6 through the DC-DC controller module 5 to provide high-power charging for external devices connected to the TYPE-C interface 6. Additionally, the USB signal demultiplexer 7 internally dynamically switches the channel direction (transmit / receive) via an analog switch array to match the DFP / UFP role negotiation (i.e., host / device mode) of the Type-C interface, meeting different usage requirements. For example, this invention can access video data through the TYPE-C interface 6. The USB signal demultiplexer 7 internally dynamically switches the channel direction (transmit / receive) via an analog switch array, controlling the USB signal demultiplexer 7 to receive the video signal input from the TYPE-C interface 6 and transmit it to the ADI high-speed differential transceiver module 8. This ADI high-speed differential transceiver module 8 is used to convert parallel video signals into serial differential signals and outputs the serial differential signal through the Fakra connector 10 to meet different usage requirements.

[0028] The LED driver 2 includes a resistor R11, a capacitor C20, a dual-series-connected switching diode D3, resistors R8, R9, R13, and R14. The LEDs include LED1 and LED2. One end of each of the resistors R11, C20, and D3 is connected to the PWM terminal of the MQS connector 1. The other end of the resistors R11 and C20 is grounded. The other end of the D3 is connected to resistors R8 and R9. Resistors R8, R9, and LED1 are connected in series and then grounded. Resistors R13 and R14 are connected in series and then grounded. During operation, when the PWM signal output from the PWM terminal is high, current flows through resistor R11, driving the dual-series-connected switching diode D3 to conduct. The cathodes of LED1 and LED2 are grounded, forming a circuit. At this time, LED1 and LED2 emit light, and the brightness is determined by the PWM duty cycle. When the PWM signal output from the PWM terminal is low, the dual-series-connected switching diode D3 is cut off, the circuit of LED1 and LED2 is broken, and they stop emitting light.

[0029] The power surge protection module 3 includes a TVS diode D2, whose two ends are respectively connected to the VI+ terminal and GND terminal of the MQS connector 1, and connected to the input terminal of the reverse protection circuit module 4. The power surge protection module 3 has the following two operating states:

[0030] 1. Normal operating condition (no surge): When the input voltage VI+ is within the normal range (far below 30V), the TVS diode D2 is in a high-impedance cutoff state, which is equivalent to an open circuit for the entire circuit and does not affect the normal power supply.

[0031] 2. Surge Protection Status: Scenario 1: Positive Surge. When a positive high-voltage pulse (above 30V) occurs on the VI+ line (i.e., the connection line where the VI+ terminal is located) due to interference, the TVS diode D2 quickly breaks down and conducts, providing a very low impedance path to ground for the transient surge current. The surge current is conducted to ground through D2, thereby forcibly clamping the voltage on the VI+ / CCA line to a safe lower voltage value (e.g., 48.4V), rather than the original high voltage value of the surge. Scenario 2: Negative Surge. When a negative high-voltage pulse occurs on the VI+ line relative to ground, the TVS diode D2 will also conduct, clamping the negative voltage to a safe negative voltage level (e.g., -48.4V), preventing subsequent circuits from being damaged by reverse high voltage.

[0032] The anti-reverse circuit module 4 includes a Schottky barrier rectifier D1, an inductor L2 connected to the cathode of the Schottky barrier rectifier D1, filter capacitors C8 and C9 connected in parallel, and filter capacitor C3 connected to the inductor L2. The anode of the Schottky barrier rectifier D1 is connected to the power surge protection module 3. The filter capacitors C8 and C9, and one end of the filter capacitor C8 are connected to the GND terminal of the MQS connector 1.

[0033] Inductor L2, filter capacitors C8, C9, and C3 form a filter network for three-stage filtering to purify the power supply. High-frequency interference: Filter C8 absorbs interference quickly through its low capacitive reactance, while inductor L2 suppresses high-frequency ripple propagation. Low-frequency ripple: Filter C3 (an electrolytic capacitor with large capacitance) smooths out slowly changing voltage fluctuations. The combined effect of inductor L2, filter capacitors C8, C9, and C3 covers a wide frequency band of 100Hz to 100MHz, ensuring a clean input power supply and improving the stability of the downstream circuitry.

[0034] The DC-DC controller module 5 includes a DC-DC controller 51, a filter network circuit 52 connected to the DC-DC controller 51, and a charging output circuit 53. The filter network circuit 52 includes capacitors C4, C5, C6, and C7 connected in parallel, and a resistor R13 connected to capacitor C7. Resistor R13 is connected to the EN terminal of the DC-DC controller 51. One end of capacitor C7 connected to resistor R13 is also connected to the VIN pin of the DC-DC controller 51. Capacitor C4 is connected to the anti-reverse circuit module 4. The charging output circuit 53 includes a resistor R connected to the OUT pin of the DC-DC controller 51. 7. The VBUS1 terminal 531 connected to resistor R7, capacitor C15 connected to the OUT pin of DC-DC controller 51, capacitors C16, C18, and C19 connected in parallel with both ends of resistor C15, capacitor C17 connected to the connection line between resistor R7 and VBUS1 terminal 531, and capacitors C13 and C14 connected in parallel with both ends of capacitor C17. One end of capacitors C16, C18, C19, C17, C13, and C14 connected in parallel with both ends of resistor C15 is connected to ground. The VBUS1 terminal 531 is also connected to a TVS diode D4 for overvoltage protection and then grounded. The VIN terminal is connected to the power supply after noise suppression by the filter network circuit 52 composed of capacitors C4, C5, C6, and C7.

[0035] The DC-DC controller 51 is an MPQ4243 DC-DC control chip. Internally, the DC-DC control chip has an alternately conducting high-side switch SW1 and a low-side switch SW2. The high-side switch SW1 is connected to ground via resistor R2 and capacitor C2, and the low-side switch SW2 is connected to ground via resistor R5 and capacitor C10. The high-side switch SW1 is also connected to inductor L1 and then to resistor R5. The BST1 pin of the DC-DC control chip is also connected to a first bootstrap circuit 511 composed of resistor R1 and capacitor C1. The first bootstrap circuit 511 provides a drive voltage to the high-side switch SW1 (the floating ground drive required to maintain the high-side switch conduction by charging the bootstrap capacitor). Capacitor C1 is also connected to resistor R2. The BST2 pin of this DC-DC control chip is also connected to a second bootstrap circuit 512 composed of resistor R6 and capacitor C11. The second bootstrap circuit 512 provides a drive voltage for the low-side switch SW2. Capacitor C11 is also connected to resistor R5. When the high-side switch SW1 is turned on, the input voltage VIN stores magnetic energy through inductor L1, and the low-side switch SW2 is turned off at this time. When the high-side switch SW1 is turned off and the low-side switch SW2 is turned on, the inductor L1 releases magnetic energy, which is filtered into a smooth voltage by capacitors C19, C18, C16, C15, C17, C13, and C14, and provides a stable output to the VBUS1 pin 531.

[0036] The DC-DC control chip is also connected to a current feedback overcurrent protection circuit 513. This circuit includes resistors R15 and R16, and capacitors C12 and C23. One end of resistor R15 is connected to one end of resistor R7, and one end of resistor R16 is connected to the other end of resistor R7. Capacitor C12 is connected in parallel to one end of resistors R15 and R16, and capacitor C23 is connected in parallel to the other end of resistors R15 and R16. The other ends of resistors R15 and R16 are connected to the ISENS+ and ISENS- pins of the DC-DC control chip, respectively. Current changes are detected through resistors R15 and R16 to achieve current feedback and overcurrent protection functions.

[0037] The DC-DC power module 9 includes a synchronous buck converter 91 and a multi-channel synchronous buck converter 92. The input terminal of the synchronous buck converter 91 is connected to the output terminal of the anti-reverse circuit module 4, and the synchronous buck converter 91 has a 3V3 terminal that outputs 3.3V. The input terminal of the multi-channel synchronous buck converter 92 is connected to the 3V3 terminal, and the multi-channel synchronous buck converter 92 has a 1V8 terminal that outputs 1.8V respectively. Both the 3V3 terminal and the 1V8 terminal are connected to the ADI high-speed differential transceiver module 8 to provide 3.3V and 1.8V voltages to the ADI high-speed differential transceiver module 8.

[0038] The synchronous buck converter 91 uses the MAX20402AFLB / VY+ signal. This converter converts a high input voltage (≤36V) to a stable 3.3V output, providing 3.3V power to the ADI high-speed differential transceiver module 8. The converter 91 is connected to an input filter circuit, which includes a high-frequency ceramic capacitor C67 and a low-frequency ceramic capacitor C68 connected in parallel. The high-frequency capacitor C67 is located near the VIN pin of the converter 91, filtering out high-frequency noise from the input voltage and reducing input ripple. The low-frequency capacitor C68, together with the high-frequency capacitor C67, forms a wideband filter to suppress low-frequency fluctuations in the input voltage, ensuring input voltage stability.

[0039] The synchronous buck converter 91 is connected to an energy storage inductor L5. When the internal switch of the synchronous buck converter 91 is turned on, the energy storage inductor L5 stores magnetic energy; when the switch is turned off, the energy storage inductor L5 releases energy to the output terminal, realizing buck conversion (volt-second balance principle).

[0040] The synchronous buck converter 91 is connected to an output filter capacitor C74, which is connected to the 3V3 terminal. This output filter capacitor C74 smooths the ripple of the switching frequency and maintains a stable output voltage through charging and discharging. The synchronous buck converter 91 integrates a synchronous rectifier MOSFET (high-side and low-side switch), and adjusts the output voltage by controlling the duty cycle through PWM. The synchronous buck converter 91 is connected to a pull-up resistor R46, which pulls the PGOOD signal up to 3V3. When the output voltage is normal, PGOOD outputs a high level for system power status monitoring. The synchronous buck converter 91 is also connected to a bias power supply filter capacitor C75, which filters out noise from the internal bias circuit of the chip, ensuring stable operation of the control circuit.

[0041] The multi-channel synchronous buck converter 92, model MAX20029BATID / V+, has an input of ≤5.5V and outputs of 1.8V and 1V, providing a low-voltage power rail for the ADI high-speed differential transceiver module 8.

[0042] The multi-channel synchronous buck converter 92 has four 2.2μF / 16V capacitors connected in parallel on the 3V3 terminal, significantly reducing input impedance, filtering out ripple and noise from the 3V3 power supply, and ensuring stable power supply to the chip. The multi-channel synchronous buck converter 92 is connected to an energy storage inductor L4, which is also connected to the 1V8 terminal, working with the internal switch of the multi-channel synchronous buck converter 92 to achieve a 1.8V step-down. The multi-channel synchronous buck converter 92 is connected to an output filter capacitor C72, which is also connected to the 1V8 terminal. This filter capacitor C72 is used to smooth the 1.8V ripple. The multi-channel synchronous buck converter 92 is connected to an energy storage inductor L3 and an output filter capacitor C66. The energy storage inductor L3 is connected to the VDD terminal, and the energy storage inductor L3, in conjunction with the internal switch of the multi-channel synchronous buck converter 92, achieves a 1.0V step-down. The output filter capacitor C66 effectively suppresses the 1.0V ripple.

[0043] The ADI high-speed differential transceiver module 8 includes an ADI high-speed differential transceiver chip 81 of model MAX96749APGTN / VY+T. The ADI high-speed differential transceiver chip 81 is used to convert parallel video signals into serial differential signals, supporting long-distance transmission. This ADI high-speed differential transceiver chip 81 is connected to a single-channel XOR gate circuit 82, an interface ESD protection circuit 83, a low-frequency ripple suppression circuit 84, and a high-frequency noise filtering circuit 85. The interface ESD protection circuit 83 is connected to a Fakra connector 10. The low-frequency ripple circuit 84 and the high-frequency ripple circuit 85 are respectively connected to the VDD terminal and the 1V8 terminal of the DC-DC power module 9.

[0044] The number of low-frequency ripple circuits 84 is multiple, and each low-frequency ripple circuit 84 includes a first ceramic capacitor 841 and a second ceramic capacitor 842 connected in parallel. One end of the first ceramic capacitor 841 is connected to both the VDD terminal and a pin of the ADI high-speed differential transceiver chip 81, and the other end is grounded. The first ceramic capacitor 841 and the second ceramic capacitor 842 are used to suppress low-frequency ripple of the power supply.

[0045] The number of high-frequency ripple circuits 85 is multiple, and each high-frequency ripple circuit 85 includes a third ceramic capacitor 851 and a fourth ceramic capacitor 852 connected in parallel. One end of the third ceramic capacitor 851 is connected to both the VDD terminal and a pin of the ADI high-speed differential transceiver chip 81, and the other end is grounded. The third ceramic capacitor 851 and the fourth ceramic capacitor 852 have small parasitic inductance, which filters out high-frequency noise.

[0046] The interface ESD protection circuit 83 includes an ESD protection diode D7. The cathode of the ESD protection diode D7 is connected to the MFP19 / LMN2 terminal of the ADI high-speed differential transceiver chip 81 via a resistor R48. The cathode of the ESD protection diode D7 is also connected to the SIOAN / SIOA terminal of the ADI high-speed differential transceiver chip 81 via a capacitor C28. Furthermore, the cathode of the ESD protection diode D7 is also connected to the Fakra connector 10. The interface ESD protection circuit 83 protects the Fakra connector 10 from electrostatic discharge (ESD) damage. ESD pulse: When ESD is introduced into J1 (i.e., the Fakra connector), the ESD protection diode D7 quickly conducts, clamping the voltage within a safe range.

[0047] There are two single-channel XOR gate circuits 82. The first single-channel XOR gate circuit 82 includes a first single-channel XOR gate chip 821. The Y pin of the first single-channel XOR gate chip 821 is connected to a 3V3 terminal after a resistor R23. The A pin of the first single-channel XOR gate chip 821 is grounded. The B pin of the first single-channel XOR gate chip 821 is connected to the MFP9 pin of the ADI high-speed differential transceiver chip 81. The B pin of the first single-channel XOR gate chip 821 is also connected to a VDDIO terminal after a resistor R21. The VDDIO terminal is connected to the ADI high-speed differential transceiver chip 81. Input: A is connected to the MFP9 of the MAX96749, and B is connected to 3V3. Power supply: VCC is connected to VDDIO. Function: If MFP9 = 0 (low level), then Y = 0 ⊕ 1 = 1 (high level); if MFP9 = 1, then Y = 0. The first single-channel XOR gate circuit 82 implements logic level conversion by XORing the state of the MFP with a fixed level, which is used to control external circuits.

[0048] The second single-channel XOR gate circuit 82 includes a second single-channel XOR gate chip 822. The Y-pin of the second single-channel XOR gate chip 822 is connected to a 3V3 terminal via a resistor R27. The A-pin of the second single-channel XOR gate chip 822 is connected to the MFP8 pin of the ADI high-speed differential transceiver chip 81. The B-pin of the second single-channel XOR gate chip 822 is connected to the VDDIO terminal, which is also connected to the ADI high-speed differential transceiver chip 81. A resistor R25 is also connected between the B-pin and A-pin of the second single-channel XOR gate chip 822. The second single-channel XOR gate chip 822 is symmetrical to the first single-channel XOR gate chip 821, with A connected to MFP8, B connected to 3V3, and VCC connected to VDDIO. It performs an XOR operation on the state of MFP8 and outputs the result to the subsequent circuit.

[0049] The ADI 81 high-speed differential transceiver chip's RXN / RXP (video input) and AUXN / AUXP (auxiliary channels) employ an AC coupling design: AC coupling capacitors (0.1μF, such as C50~C62, C64) act as DC blocking capacitors, isolating the DC bias between the preceding and following stages (such as the common-mode voltage difference between the transmitting and receiving ends) and avoiding DC level conflicts. Signal transmission: Only AC signals (differential changes in video data) are allowed to pass through, ensuring the "AC coupling" characteristic of the signal. Impedance matching of the AC coupling capacitors: The 0.1μF capacitors are approximately short-circuited at high frequencies, and combined with the characteristic impedance of the transmission line, this reduces signal reflection and optimizes the integrity of the high-speed differential signal.

[0050] In summary, this utility model adds a power surge protection module 3 and a reverse protection circuit module 4. The power surge protection module 3 can provide surge protection for the entire circuit, that is, resist surge current and prevent downstream circuits from being damaged by reverse high voltage. The reverse protection circuit module 4 is connected to the output terminal of the power surge protection module 3. This reverse protection circuit module 4 is used to block reverse current and prevent damage to downstream circuits. Furthermore, this invention can output high-power charging voltage and current to the TYPE-C interface 6 through the DC-DC controller module 5 to provide high-power charging for external devices connected to the TYPE-C interface 6. Additionally, the USB signal demultiplexer 7 internally dynamically switches the channel direction (transmit / receive) via an analog switch array to match the DFP / UFP role negotiation (i.e., host / device mode) of the Type-C interface, meeting different usage requirements. For example, this invention can access video data through the TYPE-C interface 6. The USB signal demultiplexer 7 internally dynamically switches the channel direction (transmit / receive) via an analog switch array, controlling the USB signal demultiplexer 7 to receive the video signal input from the TYPE-C interface 6 and transmit it to the ADI high-speed differential transceiver module 8. This ADI high-speed differential transceiver module 8 is used to convert parallel video signals into serial differential signals and outputs the serial differential signal through the Fakra connector 10 to meet different usage requirements.

[0051] Of course, the above description is only a specific embodiment of the present utility model and is not intended to limit the scope of the present utility model. All equivalent changes or modifications made to the structure, features and principles described in the claims of the present utility model should be included in the scope of the claims of the present utility model.

Claims

1. A vehicle-mounted high-definition video transmission high-power charging circuit, characterized in that: It includes: MQS connector (1); LED driver (2), which is connected to an LED and connected to the PWM terminal of MQS connector (1); A power surge protection module (3) is connected to an MQS connector (1); Anti-reverse circuit module (4), which is connected to the output terminal of power surge protection module (3); The DC-DC controller module (5) is connected to the output terminal of the anti-reverse circuit module (4) and is used to output high-power charging voltage and current. The TYPE-C interface (6) is used for inputting and outputting video signals and for high-power charging. It is connected to the DC-DC controller module (5) and receives the high-power charging voltage and current output by the DC-DC controller module (5). USB signal demultiplexer (7), which is connected to TYPE-C interface (6) and used to receive video signals input from TYPE-C interface (6); ADI high-speed differential transceiver module (8), which is connected to USB signal demultiplexer (7) and used to convert parallel video signals into serial differential signals; A DC-DC power module (9) is connected between the MQS connector (1) and the ADI high-speed differential transceiver module (8) and is used to power the ADI high-speed differential transceiver module (8). Fakra connector (10) connects to ADI high-speed differential transceiver module (8) to output serial differential signals.

2. The high-definition video transmission high-power charging circuit for vehicle according to claim 1, characterized in that: The LED driver (2) includes a resistor R11, a capacitor C20, a dual series-connected switching diode D3, a resistor R8, a resistor R9, a resistor R13, and a resistor R14. The LEDs include LED1 and LED2. One end of the resistor R11, the capacitor C20, and the dual series-connected switching diode D3 are all connected to the PWM terminal of the MQS connector (1). The other end of the resistor R11 and the capacitor C20 is grounded. The other end of the dual series-connected switching diode D3 is connected to the resistor R8 and the resistor R9. The resistor R8, the resistor R9, and the LED1 are connected in series and then grounded. The resistor R13, the resistor R14, and the LED2 are connected in series and then grounded.

3. The high-definition video transmission high-power charging circuit for vehicle according to claim 1, characterized in that: The power surge protection module (3) includes a TVS diode D2, whose two ends are respectively connected to the VI+ terminal and GND terminal of the MQS connector (1), and connected to the input terminal of the anti-reverse circuit module (4).

4. The in-vehicle high-definition video transmission high-power charging circuit according to claim 1, characterized in that: The anti-reverse circuit module (4) includes a Schottky barrier rectifier D1, an inductor L2 connected to the cathode of the Schottky barrier rectifier D1, a filter capacitor C8 and a filter capacitor C9 connected in parallel, and a filter capacitor C3 connected to the inductor L2. The anode of the Schottky barrier rectifier D1 is connected to the power surge protection module (3). The filter capacitors C8 and C9 and one end of the filter capacitor C8 are connected to the GND terminal of the MQS connector (1).

5. A vehicle-mounted high-definition video transmission high-power charging circuit according to any one of claims 1-4, characterized in that: The DC-DC controller module (5) includes a DC-DC controller (51), a filter network circuit (52) connected to the DC-DC controller (51), and a charging output circuit (53). The filter network circuit (52) includes capacitors C4, C5, C6, and C7 connected in parallel, and a resistor R13 connected to capacitor C7. The resistor R13 is connected to the EN terminal of the DC-DC controller (51), and one end of capacitor C7 connected to resistor R13 is also connected to the VIN pin of the DC-DC controller (51). The capacitor C4 is connected to the anti-reverse circuit module (4). The charging output circuit (53) includes the OUT terminal of the DC-DC controller (51). The resistor R7 connected to the pin and the VBUS1 terminal (531) connected to the resistor R7, the capacitor C15 connected to the OUT pin of the DC-DC controller (51), the capacitors C16, C18, and C19 connected in parallel with the two ends of the resistor C15, the capacitor C17 connected to the connection line between the resistor R7 and the VBUS1 terminal (531), and the capacitors C13 and C14 connected in parallel with the two ends of the capacitor C17, one end of the capacitors C16, C18, C19, C17, C13, and C14 connected in parallel with the two ends of the resistor C15 are all connected to ground. The VBUS1 terminal (531) is also connected to the TVS diode D4 for overvoltage protection and then grounded.

6. The in-vehicle high-definition video transmission high-power charging circuit according to claim 5, characterized in that: The DC-DC controller (51) is a DC-DC control chip of model MPQ4243. The DC-DC control chip has an alternating high-side switch SW1 and a low-side switch SW2. The high-side switch SW1 is connected to resistor R2 and capacitor C2 and then grounded. The low-side switch SW2 is connected to resistor R5 and capacitor C10 and then grounded. The high-side switch SW1 is also connected to inductor L1 and then to resistor R5. The BST1 pin of the DC-DC control chip is also connected to a first bootstrap circuit (511) composed of resistor R1 and capacitor C1. The capacitor C1 is also connected to resistor R2. The BST2 pin of the DC-DC control chip is also connected to a second bootstrap circuit (512) composed of resistor R6 and capacitor C11. The capacitor C11 is also connected to resistor R5. When the high-side switch SW1 is turned on, the input voltage VIN stores magnetic energy through the inductor L1, and the low-side switch SW2 is turned off at this time. When the high-side switch SW1 is turned off and the low-side switch SW2 is turned on, the inductor L1 releases magnetic energy, which is filtered into a smooth voltage by capacitors C19, C18, C16, C15, C17, C13, and C14, and provides a stable output to the VBUS1 terminal (531).

7. The high-definition video transmission high-power charging circuit for vehicle according to claim 6, characterized in that: The DC-DC control chip is also connected to a current feedback overcurrent protection circuit (513). The current feedback overcurrent protection circuit (513) includes resistors R15 and R16, and capacitors C12 and C23. One end of resistor R15 is connected to one end of resistor R7, and one end of resistor R16 is connected to the other end of resistor R7. Capacitor C12 is connected in parallel to one end of resistors R15 and R16, and capacitor C23 is connected in parallel to the other end of resistors R15 and R16. The other ends of resistors R15 and R16 are respectively connected to the ISENS+ and ISENS- pins of the DC-DC control chip.

8. The high-definition video transmission and high-power charging circuit for vehicle according to claim 6 or 7, characterized in that: The DC-DC power module (9) includes a synchronous buck converter (91) and a multi-channel synchronous buck converter (92). The input terminal of the synchronous buck converter (91) is connected to the output terminal of the anti-reverse circuit module (4). The synchronous buck converter (91) has a 3V3 terminal that outputs 3.3V. The input terminal of the multi-channel synchronous buck converter (92) is connected to the 3V3 terminal, and the multi-channel synchronous buck converter (92) has a 1V8 terminal that outputs 1.8V respectively. Both the 3V3 terminal and the 1V8 terminal are connected to the ADI high-speed differential transceiver module (8) to provide 3.3V and 1.8V voltages to the ADI high-speed differential transceiver module (8).

9. A vehicle-mounted high-definition video transmission high-power charging circuit according to any one of claims 1-4, characterized in that: The ADI high-speed differential transceiver module (8) includes an ADI high-speed differential transceiver chip (81) of model MAX96749APGTN / VY+T. The ADI high-speed differential transceiver chip (81) is connected to a single-channel XOR gate circuit (82), an interface ESD protection circuit (83), a low-frequency ripple circuit for suppressing power supply (84), and a high-frequency ripple circuit for filtering high-frequency noise (85). The interface ESD protection circuit (83) is connected to a Fakra connector (10). The low-frequency ripple circuit (84) and the high-frequency ripple circuit (85) are respectively connected to the VDD terminal and the 1V8 terminal of the DC-DC power module (9).

10. The high-definition video transmission high-power charging circuit for vehicle according to claim 9, characterized in that: The number of low-frequency ripple circuits (84) is multiple, and each low-frequency ripple circuit (84) includes a first ceramic capacitor (841) and a second ceramic capacitor (842) connected in parallel. One end of the first ceramic capacitor (841) is connected to both the VDD terminal and a pin of the ADI high-speed differential transceiver chip (81), and the other end is grounded. The number of high-frequency ripple circuits (85) is multiple, and each high-frequency ripple circuit (85) includes a third ceramic capacitor (851) and a fourth ceramic capacitor (852) connected in parallel. One end of the third ceramic capacitor (851) is connected to both the VDD terminal and a pin of the ADI high-speed differential transceiver chip (81), and the other end is grounded. The interface ESD protection circuit (83) includes an ESD protection diode D7. The cathode of the ESD protection diode D7 is connected to the MFP19 / LMN2 terminal of the ADI high-speed differential transceiver chip (81) after being connected to the resistor R48. The cathode of the ESD protection diode D7 is connected to the SIOAN / SIOA terminal of the ADI high-speed differential transceiver chip (81) after being connected to the capacitor C28. The cathode of the ESD protection diode D7 is also connected to the Fakra connector (10). The number of single-channel XOR gate circuits (82) is two. The first single-channel XOR gate circuit (82) includes a first single-channel XOR gate chip (821). The Y pin of the first single-channel XOR gate chip (821) is connected to the 3V3 terminal after the resistor R23. The A pin of the first single-channel XOR gate chip (821) is grounded. The B pin of the first single-channel XOR gate chip (821) is connected to the MFP9 pin of the ADI high-speed differential transceiver chip (81). The B pin of the first single-channel XOR gate chip (821) is also connected to the VDDIO terminal after the resistor R21. The VDDIO terminal is connected to the ADI high-speed differential transceiver chip (81). The second single-channel XOR gate circuit (82) includes a second single-channel XOR gate chip (822). The Y pin of the second single-channel XOR gate chip (822) is connected to the 3V3 terminal after the resistor R27. The A pin of the second single-channel XOR gate chip (822) is connected to the MFP8 pin of the ADI high-speed differential transceiver chip (81). The B pin of the second single-channel XOR gate chip (822) is connected to the VDDIO terminal. The VDDIO terminal is connected to the ADI high-speed differential transceiver chip (81). A resistor R25 is also connected between the B pin and the A pin of the second single-channel XOR gate chip (822).

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