Analog-to-digital converter with misalignment calibration function, computing and storage integrated device and electronic equipment

Abstract

The application relates to an analog-to-digital converter with a misalignment calibration function, a storage-computation integrated device and electronic equipment. The analog-to-digital converter comprises a comparator, a latch and a calibration module. The calibration module comprises a coarse calibration circuit for coarsely calibrating the misalignment voltage of the comparator, a fine calibration circuit for finely calibrating the misalignment voltage of the comparator and a calibration control logic circuit for controlling the work of the coarse calibration circuit and the fine calibration circuit. The calibration control logic circuit outputs a coarse calibration control signal to control the coarse calibration circuit to coarsely calibrate the misalignment voltage of the comparator. The calibration control logic circuit is also used to output a fine calibration control signal for controlling the work of the fine calibration circuit after coarse calibration, so as to inject charges into the input end of the comparator, thereby offsetting the misalignment voltage of the comparator. The calibration range of the fine calibration circuit is greater than one calibration step of the coarse calibration circuit. The analog-to-digital converter provided by the application has the misalignment calibration function and has the advantages of small area, low power consumption, small error and being not easy to be disturbed.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to an analog-to-digital converter, a memory computing device, and an electronic device with offset calibration function. Background Technology

[0002] An analog-to-digital converter (ADC) converts analog signals into digital signals. An ADC samples an analog signal and then quantizes and encodes the sampled analog signal to obtain the corresponding digital signal.

[0003] However, during analog-to-digital conversion, ADCs are susceptible to noise interference and offset, leading to bit errors in the output digital signal. Calibrating the offset voltage of the ADC can significantly reduce the bit error rate of the ADC output signal. The comparator in the ADC is the primary source of offset voltage. For an ideal comparator, the output should switch instantaneously when the input voltage difference (Vip - Vin) is 0. However, in reality, due to minute mismatches in transistor manufacturing (such as differences in threshold voltage and size), the comparator may not switch even when the input difference is 0. The input voltage difference required for the comparator output to switch is the offset voltage. Comparators typically have inherent offset voltages, especially those containing latches, which significantly impact comparator performance. For example, comparators containing CMOS latches have large offset voltages, reaching tens of millivolts. Furthermore, in some applications, comparators are used in two-step ADCs to form a coarse-quantized fully parallel ADC, which can cause quantization errors between the coarse-quantized fully parallel ADC and the subsequent ADC due to the presence of offset voltage. In dynamic comparators, offset voltage primarily originates from the mismatch of transistors in the internal latch stage. This mismatch is random and fixed, directly reducing the comparator's accuracy. For high-precision analog-to-digital converters (ADCs), the comparator's offset must be calibrated to a very small level (e.g., less than LSB / 2). Since the comparator is the quantizer of the ADC to implement quantization, it is a crucial component of the ADC. Therefore, it is evident that the comparator's offset has a significant impact on the overall performance of the ADC.

[0004] Therefore, designing an analog-to-digital converter (ADC) with low offset voltage is particularly important. However, current ADCs often suffer from problems such as large area, high power consumption, susceptibility to signal path interference, and large quantization errors when calibrating offset voltage, which affects the performance of the ADC and reduces its applicability and target applications. Utility Model Content

[0005] In view of this, in order to solve some or all of the above-mentioned technical problems, this application provides an analog-to-digital converter with offset calibration function.

[0006] The analog-to-digital converter provided by this utility model includes: a comparator for comparing an input voltage with a reference voltage, a latch for latching the comparison result of the comparator, and a calibration module for calibrating the offset voltage of the comparator. The calibration module includes: a coarse calibration circuit for coarsely calibrating the offset voltage of the comparator, a fine calibration circuit for finely calibrating the offset voltage of the comparator, and a calibration control logic circuit for controlling the operation of the coarse calibration circuit and the fine calibration circuit. The calibration control logic circuit outputs a coarse calibration control signal to control the coarse calibration circuit to coarsely calibrate the offset voltage of the comparator. The calibration control logic circuit also outputs a fine calibration control signal after coarse calibration to control the fine calibration circuit to perform fine calibration. The fine calibration circuit injects different charges into the two input terminals of the comparator according to the fine calibration control signal to introduce an input voltage, thereby canceling the offset voltage of the comparator. The calibration range of the fine calibration circuit is larger than one calibration step of the coarse calibration circuit.

[0007] In a preferred embodiment of this invention, the comparator includes a built-in internal latch, and the coarse calibration circuit is used to adjust the load capacitance of the two output terminals of the internal latch to offset the offset voltage of the comparator.

[0008] In a preferred embodiment of this utility model, the coarse calibration circuit includes: a first branch electrically connected to a first output terminal of the internal latch, and a second branch electrically connected to a second output terminal of the internal latch; the first branch includes a plurality of first switched capacitor branches connected in parallel, each first switched capacitor branch including a first switch and a first capacitor, one end of the first switch being electrically connected to the first output terminal of the internal latch, the other end of the first switch being grounded through the first capacitor, and the control terminal of the first switch being connected to the calibration control logic circuit to receive the coarse calibration control signal; the second branch includes a plurality of second switched capacitor branches connected in parallel, each second switched capacitor branch including a second switch and a second capacitor, one end of the second switch being electrically connected to the second output terminal of the internal latch, the other end of the second switch being grounded through the second capacitor, and the control terminal of the second switch being connected to the calibration control logic circuit to receive the coarse calibration control signal.

[0009] In a preferred embodiment of the present invention, the calibration control logic circuit is used to control the fine calibration circuit to inject a preset calibration voltage into the input terminal of the comparator to find a compensation voltage that can compensate for the offset voltage of the comparator. The calibration control logic circuit is also used to apply the compensation voltage to the comparator when the comparator is working.

[0010] In a preferred embodiment of this utility model, the fine calibration circuit includes: a plurality of third branches electrically connected to the first input terminal of the comparator, and a plurality of fourth branches electrically connected to the second input terminal of the comparator; each third branch includes a third capacitor and a third switch, one end of the third capacitor is electrically connected to the first input terminal of the comparator, the other end of the third capacitor is electrically connected to one end of the third switch, and the control terminal of the third switch is connected to the calibration control logic circuit so that the other end of the third switch switches between power supply VDD and ground, thereby injecting charge; each fourth branch includes a fourth capacitor and a fourth switch, one end of the fourth capacitor is electrically connected to the second input terminal of the comparator, the other end of the fourth capacitor is electrically connected to one end of the fourth switch, and the control terminal of the fourth switch is connected to the calibration control logic circuit so that the other end of the fourth switch switches between power supply VDD and ground, thereby injecting charge.

[0011] In a preferred embodiment of this utility model, the comparator includes: switching transistors M0, M1a, M1b, M2a, M2b, M3, M4, M5, and M6; power supply VDD is connected to ground sequentially through the switching transistors M3, M1b, M1a, and M0, and also connected to ground sequentially through the switching transistors M6, M2b, M2a, and M0; the control terminals of the switching transistors M1a and M1b are connected together to form the first input terminal of the comparator, and the connection point of the switching transistors M1a and M1b is open to... The switching transistor M4 is connected to the power supply VDD, and the connection points of switching transistors M1a and M1b are electrically connected to the coarse calibration circuit. The control terminals of switching transistors M2a and M2b are connected together to form the second input terminal of the comparator. The connection points of switching transistors M2a and M2b are connected to the power supply VDD through the switching transistor M5, and the connection points of switching transistors M2a and M2b are electrically connected to the coarse calibration circuit. The control terminals of switching transistors M0, M3, M4, M5, and M6 are all connected to the first clock signal CLK.

[0012] In a preferred embodiment of this utility model, the latch includes: switching transistors M7, M8, M9, M10, M11, M12, M13, and M14; power supply VDD is connected sequentially to the control terminals of switching transistors M10 and M12 through switching transistors M9 and M7, and the control terminal of switching transistor M7 is connected to the second output terminal Vmn of the comparator; power supply VDD is connected sequentially to the control terminals of switching transistors M9 and M11 through switching transistors M10 and M8, and the control terminal of switching transistor M8 is connected to the first output terminal Vmp of the comparator; the control terminal of switching transistor M10 is connected to ground through switching transistor M13, and the control terminal of switching transistor M10 is also connected to ground through switching transistor M11; the control terminal of switching transistor M9 is connected to ground through switching transistor M12, and the control terminal of switching transistor M9 is also connected to ground through switching transistor M14; the control terminals of switching transistors M13 and M14 are both connected to the second clock signal nCLK.

[0013] This utility model also provides an in-memory computing device, which includes an in-memory computing module and an analog-to-digital converter for converting the analog multiplication and accumulation results output by the in-memory computing module into digital signals, wherein the analog-to-digital converter is any of the analog-to-digital converters described above.

[0014] In a preferred embodiment of this utility model, the in-memory calculation module includes: a first in-memory calculation circuit based on digital signals, a second in-memory calculation circuit based on analog signals, and an accumulator. The first in-memory calculation circuit performs multiplication and accumulation calculation on the input feature data and the high-weight bits of the weights based on a digital addition tree to obtain a first multiplication and accumulation result of digital. The second in-memory calculation circuit performs multiplication and accumulation calculation on the input feature data and the low-weight bits of the weights based on a capacitor to obtain an analog multiplication and accumulation result. The analog-to-digital converter is used to perform analog-to-digital conversion on the analog multiplication and accumulation result output by the second in-memory calculation circuit to obtain a second multiplication and accumulation result of digital. The accumulator is used to accumulate the first multiplication and accumulation result and the second multiplication and accumulation result.

[0015] This application also provides an electronic device that includes any of the analog-to-digital converters described above.

[0016] The analog-to-digital converter (ADC) provided by this invention, through a calibration module comprising a coarse calibration module, a fine calibration module, and a calibration control logic circuit, enables it to perform two-stage calibration: coarse calibration and fine calibration. The calibration control logic circuit outputs a coarse calibration control signal to control the coarse calibration circuit to coarsely calibrate the offset voltage of the comparator. After coarse calibration, the calibration control logic circuit also outputs a fine calibration control signal to control the fine calibration circuit to perform fine calibration. The fine calibration circuit injects different charges into the two input terminals of the comparator according to the fine calibration control signal to introduce an input voltage, thereby canceling the offset voltage of the comparator. The calibration range of the fine calibration circuit is larger than one calibration step of the coarse calibration circuit. Therefore, the ADC provided by this invention can perform both coarse calibration over a large range on the offset voltage of the comparator within the ADC and fine calibration on the offset voltage of the comparator within the ADC. The calibration module uses a coarse calibration control signal to enable the coarse calibration circuit to perform coarse calibration on the offset voltage over a large voltage range. This allows for calibration of the offset voltage over a wider range and faster reduction or cancellation of the offset voltage, making the ADC suitable for situations with large offset voltages. Furthermore, after coarse calibration, the calibration module performs fine calibration based on charge injection using a fine calibration circuit. This fine calibration circuit can perform high-precision calibration more accurately over a smaller voltage range, thereby reducing the quantization error of the analog-to-digital converter (ADC) and improving its conversion accuracy. In particular, the calibration range of the fine calibration circuit in this invention is larger than one calibration step of the coarse calibration circuit, allowing the ADC to perform coarse and fine calibrations on the offset voltage in different ranges and modes. Furthermore, because this invention performs coarse calibration before fine calibration, the offset voltage calibration is controlled within a smaller voltage range. Therefore, the analog-to-digital converter (ADC) can use fewer electronic components and a smaller correction step size to accurately calibrate the offset voltage. This means the ADC can use a smaller circuit area and reduce power consumption, especially in the chip circuitry. Coarse calibration also reduces the number of small electronic components that might be needed in the fine calibration circuit, such as small capacitors, thus reducing interference from small capacitors on the input signal path. Therefore, the ADC provided by this invention, through both coarse and fine calibration, simultaneously possesses the advantages of both. Furthermore, its combination with charge injection-based fine calibration allows the ADC to achieve offset voltage calibration while also resulting in a smaller ADC area, lower power consumption, less susceptibility to signal path interference, and smaller quantization error. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the circuit structure of the analog-to-digital converter provided in the embodiments of this application; Figure 2 This is a schematic diagram of the circuit structure of an analog-to-digital converter provided in another embodiment of this application; Figure 3 This is a circuit diagram of an analog-to-digital converter provided in one embodiment of this application; Figure 4 This is a control flowchart of two calibration stages in one embodiment of this application; Figure 5 This is a structural block diagram of the hybrid in-memory computing device provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the hybrid in-memory computing device provided in the embodiments of this application; Figure 7 This is a comparison chart showing the error of a mixed-signal-based in-memory computing device provided in one embodiment of this application compared to existing analog computing schemes. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this utility model clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be adopted to implement this utility model. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of this utility model disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of this utility model.

[0020] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0021] See Figure 1 and Figure 2 The diagram shows the structure of an analog-to-digital converter (ADC) with offset calibration function provided in this embodiment of the present invention. The ADC includes a comparator 30, a latch 20, and a calibration module 10. The comparator 30 compares the input voltage with a reference voltage, the latch 20 latches the comparison result of the comparator 30, and the calibration module 10 calibrates the offset voltage of the comparator 30. The calibration module 10 includes a coarse calibration circuit 101 for coarse calibration of the offset voltage of the comparator 30, a fine calibration circuit 102 for fine calibration of the offset voltage of the comparator 30, and a calibration control logic circuit 103 for controlling the operation of the coarse calibration circuit 101 and the fine calibration circuit 102. The calibration control logic circuit 103 is used to output a coarse calibration control signal to control the coarse calibration circuit 101 to coarsely calibrate the offset voltage of the comparator 30; the calibration control logic circuit 103 is also used to output a fine calibration control signal after coarse calibration to control the fine calibration circuit 102 to perform fine calibration; the fine calibration circuit is used to inject different charges into the two input terminals of the comparator according to the fine calibration control signal to introduce an input voltage, thereby canceling the offset voltage of the comparator 30, and the calibration range of the fine calibration circuit 102 is larger than one calibration step of the coarse calibration circuit 101.

[0022] Therefore, the analog-to-digital converter (ADC) provided by this invention can perform both coarse calibration of the offset voltage of the comparator 30 within the ADC over a wide range and fine calibration of the offset voltage of the comparator 30 within the ADC, thereby achieving the required quantization range and improving the conversion accuracy of the ADC. Specifically, the calibration range of the coarse calibration circuit 101 is greater than the maximum value of the offset voltage of the comparator 30, allowing the coarse calibration circuit 101 to perform calibration within a voltage range larger than the maximum value of the offset voltage, thus canceling out the offset voltage of the comparator 30. The calibration module 10 uses a coarse calibration control signal to cause the coarse calibration circuit 101 to first perform coarse calibration of the offset voltage within a large voltage range, thereby enabling calibration of the offset voltage over a large range and quickly reducing or canceling the offset voltage, and making the ADC suitable for situations with large offset voltages. Furthermore, after coarse calibration, the calibration module 10 performs fine calibration through the fine calibration circuit 102. This allows the fine calibration circuit 102 to perform calibration within a smaller voltage range, thereby reducing the quantization error of the analog-to-digital converter (ADC) and improving its conversion accuracy. In particular, the calibration range of the fine calibration circuit 102 in this invention is larger than one calibration step of the coarse calibration circuit 101, enabling the ADC to perform coarse and fine calibrations in different ranges and modes for the offset voltage. Moreover, the fine calibration circuit 102 of this invention introduces an input voltage by injecting different charges into the two input terminals of the comparator according to the fine calibration control signal, thereby canceling the comparator's offset voltage. Therefore, the fine calibration circuit 102 can perform higher-precision calibration within a smaller calibration range, thus better addressing quantization errors and optimizing its accuracy. Furthermore, since this invention performs coarse calibration before fine calibration, the offset voltage calibration is controlled to a smaller voltage range. Therefore, the analog-to-digital converter can use fewer electronic components and a smaller correction step size to accurately calibrate the offset voltage. In other words, the analog-to-digital converter can use a smaller circuit area and reduce the power consumption of the circuit, especially the chip circuit. Coarse calibration can reduce the number of tiny electronic components that may be needed in the fine calibration circuit 102. For example, coarse calibration can reduce the number of small capacitors that may be needed in the fine calibration circuit 102, thereby reducing the interference of small capacitors on the input signal path.

[0023] In summary, the analog-to-digital converter (ADC) provided by this invention has an offset voltage calibration function. First, it performs coarse calibration to reduce the offset voltage to a smaller range. Then, it combines the calibration control logic unit and the fine calibration circuit 102 to cancel out the offset voltage after coarse calibration (the cancellation can mean completely removing the offset voltage or reducing it to a very small acceptable range). Therefore, the ADC provided by this invention, through both coarse and fine calibration, simultaneously possesses the advantages of both. Furthermore, by combining fine calibration based on charge injection, the ADC not only achieves offset voltage calibration but also results in a smaller ADC area, lower power consumption, less interference in the signal path, and smaller quantization error.

[0024] The ADC provided by this invention has a wider range of applications and can be used in a wider range of applications, such as high-precision or high-speed analog-to-digital converters. For example, the ADC provided by this invention can be applied to AI computing chips, wireless communication chips, wired communication chips, digital signal processing chips, mobile phone main control chips, AR / VR main control chips, etc.

[0025] See Figure 2As shown, in one embodiment of this invention, the coarse calibration circuit 101 is a switched-capacitor-based coarse calibration circuit 101 (i.e., the switched-capacitor coarse calibration circuit 101 in the figure). It adjusts the capacitor array connected to the nodes inside the comparator 30, for example, by controlling the connection or disconnection of capacitors through a switch, to change the load capacitance of the nodes, thereby calibrating / canceling the offset voltage. In this preferred embodiment, the coarse calibration circuit 101 calibrates the offset voltage of the comparator 30 by adjusting the load capacitance of the nodes inside the comparator 30. It can significantly change the voltage at the nodes inside the comparator 30, thus performing a larger-scale coarse calibration. The coarse calibration circuit 101 can perform coarse calibration by adjusting the sensitive nodes inside the comparator 30. Preferably, the comparator includes a built-in internal latch. Under the control of the coarse calibration code (i.e., the aforementioned coarse calibration control signal) output by the calibration control logic circuit 103, the coarse calibration circuit 101 adjusts the load capacitance of the two output terminals of the built-in internal latch of the comparator 30 to calibrate / cancele the offset voltage of the comparator 30. For example, the calibration control logic circuit 103 adjusts the load capacitance at the output of the internal latch by regulating the binary-weighted switched capacitor array connected to the output of the internal latch, thereby enabling rapid coarse calibration with relatively simple and low-cost circuit implementation. Under the control of the calibration control logic circuit 103, the switched capacitor coarse calibration circuit 101 can change the load capacitance of the node by switching the capacitors on and off, thus adjusting the regeneration time constant of the latch 20. Since mismatch can cause varying regeneration speeds, this speed difference can be compensated for by asymmetrically adjusting the capacitance at the two outputs of the latch 20, thereby offsetting the offset voltage. Furthermore, this method features a simple circuit structure, low cost, and low power consumption.

[0026] exist Figure 2 In this circuit, the fine calibration circuit 102 is a charge injection-based fine calibration circuit. Under the control of the fine calibration code (i.e., the aforementioned fine calibration control signal) output by the calibration control logic circuit 103, it can inject a preset calibration voltage into the input terminal of the comparator 30. Through an iterative algorithm (e.g., binary search), it finds a voltage value that can compensate for the offset voltage of the comparator 30 (i.e., the compensation voltage value) and stores this compensation voltage value. In other words, it continuously checks the corresponding output to the input signal through an algorithm, thereby attempting to find the offset voltage value. When the comparator 30 of the analog-to-digital converter is working, the calibration control logic circuit 103 applies the compensation voltage to the comparator 30, thereby achieving fine calibration of the offset voltage. This method can quickly and accurately find the compensation voltage, thus quickly and accurately performing fine calibration of the offset voltage. It can also reduce the quantization error of the analog-to-digital converter and improve its accuracy.

[0027] See Figure 3 and Figure 4 In the preferred embodiment shown, the comparator 30 has an internal latch, and the coarse calibration circuit 101 is a switched capacitor-based circuit. In this preferred embodiment, the coarse calibration circuit 101 includes: a first branch 1011 electrically connected to the first output terminal of the internal latch, and a second branch 1012 electrically connected to the second output terminal of the internal latch; the first branch 1011 includes a plurality of first switched capacitor branches connected in parallel, each first switched capacitor branch including a first switch and a first capacitor, one end of the first switch being electrically connected to the first output terminal Vxn of the internal latch, the other end of the first switch being grounded through the first capacitor, and the control terminal of the first switch being connected to the calibration control logic circuit 103 to receive the coarse calibration control signal CCDN; the second branch 1012 includes a plurality of second switched capacitor branches connected in parallel, each second switched capacitor branch including a second switch and a second capacitor, one end of the second switch being electrically connected to the second output terminal Vxp of the internal latch, the other end of the second switch being grounded through the second capacitor, and the control terminal of the second switch being connected to the calibration control logic circuit 103 to receive the coarse calibration control signal CCDP. Therefore, under the control of the calibration control logic circuit 103, the way the capacitor in the coarse calibration circuit 101 is connected to the sensitive node of the comparator 30 can be changed, thereby changing the load capacitance of the sensitive node inside the comparator 30, and thus fine-tuning the regeneration time constant of the latch 20. Since mismatch can cause the regeneration speed to vary, this speed difference can be compensated by asymmetrically adjusting the capacitors on both sides, thereby canceling the offset. Therefore, it can calibrate the offset voltage over a wide voltage range, and its circuit structure is simple, low in cost, and low in power consumption.

[0028] See you again Figure 3The fine calibration circuit 102 includes: a plurality of third branches 1021 electrically connected to the first input terminal Vinp of the comparator 30, and a plurality of fourth branches 1022 electrically connected to the second input terminal Vinn of the comparator 30; each third branch 1021 includes a third capacitor C3 and a third switch K3, one end of the third capacitor is electrically connected to the first input terminal Vinp of the comparator 30, and the other end of the third capacitor is electrically connected to one end of the third switch, the control terminal of the third switch is connected to the fine calibration control signal CFDP output by the calibration control logic circuit 103, so that the other end of the third switch switches between power supply VDD and ground, thereby injecting charge; each fourth branch 1022 includes a fourth capacitor C4 and a fourth switch K4, one end of the fourth capacitor C4 is electrically connected to the second input terminal Vinn of the comparator 30, and the other end of the fourth capacitor is electrically connected to one end of the fourth switch, the control terminal of the fourth switch is connected to the fine calibration control signal CFDN output by the calibration control logic circuit 103, so that the other end of the fourth switch switches between power supply VDD and ground, thereby injecting charge. Under the control of the calibration control logic circuit 103, the fine calibration control signal CFDP allows the input terminal Vinp of comparator 30 to be connected to ground or power supply VDD through a third capacitor, thereby injecting charge into the first input terminal of comparator 30 through several third branches 1021. Similarly, the fine calibration control signal CFDN allows charge to be injected into the second input terminal of comparator 30 through several fourth branches 1022. This invention can inject a known calibration voltage (e.g., through a DAC) into the two input terminals of comparator 30. By controlling the connection or disconnection of the capacitor with a switch, the load capacitance of the node is changed, thereby fine-tuning the regeneration time constant of latch 20. Since mismatch can cause varying regeneration speeds, this speed difference can be compensated by asymmetrically adjusting the capacitance of the two input terminals of comparator 30, thus offsetting the offset voltage. For example, an iterative algorithm (such as binary search) can be used to find a voltage value that can compensate for the inherent offset, and this digital code can be stored. During normal operation, the DAC continuously applies this compensation voltage, allowing the fine calibration circuit 102 to offset / calibrate the offset voltage.

[0029] When injecting charge into the two input terminals of comparator 30, it is preferable to inject charge into the two input terminals of comparator 30 through a capacitor DAC (i.e., CDAC). This allows for continuous and accurate charge injection into comparator 30, enabling continuous and precise fine calibration of the offset voltage within a small voltage range, resulting in low quantization error and high conversion accuracy of the analog-to-digital converter. However, the additional DAC circuit increases the circuit area and power consumption of the analog-to-digital converter, especially under high-precision requirements. A high bit depth of the DAC will occupy more chip area and increase power consumption. Moreover, extremely small capacitors are required to achieve small calibration steps, but small capacitors are difficult to physically implement (limited by process limitations and the parasitic capacitance of transistors), and extremely small capacitors themselves have significant mismatch. Furthermore, direct voltage injection into comparator 30 may introduce nonlinearity, noise, or load effects into the analog input signal path, affecting the speed and linearity of comparator 30. Therefore, in the analog-to-digital converter provided by this utility model, before fine calibration, coarse calibration is first performed through the coarse calibration circuit 101 and calibration control logic circuit 103 in the calibration module 10, so that the offset voltage is roughly calibrated to a smaller voltage range. This eliminates the need for a large area DAC array for calibration, reduces the power consumption of the entire circuit and the analog-to-digital converter, and reduces the interference of small capacitors on the input signal path.

[0030] In the analog-to-digital converter provided by this utility model, the comparator 30 can adopt various circuit structures, preferably, such as Figure 3In this embodiment, comparator 30 includes switching transistors M0, M1a, M1b, M2a, M2b, M3, M4, M5, and M6. Power supply VDD is connected to ground sequentially through switching transistors M3, M1b, M1a, and M0, and also sequentially through switching transistors M6, M2b, M2a, and M0. The control terminals of switching transistors M1a and M1b are connected together to form the first input terminal Vinp of comparator 30. The connection point Vxn of switching transistors M1a and M1b is connected to power supply VDD through switching transistor M4, and the connection point Vxn of switching transistors M1a and M1b is electrically connected to the coarse calibration circuit 101. The control terminals of the switching transistors M2a and M2b are connected together to form the second input terminal Vinn of the comparator 30. The connection point Vxp of the switching transistors M2a and M2b is connected to the power supply VDD through the switching transistor M5, and the connection point Vxp of the switching transistors M2a and M2b is electrically connected to the coarse calibration circuit 101. The control terminals of the switching transistors M0, M3, M4, M5, and M6 are all connected to the first clock signal CLK. Therefore, the first clock signal CLK can control the on / off state of the switching transistors M3-M6 and the switching transistor M0, thereby enabling the comparator 30 to compare the input voltage with the reference voltage. This comparator 30 has fewer electronic components, a simple circuit structure, low power consumption, low cost, good stability, and fast processing speed.

[0031] The latch in the analog-to-digital converter (ADC) that latches the comparison result of the comparator includes switches M7, M8, M9, M10, M11, M12, M13, and M14. Power supply VDD is connected sequentially to the control terminals of switches M10 and M12 via switches M9 and M7, respectively. The control terminal of switch M7 is connected to the second output terminal Vmn of the comparator. Power supply VDD is also connected sequentially to the control terminals of switches M9 and M11 via switches M10 and M8, respectively. The control terminal of switch M8 is connected to the first output terminal Vmp of the comparator. The control terminal of switch M10 is connected to ground via switch M13, and also via switch M11. The control terminal of switch M9 is connected to ground via switch M12, and also via switch M14. The control terminals of switches M13 and M14 are both connected to the second clock signal nCLK. This latch has a simple circuit structure, fewer electronic components, lower cost, lower power consumption, better stability, and faster processing speed.

[0032] The following is combined Figure 3 and Figure 4 The working principle and process of this utility model are roughly described as follows: First, the calibration module performs a rough calibration of the offset voltage using the calibration control logic circuit and the coarse calibration circuit. The first and second branches of the coarse calibration circuit adjust the internal nodes in the comparator (i.e., Figure 3 Specifically, the capacitors (Vxn and Vxp) are calibrated by controlling the on / off state of the switches in the first and second branches through the coarse calibration codes CCDN and CCDP output by the calibration control logic circuit. This controls whether the first and second capacitors are connected to the circuit, thereby adjusting the capacitance of nodes Vxn and Vxp, and thus coarsely calibrating the offset voltage of the comparator. Then, the third and fourth branches included in the fine calibration circuit inject different charges into the two input terminals of the comparator to introduce an input voltage and further finely cancel the offset voltage of the comparator.

[0033] like Figure 3 As shown, when the voltage Vinp at the first input terminal of the comparator is greater than the voltage Vinn at the second input terminal, the conduction capability of switches M1b and M1a is stronger than that of switches M2b and M2a. Therefore, switches M1b and M1a pull a larger current to ground, making the voltage at node Vmp lower than that at node Vmn. The lower Vmp voltage makes the conduction capability of switch M8 stronger than that of M7. Therefore, a larger current flows from the power supply to node Voutp of the latch, making the voltage at node Voutp larger. Then, the positive feedback of the latch formed by switches M7~M14 pulls the voltage at node Voutp to the power supply voltage VDD and pulls the voltage at node Voutn to ground.

[0034] The coarse calibration code CCDN adjusts the capacitance of node Vxn within the comparator by controlling the size of the connected capacitor array. More capacitors connected to the circuit in the first branch result in a lower voltage at node Vxn; similarly, the coarse calibration code CCDP adjusts the capacitance of node Vxp. Therefore, the calibration module effectively generates an equivalent differential voltage at the comparator's input. The calculation process is as follows: in, These are the capacitance differences generated by the capacitor arrays controlled by two coarse calibration codes, CCDN and CCDP. Cvxn and Cvxp are the total capacitance values ​​at nodes Vxn and Vxp, respectively. VT is the gate-source voltage difference between switching transistors M1b and M1a, and VT is the threshold voltage of the switching transistors (switching transistors M1a, M1b, M2a, M2b).

[0035] For fine calibration circuits, it controls the capacitor array to switch between VDD and ground to inject charge through fine calibration codes CFDP / CFDN.

[0036] Figure 3 The CDAC is integrated into the analog-to-digital converter (ADC) and is used to provide a reference voltage to the comparator's input. Typically, the capacitance of the CDAC is more than 100 times larger than that of the Cvxn, because a larger CDAC capacitance helps suppress KT / C noise and reduces mismatch voltage. Typically, it's 0.2*VDD. Therefore, for the same capacitance change, the equivalent input voltage change introduced by the capacitance change in the fine calibration circuit is about 1 / 20th of that in the coarse calibration circuit. The fine calibration circuit's calibration range is larger than one step size of the coarse calibration circuit. The coarse calibration circuit's calibration range is larger than the maximum value of the comparator offset voltage. Therefore, it can be seen that the analog-to-digital converter provided by this invention can first roughly calibrate the offset voltage over a large range using the coarse calibration circuit, and then use the fine calibration circuit to calibrate / cancel the offset voltage with high precision over a smaller range. Thus, coarse calibration ensures the maximum voltage calibration range of the calibration circuit without requiring large-area DAC or other auxiliary circuitry, thereby reducing the ADC's area and power consumption, and also reducing interference to the input signal path; moreover, the fine calibration circuit can guarantee the minimum step size of the calibration circuit, thereby reducing the quantization error of the analog-to-digital converter and improving its accuracy.

[0037] See Figure 4 The diagram shown is a calibration control flowchart in one embodiment of this utility model. After calibration begins, coarse calibration is performed first. The ADC performs a coarse calibration scan, for example, sequentially scanning 111, 110, 101, 100, 000, 001, 010, 011... until the coarse calibration end condition is met. The coarse calibration end condition is, for example, one of the following: 1. When the minimum value is scanned, the comparator output is still 1; 2. During the scan, the comparator output flips; 3. When the maximum value is scanned, the comparator output is still 0 (at this time, the fine calibration output is 00000). For example, when the coarse calibration meets the above end condition 1, the coarse calibration ends and fine calibration begins, until one of the following calibration end conditions is met, then the calibration ends: 1. When the minimum value is input (e.g., 11111), the comparator output is still 1; 2. When the minimum value is input (e.g., 11111), the comparator output is still 0, but during the scan, the comparator flips. See details below. Figure 3 As shown, examples will not be repeated here.

[0038] In summary, the analog-to-digital converter (ADC) provided by this invention, through a two-stage calibration scheme (i.e., coarse calibration followed by fine calibration), enables the ADC to calibrate the offset voltage while simultaneously addressing the problem of large quantization errors. Furthermore, it eliminates the need for large-area circuitry, reducing the area and power consumption of the ADC, especially chip-based ADCs, and minimizing interference with the input signal path. This improves ADC performance and expands its applicability and target applications.

[0039] It is worth noting that comparators with built-in internal latches can be configured as ultra-high-speed comparators, thus enabling analog-to-digital converters (ADCs) to be applied in fields requiring ultra-high speed. However, existing comparators with built-in internal latches have relatively large offset voltages, making it difficult to achieve high-precision ADCs. The ADC provided by this invention, however, achieves a combination of coarse and fine calibration through a calibration module, enabling the ADC to achieve high precision while requiring a smaller area and lower power consumption, thereby broadening its applicability across a wider range of fields. The ADC provided by this invention can be applied to, for example, AI computing chips, wireless communication chips, wired communication chips, digital signal processing chips, mobile phone main control chips, and AR / VR main control chips.

[0040] This application also provides a mixed-signal in-memory computing device, the in-memory computing device comprising: an in-memory computing module, and an analog-to-digital converter for converting the analog multiplication-accumulation result output by the in-memory computing module into a digital signal, wherein the analog-to-digital converter is any one of the above-mentioned analog-to-digital converters.

[0041] The in-memory computing device can take various forms, such as a chip or a module. It is particularly well-suited for low-power AI computing chips. Low-power AI computing chips are a key engine driving artificial intelligence from the cloud to real-world scenarios, and their importance is reflected in three aspects. First, they enable the "ubiquitousness" of AI applications. Many key AI scenarios, such as smartphones, autonomous vehicles, security monitoring, and wearable devices, have stringent limitations on power consumption and heat dissipation. Low-power AI computing chips enable these devices to perform real-time intelligent processing directly on the terminal, eliminating the dependence on continuous network connections and cloud data backhaul, significantly reducing latency and protecting data privacy. Second, they directly determine the feasibility and sustainability of AI applications. In the fields of IoT and edge computing, devices often need to rely on batteries for long-term independent operation. Extremely high power consumption can quickly deplete the battery, causing application failure. Low-power AI computing chips, on the other hand, ensure that devices can operate stably for months or even years, greatly expanding the deployment boundaries of AI.

[0042] This invention provides a mixed-signal in-memory computing chip that effectively reduces the power consumption of the computing core. In-memory computing reduces data transfer power consumption, while mixed-signal operations reduce power consumption by decreasing signal amplitude. Although mixed-signal operations reduce power consumption, they require an analog-to-digital converter (ADC) to convert the voltage on the bit lines into digital signals for subsequent digital circuitry. However, in existing technologies, ADCs are susceptible to comparator offset during analog-to-digital conversion, leading to bit errors in the output digital signal. Furthermore, because AI computing chips require extremely high parallel processing, especially those supporting large-scale models, mixed-signal AI computing devices require a large number of ADCs, necessitating control over ADC area. Therefore, the in-memory computing device provided by this invention, based on mixed-signal processing and the aforementioned ADC with offset calibration function, achieves low power consumption, small area, low bit error rate, and supports operations requiring higher computing power, thus better supporting the AI ​​functions of AI computing chips and AI devices.

[0043] The in-memory computing device provided by this utility model is not only suitable for AI computing, but can also be applied to in-memory computing chips and neuromorphic chips, representing the mainstream big data computing chip architecture of the future.

[0044] In in-memory computing chip architectures, the traditional implementation architectures mainly fall into two categories: digital computing architecture and analog computing architecture. Digital computing architecture refers to the summation of matrix-vector products obtained by cascading multi-level addition trees to obtain the product of stored data and input vector data in the in-memory computing unit matrix. Analog computing architecture, on the other hand, refers to the summation of digital signals obtained by accumulating charges or currents through the accumulation of the product of stored data and input vector data in the in-memory computing unit matrix and then converting it into a digital signal by an analog-to-digital converter (ADC). The advantages of digital computing architecture are high computational reliability, less susceptible to fluctuations in process technology, temperature, and voltage, resulting in high computational accuracy and less susceptibility to data loss. However, the disadvantage of digital computing architecture is that due to the large number of addition trees used in computation, the power consumption and area required are several times greater than those of analog computing architecture. The advantages of analog computing architecture are low power consumption and high computational efficiency due to the use of charge or current accumulation for summation. Furthermore, the use of vertically stackable metal capacitors for charge or current voltage conversion saves a significant amount of area compared to the addition trees that occupy space from the bottom-level devices to the upper-level metal layers. However, the drawback of analog computing architecture is that it is easily affected by fluctuations in process, temperature, and voltage, which can affect the magnitude of calculated charge or current, especially the accumulation results of high-weight bits, resulting in a significant loss of calculation accuracy.

[0045] See Figure 5 and Figure 6In the preferred embodiment shown, the in-memory computing module in the in-memory computing device provided by this utility model is a mixed-signal based circuit. The in-memory computing module includes a first in-memory computing circuit (CIM) based on digital signals, a second in-memory computing circuit based on analog signals, and an accumulator. The first in-memory computing circuit performs multiplication and accumulation calculations on the input feature data and the high-weight bits of the weights based on a digital addition tree to obtain a first multiplication and accumulation result. The second in-memory computing circuit performs multiplication and accumulation calculations on the input feature data and the low-weight bits of the weights based on capacitance to obtain an analog multiplication and accumulation result. The analog-to-digital converter (ADC) is used to perform analog-to-digital conversion on the analog multiplication and accumulation result output by the second in-memory computing circuit to obtain a second digital multiplication and accumulation result. The accumulator is used to accumulate the first multiplication and accumulation result and the second multiplication and accumulation result. The analog-to-digital converter can be any of the ADCs provided by this utility model. The in-memory computing device provided by this utility model is based on mixed signals and the aforementioned ADC with offset calibration function, so that its offset voltage is completely calibrated or the offset voltage is calibrated to a relatively low level. The corresponding in-memory computing device has the advantages of low power consumption, small area, low bit error rate, and the ability to support operations requiring greater computing power, thereby better assisting the AI ​​functions of AI computing chips and AI devices.

[0046] like Figure 5 As shown, the first in-memory computing circuit includes an in-memory array and an addition tree. The in-memory array can perform in-memory multiplication calculations, and the addition tree performs addition, thus enabling the first in-memory computing circuit to achieve digital in-memory multiplication and accumulation. The second in-memory computing circuit includes an in-memory array and a capacitor array. The in-memory array can perform in-memory multiplication calculations, and the capacitors perform addition, thus enabling the second in-memory computing circuit to achieve analog in-memory multiplication and accumulation. Therefore, the above-mentioned in-memory computing device can achieve in-memory multiplication and accumulation calculations. When performing data calculations, the in-memory computing device provided by this utility model divides the data matrix into two parts according to weights: a high-weight bit matrix and a low-weight bit matrix. That is, it is equivalent to dividing the weights into two parts according to the bits, with the higher bits on the left being the high-weight bits and the remaining weight bits being the low-weight bits, so that part of the in-memory computing device is implemented digitally and part is implemented analogly. Preferably, the weights are divided into two parts on an average basis. Correspondingly, the first in-memory calculation circuit is configured as a digital structure for processing high-weight bits, and the second in-memory calculation circuit is configured as an analog structure for processing low-weight bits.

[0047] like Figure 6As shown, taking 8-bit data as an example, the high four bits are classified as high-weight bits and the low four bits as low-weight bits. However, this is only an example, and the architecture of this utility model also includes and is applicable to other grouping methods. The specific grouping can be determined based on a comprehensive consideration of the product's requirements for chip computing accuracy, power consumption, and area. For example, for applications requiring high accuracy in autonomous driving, the digital first-memory computing circuit is set up with more circuits than the analog second-memory computing circuit. For the calculation of high-weight bit matrix data, a multi-level cascaded addition tree digital computing circuit architecture with high computing accuracy, strong computing stability, and high computing reliability is adopted to ensure high computing accuracy and resistance to damage. For the calculation of low-weight bits, which have a lower impact on computing accuracy, an analog computing circuit architecture with low power consumption and small area for charge or current accumulation is adopted to reduce chip computing power consumption and chip area. like Figure 7 As shown, taking 8-bit unsigned data computation as an example, the mixed-signal-based in-memory computing device provided by this invention achieves a reduction in computational accuracy and stability from 50% to less than 3% compared to existing analog computing architectures. The mixed-signal-based in-memory computing device with offset voltage calibration function provided by this invention significantly reduces the area and power consumption of the in-memory computing chip. This invention can be applied to fields requiring high precision, high reliability, low power consumption, and low area cost, such as artificial intelligence and metaverse; artificial intelligence training or inference; autonomous driving chips; VR chips; robot embedded chips; wearable smart chips; and deep learning applications using parallel computing. This application also provides an electronic device that includes any of the aforementioned analog-to-digital converters or any of the aforementioned in-memory computing devices. It can be applied to computing centers, computing devices, edge computing, autonomous driving, AR, VR, LiDAR, and other related electronic devices, as well as a range of electronic devices such as smartphones, tablets, wearable electronic devices, smart home electronic products, industrial or medical or battery-powered devices.

[0048] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0049] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0050] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details are set forth in the above description for purposes of explanation.

[0051] It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. An analog-to-digital converter with offset calibration function, characterized in that, The analog-to-digital converter includes: a comparator for comparing an input voltage with a reference voltage, a latch for latching the comparison result of the comparator, and a calibration module for calibrating the offset voltage of the comparator. The calibration module includes: a coarse calibration circuit for coarse calibration of the comparator's offset voltage, a fine calibration circuit for fine calibration of the comparator's offset voltage, and a calibration control logic circuit for controlling the operation of the coarse calibration circuit and the fine calibration circuit. The calibration control logic circuit outputs a coarse calibration control signal to control the coarse calibration circuit to coarsely calibrate the comparator's offset voltage. The calibration control logic circuit also outputs a fine calibration control signal after coarse calibration to control the fine calibration circuit to perform fine calibration. The fine calibration circuit injects different charges into the two input terminals of the comparator according to the fine calibration control signal to introduce an input voltage, thereby canceling the comparator's offset voltage. The calibration range of the fine calibration circuit is larger than one calibration step of the coarse calibration circuit.

2. The analog-to-digital converter according to claim 1, characterized in that, The comparator includes a built-in internal latch, and the coarse calibration circuit is used to adjust the load capacitance of the two output terminals of the internal latch to calibrate the offset voltage of the comparator.

3. The analog-to-digital converter according to claim 2, characterized in that, The coarse calibration circuit includes: a first branch electrically connected to the first output terminal of the internal latch, and a second branch electrically connected to the second output terminal of the internal latch; The first branch includes several first switched capacitor branches connected in parallel. Each first switched capacitor branch includes a first switch and a first capacitor. One end of the first switch is electrically connected to the first output terminal of the internal latch, and the other end of the first switch is grounded through the first capacitor. The control terminal of the first switch is connected to the calibration control logic circuit to receive the coarse calibration control signal. The second branch includes several second switched capacitor branches connected in parallel. Each second switched capacitor branch includes a second switch and a second capacitor. One end of the second switch is electrically connected to the second output terminal of the internal latch, and the other end of the second switch is grounded through the second capacitor. The control terminal of the second switch is connected to the calibration control logic circuit to receive the coarse calibration control signal.

4. The analog-to-digital converter according to claim 1, characterized in that, The calibration control logic circuit is used to control the fine calibration circuit to inject a preset calibration voltage into the input terminal of the comparator to find a compensation voltage that can compensate for the offset voltage of the comparator. The calibration control logic circuit is also used to apply the compensation voltage to the comparator when the comparator is working.

5. The analog-to-digital converter according to claim 4, characterized in that, The fine calibration circuit includes: a plurality of third branches electrically connected to the first input terminal of the comparator, and a plurality of fourth branches electrically connected to the second input terminal of the comparator; Each of the third branches includes a third capacitor and a third switch. One end of the third capacitor is electrically connected to the first input terminal of the comparator, and the other end of the third capacitor is electrically connected to one end of the third switch. The control terminal of the third switch is connected to the calibration control logic circuit so that the other end of the third switch switches between power supply VDD and ground, thereby injecting charge. Each of the fourth branches includes a fourth capacitor and a fourth switch. One end of the fourth capacitor is electrically connected to the second input terminal of the comparator, and the other end of the fourth capacitor is electrically connected to one end of the fourth switch. The control terminal of the fourth switch is connected to the calibration control logic circuit so that the other end of the fourth switch switches between power supply VDD and ground, thereby injecting charge.

6. The analog-to-digital converter according to any one of claims 1 to 5, characterized in that, The comparator includes: switching transistors M0, M1a, M1b, M2a, M2b, M3, M4, M5, and M6; The power supply VDD is connected to ground sequentially through the switching transistors M3, M1b, M1a, and M0, and also connected to ground sequentially through the switching transistors M6, M2b, M2a, and M0. The control terminals of the switching transistors M1a and M1b are connected together to form the first input terminal of the comparator. The connection point of the switching transistors M1a and M1b is connected to the power supply VDD through the switching transistor M4, and the connection point of the switching transistors M1a and M1b is electrically connected to the coarse calibration circuit. The control terminals of the switching transistors M2a and M2b are connected together to form the second input terminal of the comparator. The connection point of the switching transistors M2a and M2b is connected to the power supply VDD through the switching transistor M5, and the connection point of the switching transistors M2a and M2b is electrically connected to the coarse calibration circuit. The control terminals of the switching transistors M0, M3, M4, M5, and M6 are all connected to the first clock signal CLK.

7. The analog-to-digital converter according to any one of claims 1 to 5, characterized in that, The latch includes: switching transistors M7, M8, M9, M10, M11, M12, M13, and M14; The power supply VDD is connected to the control terminals of the switching transistors M10 and M12 in sequence through switching transistors M9 and M7. The control terminal of the switching transistor M7 is connected to the second output terminal Vmn of the comparator. The power supply VDD is connected to the control terminals of the switching transistors M9 and M11 in sequence through switching transistors M10 and M8. The control terminal of the switching transistor M8 is connected to the first output terminal Vmp of the comparator. The control terminal of the switching transistor M10 is connected to ground through the switching transistor M13. The control terminal of the switching transistor M10 is also connected to ground through the switching transistor M11. The control terminal of the switching transistor M9 is connected to ground through the switching transistor M12. The control terminal of the switching transistor M9 is also connected to ground through the switching transistor M14. The control terminals of both switching transistors M13 and M14 are connected to the second clock signal nCLK.

8. A storage-and-computing integrated device, characterized in that, include: An in-memory computing module and an analog-to-digital converter for converting the analog multiply-accumulate result output by the in-memory computing module into a digital signal, wherein the analog-to-digital converter is the analog-to-digital converter according to any one of claims 1 to 7.

9. The in-memory computing device according to claim 8, characterized in that, The in-memory calculation module includes: a first in-memory calculation circuit based on digital signals, a second in-memory calculation circuit based on analog signals, and an accumulator. The first in-memory calculation circuit performs multiplication and accumulation calculation on the input feature data and the high-weight bits of the weights based on a digital addition tree to obtain a first multiplication and accumulation result. The second in-memory calculation circuit performs multiplication and accumulation calculation on the input feature data and the low-weight bits of the weights based on a capacitor to obtain an analog multiplication and accumulation result. The analog-to-digital converter is used to perform analog-to-digital conversion on the analog multiplication and accumulation result output by the second in-memory calculation circuit to obtain a second multiplication and accumulation result. The accumulator is used to accumulate the first multiplication and accumulation result and the second multiplication and accumulation result.

10. An electronic device, characterized in that, The analog-to-digital converter includes any one of claims 1 to 7.

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