A capacitor
Patent Information
- Application Number
- CN202522578196.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-04
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-12-04
AI Technical Summary
Existing ceramic capacitors struggle to achieve small capacitance while maintaining a large bonding area, and they also suffer from increased dielectric loss and decreased insulation performance in high-frequency applications.
Employing a multilayer structure design, the device fabricates nanoscale thin-film dielectric layers and conductive vias on a glass substrate, and combines this with TGV technology to achieve electrical interconnection. By utilizing the low-loss characteristics of silicon oxide and silicon nitride materials, the bonding area is expanded and the dielectric layer thickness is controlled to achieve small capacity and high insulation.
It achieves capacitors with small capacity and large bonding area, low loss and high insulation performance, suitable for high frequency applications, and low cost and easy large-size mass production.
Smart Images
Figure CN224935988U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic components technology, specifically to a capacitor. Background Technology
[0002] The capacitance of a ceramic capacitor is determined by both its dielectric layer area and the dielectric constant of the material. This characteristic leads to inherent limitations in its structural design and performance balance. Existing ceramic capacitors struggle to meet the demand for "small capacitance and large bonding area." For example, when a product requires a bonding area of 4mm × 1mm, the dielectric layer area of the ceramic capacitor must also reach a similar size, and this area directly determines the capacitance. Therefore, it is impossible to maintain a large bonding area while keeping the capacitance at a low level. Furthermore, in terms of electrical performance, the temperature drift, loss tangent, and insulation performance of ceramic capacitors are all closely related to the dielectric constant of the ceramic material. In applications with stringent requirements for low temperature drift, low loss, and high insulation performance (such as high-frequency or high-reliability circuits), traditional ceramic capacitors often struggle to achieve all these specifications simultaneously. Especially when the capacitor size is fixed and an increase in capacitance is required, a high dielectric constant ceramic material must be used. However, this usually leads to increased dielectric loss and decreased insulation resistance, which in turn affects the capacitor's high-frequency characteristics and overall stability. Therefore, although ceramic capacitor technology is mature and widely used, the inherent constraints between its materials and structure pose significant challenges when pursuing comprehensive performance such as small capacity, large bonding area, low loss and high insulation. Utility Model Content
[0003] Therefore, the purpose of this invention is to provide a capacitor. The capacitor provided by this invention can achieve small capacitance and large bonding area, and has the characteristics of low loss and high insulation.
[0004] To achieve the above-mentioned objectives, this utility model provides the following technical solution: This invention provides a capacitor comprising a substrate having a first through-hole, a first metal bonding layer located on the lower surface of the substrate, a first electrode layer located on the upper surface of the substrate, the area of the first electrode layer being smaller than the area of the substrate, a first dielectric layer located on the surface of the first electrode layer, a second dielectric layer surrounding the first electrode layer, a second electrode layer located on the surface of the first dielectric layer, an insulating buffer layer located on the surfaces of the second electrode layer and the second dielectric layer, a second metal bonding layer located on the surface of the insulating buffer layer, and a second through-hole disposed in the insulating buffer layer between the second electrode layer and the second metal bonding layer, wherein the first through-hole and the second through-hole are filled with conductive metal; the thickness of the first dielectric layer and the second dielectric layer is independently 60~800nm.
[0005] Preferably, the first metal bonding layer and the second metal bonding layer independently comprise a composite metal bonding layer composed of layers M1, M2 and M3, or a composite metal bonding layer composed of layers M1 and M3; the material of layer M1 independently comprises Ti, and the thickness is independently 200~400nm; the material of layer M2 comprises Ni and / or Pd, and the thickness is 200~400nm; the material of layer M3 independently comprises Au and / or Cu, and the thickness is independently 1~5μm.
[0006] Preferably, the first electrode layer and the second electrode layer independently include a composite metal electrode layer composed of an M4 layer, an M5 layer and an M6 layer. The M4 layer is made of Ti and has a thickness of 100~300nm; the M5 layer is made of Cu and / or Al and has a thickness of 200~700nm; and the M6 layer is made of Ti and has a thickness of 100~300nm.
[0007] Preferably, the materials of the first dielectric layer and the second dielectric layer independently comprise silicon oxide and / or silicon nitride.
[0008] Preferably, the insulating buffer layer is made of one or more of polyimide, silicon oxide, and silicon nitride.
[0009] Preferably, an adhesive layer is further provided between the second electrode layer and the insulating buffer layer.
[0010] Preferably, the conductive metal layer filling the first through hole includes an M7 layer and an M8 layer stacked sequentially. The material of the M7 layer includes Ti and the thickness is 50~100nm. The material of the M8 layer includes Cu and / or Al. The diameter of the first through hole is 27~33μm, the hole spacing is 54~66μm, and the hole perpendicularity is 78~88°.
[0011] Preferably, the conductive metal layer filling the second via comprises sequentially stacked M9 layers and M... 10 The M9 layer is made of Ti and has a thickness of 50-100 nm; the M... 10 The material of the layer includes Cu and / or Al; the diameter of the second through hole is 8~12μm, the hole spacing is 16~24μm, and the hole perpendicularity is 78~88°.
[0012] Preferably, the substrate includes a glass substrate, a silicon substrate, or a gallium arsenide substrate.
[0013] Preferably, the thickness of the substrate is 250~300μm.
[0014] Currently, in the field of electronic components, the demand for small capacity and large bonding area is becoming increasingly prominent. Traditional ceramic capacitors, because the area of the dielectric layer must be comparable to the bonding area, and the area directly determines the capacitance, make it difficult to achieve small capacity while maintaining a large bonding area. However, the capacitor provided by this utility model, with its multi-layer structure design, can reduce the size of the dielectric layer in a larger product to form a capacitor. Then, through the use of an insulating protective layer as a passivation layer, a first through-hole (e.g., a glass through-hole TGV), a second through-hole, and redistribution technology (connecting the first electrode layer and the second electrode layer in the capacitor through the first through-hole, the second through-hole, the first metal bonding layer, and the second metal bonding layer), the bonding area is expanded to the required size. This multi-layer structure design fundamentally solves the contradiction between small capacity and large bonding area, and realizes independent control of the size of the dielectric region and the bonding region.
[0015] In terms of performance, ceramic capacitors, with a fixed size, typically rely on increasing the dielectric constant of the ceramic material to increase capacitance. However, this often results in increased dielectric loss and decreased insulation performance, thus affecting high-frequency characteristics. In contrast, the capacitor provided by this invention has a nano-scale thin film dielectric layer, which is several orders of magnitude thinner than ceramic materials (hundreds of micrometers), enabling a higher capacitance value to be achieved in the same area.
[0016] Furthermore, silicon nitride / silicon oxide, as the dielectric, possesses extremely low loss tangent and excellent high-frequency characteristics, ensuring the stability and reliability of the capacitor in high-frequency, high-requirement applications from a material perspective.
[0017] Furthermore, when the substrate is glass, the capacitor provided by this invention is a glass-based capacitor. As an integrated component "grown" on a glass substrate, the glass-based capacitor combines the excellent insulation properties, good high-frequency characteristics, mature manufacturing process, and low cost of glass itself. It already has a wide range of applications in display, photovoltaic, and packaging fields, and is theoretically an ideal capacitor substrate material. Combining the current mature TGV process with the ability to prepare silicon nitride and silicon oxide dielectric layers, the glass-based capacitor provided by this invention is expected to achieve a balance between wide capacitance coverage and high performance, providing a new technological path for the development of next-generation electronic components.
[0018] Glass-based capacitors are essentially thin-film MIM capacitors integrated on the TGV process platform. The glass substrate used in this invention is not only inexpensive and easy to mass-produce in large sizes, but its excellent insulation, thermal stability, and compatibility with silicon processes provide an ideal technical platform for achieving capacitor products with high consistency and a wide tolerance range. This method of "growing" passive components on a substrate provides a new technical path for system-in-package (SiP) and the integration and cost reduction of future electronic components.
[0019] The capacitor provided by this utility model takes "electrical interconnection" as its core. The substrate and interconnection channel are formed, and then the conductive layer, insulating buffer layer and bonding layer are prepared in sequence. The parameters of each step are matched with each other, and finally a highly reliable and high-density 3D integrated interconnection structure is achieved. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a capacitor. Figure 2 This is a flowchart of the capacitor manufacturing process; Figure 3 This is a perspective view of the capacitor in Example 1; Figure 4 This is a side view of the capacitor in Example 1; Figure 5 This is a top view of the capacitor in Example 1; Figure 6 This is a perspective view of the capacitor in Example 2; Figure 7 This is a side view of the capacitor in Example 2; Figure 8 This is a top view of the capacitor in Example 2; Figure 9 This is a measured capacitance distribution diagram of the capacitor in Example 1; Figure 10 This is a measured insulation resistance distribution diagram of the capacitor in Example 1; Figure 11 This is a distribution diagram of the measured loss tangent of the capacitor in Example 1. Detailed Implementation
[0021] This invention provides a capacitor comprising a substrate having a first through-hole, a first metal bonding layer located on the lower surface of the substrate, a first electrode layer located on the upper surface of the substrate, the area of the first electrode layer being smaller than the area of the substrate, a first dielectric layer located on the surface of the first electrode layer, a second dielectric layer surrounding the first electrode layer, a second electrode layer located on the surface of the first dielectric layer, an insulating buffer layer located on the surfaces of the second electrode layer and the second dielectric layer, a second metal bonding layer located on the surface of the insulating buffer layer, and a second through-hole disposed in the insulating buffer layer between the second electrode layer and the second metal bonding layer, wherein the first through-hole and the second through-hole are filled with conductive metal.
[0022] See the structural diagram of the capacitor. Figure 1 The following is combined with Figure 1 The structure of the capacitor is described in detail.
[0023] The capacitor provided by this utility model includes a substrate with a first through hole. In one specific embodiment of this utility model, the substrate may include a glass substrate, a silicon substrate, or a gallium arsenide substrate; the glass substrate may include a BF33 glass substrate or an SG3.4 glass substrate. In another specific embodiment of this utility model, the performance indicators of the glass substrate may include: a density of 2.2~2.4 g / cm³. 3 Specifically, it can be expressed as 2.2 g / cm³. 3 2.25g / cm 3 2.3g / cm 3 2.35g / cm 3 Or 2.4g / cm 3 Young's modulus is 72~74 GPa, specifically 72 GPa, 72.5 GPa, 73 GPa, 73.5 GPa or 74 GPa; Poisson's ratio is 0.16~0.21, specifically 0.16, 0.17, 0.18, 0.19, 0.2 or 0.21; shear modulus is 30~32 GPa, specifically 30 GPa, 30.5 GPa, 31 GPa, 31.5 GPa or 32 GPa; Vickers hardness at a 200g load is 600~700 kgf / mm. 2 Specifically, it can be 600 kgf / mm 2 620kgf / mm 2 640kgf / mm 2 660kgf / mm 2 680kgf / mm 2 Or 700 kgf / mm 2 At 250℃, Log 10 The volume resistivity is 12~13 Ω·cm, specifically 12 Ω·cm, 12.2 Ω·cm, 12.4 Ω·cm, 12.6 Ω·cm, 12.8 Ω·cm, or 13 Ω·cm; the coefficient of thermal expansion in the range of 0~300℃ is (2~5)×10⁻⁶. -6 / ℃, which can be specifically 2×10 -6 / ℃, 2.5×10 -6 / ℃, 3×10 -6 / ℃, 3.5×10 -6 / ℃, 4×10 -6 / ℃, 4.5×10 -6 / ℃ or 5×10 -6 / ℃; fracture toughness is 0.7~1MPa・m 0.5 Specifically, it can be expressed as 0.7 MPa·m 0.5 0.8 MPa·m 0.5 0.9 MPa·m 0.5 or 1 MPa·m 0.5In one specific embodiment of this invention, the thickness of the substrate can be 250~300μm, specifically 250μm, 260μm, 270μm, 280μm, 290μm, or 300μm. The substrate used in this invention provides the capacitor with mechanical strength, insulation properties, thermal stability, and processing performance, ensuring successful capacitor fabrication and providing structural support and performance assurance for the final capacitor. In one specific embodiment of this utility model, the first through hole is filled with a conductive metal layer, which may include M7 layer and M8 layer stacked sequentially; the material of M7 layer may include Ti, and the thickness of M7 layer may be 50~100nm, specifically 50nm, 6nm, 70nm, 80nm, 90nm or 100nm; the material of M8 layer may include Cu and / or Al. In one specific embodiment of this utility model, the diameter of the first through hole can be 27~33μm, or 28~31μm, specifically 27μm, 28μm, 29μm, 30μm, 31μm, 32μm or 33μm; the hole spacing of the first through hole can be 54~66μm, or 58~62μm, specifically 54μm, 55μm, 56μm, 57μm, 58μm, 59μm, 60μm, 61μm, 62μm, 63μm, 64μm, 65μm or 66μm; the verticality (Via taper) of the first through hole is 78~88°, or 80~86°, specifically 78°, 79°, 80°, 81°, 82°, 83°, 84°, 85° or 86°. In one specific embodiment of this utility model, the arrangement and number of the first through holes are determined according to the thickness of the first dielectric layer, provided that the breakdown voltage requirement is met, and the diameter and spacing of the first through holes remain unchanged.
[0024] In one specific embodiment of this utility model, the first through hole filled with conductive metal serves to provide a vertical conductive channel, enabling electrical interconnection between the first electrode layer and the first metal bonding layer located on the upper and lower surfaces of the substrate, thus providing a key interconnection structure for 3D integration.
[0025] The capacitor provided by this utility model includes a first metal bonding layer located on the lower surface of the substrate. As a specific embodiment of this utility model, the first metal bonding layer may include a composite metal bonding layer (denoted as M1 / M2 / M3) composed of layers M1, M2, and M3, or a composite metal bonding layer (denoted as M1 / M3) composed of layers M1 and M3; the material of layer M1 may independently include Ti, and the thickness of layer M1 may independently be 200~400 nm, or 250~350 nm, specifically 200 nm, 250 nm, 300 nm, or 350 nm. The M2 layer can be made of Ni and / or Pd, and its thickness can be 200-400 nm, or 250-350 nm, specifically 200 nm, 250 nm, 300 nm, 350 nm, or 400 nm. The M3 layer can be made of Au and / or Cu, and its thickness can be 1-5 μm, or 2-4 μm, specifically 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm. In one specific embodiment of this invention, the roughness of the first metal bonding layer can be ±25 nm, specifically ±1 nm, ±5 nm, ±10 nm, ±15 nm, ±20 nm, or ±25 nm. In another specific embodiment of this invention, the first metal bonding layer serves to meet the product mounting bonding requirements and connect to the first electrode.
[0026] The capacitor provided by this invention includes a first electrode layer located on the upper surface of the substrate. In one specific embodiment of this utility model, the first electrode layer may include a composite metal electrode layer (denoted as M4 / M5 / M6) composed of an M4 layer, an M5 layer, and an M6 layer; the material of the M4 layer may include Ti, and the thickness of the M4 layer may be 100~300nm, or 150~250nm, specifically 100nm, 150nm, 200nm, 250nm, or 300nm; the material of the M5 layer may include Cu and / or Al, and the thickness of the M5 layer may be 200~700nm, or 300~500nm, specifically 200nm, 300nm, 400nm, 500nm, 600nm, or 700nm; the material of the M6 layer may include Ti, and the thickness of the M6 layer may be 100~300nm, or 150~250nm, specifically 100nm, 150nm, 200nm, 250nm, or 300nm. In one specific embodiment of this utility model, the area of the first electrode layer is smaller than the area of the substrate, and the area of the first electrode layer can account for 50% to 80% of the area of the substrate, specifically 50%, 55%, 60%, 65%, 70%, 75%, or 80%. In another specific embodiment of this utility model, the roughness of the first electrode layer can be within ±25nm, specifically ±1nm, ±5nm, ±10nm, ±15nm, ±20nm, or ±25nm.
[0027] The capacitor provided by this invention includes a first dielectric layer located on the surface of a first electrode layer and a second dielectric layer surrounding the first electrode layer. In one specific embodiment of this invention, the materials of the first and second dielectric layers may independently include silicon oxide and / or silicon nitride. Silicon nitride and / or silicon oxide, as dielectrics, inherently possess extremely low loss tangent and excellent high-frequency characteristics, ensuring the stability and reliability of the capacitor in high-frequency, high-requirement applications from a material perspective.
[0028] In one specific embodiment of this utility model, the thickness of the first dielectric layer and the second dielectric layer is independently 200~800nm, or 600~800nm, specifically 200nm, 300nm, 400nm, 500nm, 600nm, 700nm or 800nm; the absolute value of the breakdown voltage of the first dielectric layer and the second dielectric layer can be ≥150V, or 150~600V, specifically 150V, 200V, 250V, 300V, 350V, 400V, 450V, 500V, 550V or 600V.
[0029] In one specific embodiment of this invention, the first and second dielectric layers provide interlayer insulation, achieving electrical isolation between the first and second electrode layers. The capacitor's performance is adjusted by regulating and controlling the thickness. The thickness of the dielectric layer is a crucial factor affecting the capacitor's capacitance. Adjusting the thickness of the first and second dielectric layers can regulate the capacitor's capacitance and breakdown voltage; a thicker dielectric layer results in a higher breakdown voltage. In terms of performance, ceramic capacitors, with fixed dimensions, typically rely on increasing the dielectric constant of the ceramic material to increase capacitance. However, this often leads to increased dielectric loss and decreased insulation performance, thus affecting high-frequency characteristics. In contrast, the capacitor provided by this invention uses a nano-scale thin film dielectric layer, with a thickness far lower than that of ceramic materials (hundreds of micrometers), achieving a higher capacitance value within the same area.
[0030] The capacitor provided by this invention includes a second electrode layer located on the surface of the first dielectric layer. In one specific embodiment of this invention, the material and thickness of the second electrode layer can be the same as those of the first electrode layer, and will not be described further here. In another specific embodiment of this invention, the second electrode layer serves as a signal input / output terminal, enabling connection to an external circuit.
[0031] The capacitor provided by this invention includes an insulating buffer layer located on the surface of the second electrode layer and the second dielectric layer. In one specific embodiment of this invention, the insulating buffer layer may be made of one or more of polyimide (PI), silicon oxide, and silicon nitride; the thickness of the insulating buffer layer may be 2-5 μm, or 2.5-4.5 μm, or further 3-4 μm. In another specific embodiment of this invention, the insulating buffer layer is a structural filling layer, possessing insulating and buffering functions, capable of alleviating thermal stress between different materials (electrode layer, substrate, metal bonding layer), and providing a flat substrate for the second metal bonding layer.
[0032] In one specific embodiment of this utility model, an insulating buffer layer located between the second electrode layer and the second metal bonding layer is provided with a second through-hole, and the second through-hole is filled with a conductive metal layer, which may include M9 layers and M... stacked sequentially. 10 The M9 layer; the material of the M9 layer may include Ti, and the thickness of the M9 layer may be 50~100nm, specifically 50nm, 6nm, 70nm, 80nm, 90nm or 100nm; the M... 10The layer material includes Cu and / or Al. In one specific embodiment of this invention, the diameter of the second through hole can be 8~12μm, or 9~11μm, specifically 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 10.5μm, 11μm, 11.5μm, or 12μm; the hole spacing of the second through hole can be 16~24μm, or 18~22μm, specifically 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, or 24μm; the perpendicularity of the second through hole can be 78~88°, or 80~86°, specifically 78°, 79°, 80°, 81°, 82°, 83°, 84°, 85°, or 86°. In one specific embodiment of this utility model, the number of the second through holes is determined according to the thickness of the first dielectric layer, provided that the breakdown voltage requirement of the insulating buffer layer is met, and the diameter and spacing of the second through holes remain unchanged.
[0033] In one specific embodiment of this invention, an adhesive layer may be further provided between the second electrode layer and the insulating buffer layer. This invention does not have a specific limitation on the adhesive layer, as long as it can achieve a firm adhesion between the second electrode layer and the insulating buffer layer, such as a titanium layer, a titanium-tungsten layer, or a nickel-chromium film layer.
[0034] The capacitor provided by this invention includes a second metal bonding layer located on the surface of the insulating buffer layer. In one specific embodiment of this invention, the roughness of the second metal bonding layer can be within ±50 nm, specifically ±5 nm, ±10 nm, ±20 nm, ±30 nm, ±40 nm, or ±50 nm.
[0035] In one specific embodiment of this invention, the material and thickness of the second metal bonding layer can be the same as those of the first metal bonding layer, and will not be described again here. In another specific embodiment of this invention, the function of the second metal bonding layer is to achieve bonding with the chip or external circuit, ensuring the reliability of the interconnection.
[0036] Currently, in the field of electronic components, the demand for small capacity and large bonding area is becoming increasingly prominent. Traditional ceramic capacitors, because the area of the dielectric layer must be comparable to the bonding area, and the area directly determines the capacitance, make it difficult to achieve small capacity while maintaining a large bonding area. However, the capacitor provided by this utility model, with its multi-layer structure design, can reduce the size of the dielectric layer in larger products to form a capacitor. Then, through the use of an insulating buffer layer as a passivation layer for protection, a first through-hole (such as a glass through-hole TGV), a second through-hole, and redistribution technology, the bonding area is expanded to the required size, thus fundamentally solving the contradiction between small capacity and large bonding area in its structure.
[0037] As a specific embodiment of this utility model, the method for preparing the capacitor includes the following steps: A first through hole is formed by drilling holes in the substrate, and conductive metal is filled into the first through hole. A first metallization treatment is performed on the upper surface of the substrate to form a first electrode layer, and a second metallization treatment is performed on the lower surface of the substrate to form a first metal bonding layer. A first dielectric layer is prepared on the surface of the first electrode layer, and a second dielectric layer is prepared on the surface of the exposed substrate; A third metallization process is performed on the surface of the first dielectric layer to form a second electrode layer; An insulating buffer layer is prepared on the surface of the second electrode layer and the second dielectric layer, and a second through hole is formed by punching holes in the insulating buffer layer on the surface of the second electrode layer. A fourth metallization process is performed on the surface of the insulating buffer layer to form a second metal bonding layer, thereby obtaining a capacitor.
[0038] Unless otherwise specified, the materials and equipment used in this utility model are all commercially available products in this field.
[0039] This invention involves drilling holes in a substrate to form a first through-hole, filling the first through-hole with conductive metal, performing a first metallization treatment on the upper surface of the substrate to form a first electrode layer, and performing a second metallization treatment on the lower surface of the substrate to form a first metal bonding layer.
[0040] In one specific embodiment of this invention, the methods for filling the conductive metal, the first metallization treatment, and the second metallization treatment include physical vapor deposition and / or electroplating. This invention does not specifically limit the process conditions for the physical vapor deposition and electroplating, as long as the aforementioned conductive metal, first electrode layer, and first metal bonding layer are obtained. The function of this step is to convert the TGV into a conductive channel by filling the first via with metal and forming the first electrode layer and the first metal bonding layer on the substrate surface, and to provide a conductive substrate for the subsequent fabrication of the electrode layer and dielectric layer. This invention prepares a first dielectric layer on the surface of the first electrode layer and a second dielectric layer on the surface of the exposed substrate. This invention does not specify a particular method for preparing the first dielectric layer; any method that achieves the aforementioned first and second dielectric layers is acceptable.
[0041] This invention involves performing a third metallization treatment on the surface of the first dielectric layer to form a second electrode layer. In one specific embodiment of this invention, the third metallization treatment method includes physical vapor deposition and / or electroplating. This invention does not impose special limitations on the process conditions for the physical vapor deposition and electroplating, as long as the aforementioned material and thickness of the second electrode layer can be obtained.
[0042] This invention prepares an insulating buffer layer on the surface of the second electrode layer and the second dielectric layer, and then punches holes in the insulating buffer layer on the surface of the second electrode layer to form a second through-hole. This invention does not have a specific limitation on the preparation method of the insulating buffer layer, as long as the aforementioned insulating buffer layer can be obtained.
[0043] This invention involves performing a fourth metallization treatment on the surface of the insulating buffer layer to form a second metal bonding layer, thereby obtaining a capacitor. As a specific embodiment of this invention, the fourth metallization treatment method includes physical vapor deposition and / or electroplating. This invention does not impose special limitations on the process conditions for the physical vapor deposition and electroplating, as long as the aforementioned defined second metal bonding layer can be obtained.
[0044] The capacitor provided by this invention has excellent application prospects in the fields of display, solar photovoltaic, or packaging.
[0045] To further illustrate this utility model, the capacitor provided by this utility model will be described in detail below with reference to the embodiments, but these should not be construed as limiting the scope of protection of this utility model.
[0046] Example 1 according to Figure 2 The process flow diagram shown illustrates the fabrication of glass-based capacitors. Figures 3-8 The views shown are, in order: oblique view, side view, top view, oblique view, side view, and top view of a glass-based capacitor.
[0047] Step 1: Selection of glass substrate The performance indicators of the glass substrate are as follows: density is 2.2~2.4 g / cm³. 3 Young's modulus is 72~74 GPa; Poisson's ratio is 0.16~0.21; shear modulus is 30~32 GPa; Vickers hardness under 200g load is 600~700 kgf / mm². 2 At 250℃, Log 10 The volume resistivity is 12~13 Ω·cm; the coefficient of thermal expansion in the range of 0~300℃ is (0.5~2)×10⁻⁶. -6 / ℃; fracture toughness is 0.7~1MPa・m 0.5 The thickness is 250~300μm.
[0048] Step 2: Glass Drilling (TGV): A first through hole is formed by drilling at a designated location on the glass substrate. The diameter of the first through hole is 30±3μm, the hole spacing is 60±6μm, and the hole perpendicularity is 83±5°. The glass through holes are distributed at the center of the glass substrate.
[0049] Step 3: Glass holes and surface metallization The glass holes and glass substrate surfaces formed in step 1 are metallized. The first through-hole is filled with metal using a combination of physical vapor deposition (PVD) and electroplating. The filling metal is Ti / Al. X-ray inspection confirms that the filling pass rate is >95% and the filling state is solid filling.
[0050] A first electrode layer is fabricated on the upper surface of a glass substrate using PVD technology, and a first metal bonding layer is fabricated on the lower surface of the glass substrate. The first electrode layer is a Ti / Al / Ti composite metal layer with thicknesses of 200 nm / 600 nm / 200 nm, respectively. The first bonding layer is a Ti / Cu composite metal layer with thicknesses of 200 nm / 1000 nm, respectively. The roughness of both the first electrode layer and the first metal bonding layer is within ±25 nm (within 10 mm). 2 Within the area).
[0051] Step 4: Dielectric layer preparation A dielectric layer is prepared on the surface of the first electrode layer and the exposed glass substrate. The dielectric layer is made of silicon nitride, with a thickness of 600~800nm, a breakdown voltage (absolute value) >450V, and a maximum breakdown voltage of 600V (obtained by testing during step 4).
[0052] Step 5: Fabrication of the second electrode layer A second electrode layer is fabricated on the surface of the first dielectric layer using a PVD process. The second electrode layer is a Ti / Al / Ti composite metal layer with thicknesses of 200 nm / 600 nm / 200 nm, respectively, and a roughness within ±25 nm (within 10 mm). 2 Within the area).
[0053] Step 6: Preparation of the insulating buffer layer An insulating buffer layer is prepared on the surface of the second electrode layer and the second dielectric layer. A second through-hole is formed by drilling holes in the insulating buffer layer on the surface of the second electrode layer. The second through-hole is filled with metal. The insulating buffer layer material is polyimide (PI) with a thickness of 3.5 μm. The diameter of the second through-hole is 10 ± 2 μm and the hole spacing is 20 ± 4 μm. The metal filled in the second through-hole is Ti / Al. X-ray detection confirmed that the hole filling qualification rate is >95% and the hole filling state is solid filling. Step 7: Preparation of the second metal bonding layer A second metal bonding layer was fabricated on the insulating buffer layer using PVD technology to obtain a glass-based capacitor. The second metal bonding layer is a Ti / Ni / Au composite metal layer with thicknesses of 200 nm / 300 nm / 1000 nm, respectively, and a roughness within ±50 nm (within 10 mm). 2 Within the area).
[0054] Example 2 The glass-based capacitor was prepared according to the method of Example 1, with the only difference from Example 1 being that: the first through-hole is distributed at the edge of the glass substrate, and the closest distance between the edge of the first through-hole and the dielectric layer is 20≥d1≥8μm, and the distance between the edge of the second electrode layer and the edge of the first through-hole is 50≥d2≥20μm.
[0055] Test Example 1 1. Capacity test Test method: Measurements were performed according to Method 305 of GJB 360B-2009, with the following details: Test frequency: (1±0.05) MHz for capacitance ≤ 100pF; (1±0.1) kHz for capacitance > 100pF; Test voltage: (1.0±0.2) Vrms. Capacity test results are shown below. Figure 9 As can be seen, the capacitance accuracy of the glass-based capacitor prepared by this invention is within ±2.5%, which is extremely high.
[0056] 2. Insulation resistance test Test conditions: The capacitor shall be measured according to Method 302 of GJB 360B-2009, and the following rules shall be followed: the specified rated voltage shall be applied through a series resistor sufficient to limit the charging current to a maximum of 50mA; Special conditions: if the insulation resistance fails at a relative humidity greater than 50%, the insulation resistance may be measured again at any relative humidity less than 50%; the insulation resistance test results of the glass-based capacitor in Example 1 are shown in [reference to example 1]. Figure 10 It can be seen that the insulation resistance of the glass-based capacitor prepared by this invention is around 10¹³Ω, which is excellent.
[0057] 3. Loss tangent test Test method: The capacitor shall be measured according to Method 305 of GJB 360B-2009, and the following details shall be adopted: Test frequency: (1±0.05) MHz when capacitance ≤ 100pF; (1±0.1) kHz when capacitance > 100pF; Test voltage: (1.0±0.2) Vrms; The test results of the loss tangent distribution of the glass-based capacitor in Example 1 are shown in [reference to example 1]. Figure 11 It can be seen that the loss tangent of the glass-based capacitor prepared by this invention is ≤0.0010, which is a typical low loss tangent product.
[0058] In summary, the glass-based capacitor provided by this invention is a type of capacitor formed by using glass as a substrate, combining TGV technology to achieve vertical interconnection, and preparing a uniform and dense dielectric layer on the substrate surface through chemical vapor deposition (CVD). This structure of capacitor possesses advantages such as a wide adjustable capacitance range, good high-frequency performance, and strong quality consistency. Furthermore, glass substrates not only have lower raw material costs but are also easier to mass-produce in large sizes compared to ceramic substrates, providing significant room for subsequent cost control. The glass-based capacitor provided by this invention exhibits extremely excellent performance in terms of capacitance accuracy, insulation resistance, and loss tangent.
[0059] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. A capacitor, characterized in that, The device includes a substrate with a first through-hole, a first metal bonding layer on the lower surface of the substrate, a first electrode layer on the upper surface of the substrate, the area of the first electrode layer being smaller than the area of the substrate, a first dielectric layer on the surface of the first electrode layer, a second dielectric layer surrounding the first electrode layer, a second electrode layer on the surface of the first dielectric layer, an insulating buffer layer on the surfaces of the second electrode layer and the second dielectric layer, a second metal bonding layer on the surface of the insulating buffer layer, and a second through-hole disposed in the insulating buffer layer between the second electrode layer and the second metal bonding layer. The first and second through-holes are filled with conductive metal. The thicknesses of the first and second dielectric layers are independently 60~800nm.
2. The capacitor according to claim 1, characterized in that, The first metal bonding layer and the second metal bonding layer independently include a composite metal bonding layer composed of layers M1, M2 and M3, or a composite metal bonding layer composed of layers M1 and M3; the material of layer M1 independently includes Ti, and the thickness is independently 200~400nm; the material of layer M2 includes Ni and / or Pd, and the thickness is 200~400nm; the material of layer M3 independently includes Au and / or Cu, and the thickness is independently 1~5μm.
3. The capacitor according to claim 1, characterized in that, The first electrode layer and the second electrode layer independently include a composite metal electrode layer composed of an M4 layer, an M5 layer and an M6 layer. The material of the M4 layer includes Ti and the thickness is 100~300nm. The material of the M5 layer includes Cu and / or Al and the thickness is 200~700nm. The material of the M6 layer includes Ti and the thickness is 100~300nm.
4. The capacitor according to claim 1, characterized in that, The materials of the first dielectric layer and the second dielectric layer independently include silicon oxide and / or silicon nitride.
5. The capacitor according to claim 1, characterized in that, The insulating buffer layer is made of one or more of polyimide, silicon oxide, and silicon nitride.
6. The capacitor according to claim 1 or 5, characterized in that, An adhesive layer is also provided between the second electrode layer and the insulating buffer layer.
7. The capacitor according to claim 1, characterized in that, The conductive metal layer filling the first through hole includes M7 layer and M8 layer stacked sequentially. The material of M7 layer includes Ti and the thickness is 50~100nm. The material of M8 layer includes Cu and / or Al. The diameter of the first through hole is 27~33μm, the hole spacing is 54~66μm, and the hole perpendicularity is 78~88°.
8. The capacitor according to claim 1, characterized in that, The conductive metal layer filling the second via comprises an M9 layer and an M layer stacked sequentially. 10 The M9 layer is made of Ti and has a thickness of 50-100 nm; the M... 10 The material of the layer includes Cu and / or Al; the diameter of the second through hole is 8~12μm, the hole spacing is 16~24μm, and the hole perpendicularity is 78~88°.
9. The capacitor according to claim 1, characterized in that, The substrate includes a glass substrate, a silicon substrate, or a gallium arsenide substrate.
10. The capacitor according to claim 9, characterized in that, The thickness of the substrate is 250~300μm.