Duplexer

Abstract

Duplexer (100) with: a transmit filter (112) coupled between a transmit port (62) and a common port (68); a receiving filter (113) coupled between a receiving port (61) and the common port (68); a phase matching circuit (132) which is coupled to the common terminal (68), the transmit terminal (62) and the receive terminal (61) to match the phases of the transmit filter (112) and the receive filter (113); a laminated part (128) on which the phase matching circuit (132) is mounted; a filter chip (110) or transmit and receive filter chips which is / are mounted on the laminated part (128), wherein the transmit filter (112) and the receive filter (113) are formed in the filter chip (110) or the transmit filter (112) and the receive filter (113) are formed in the transmit and receive filter chips respectively; wherein at least one of the transmitting port (62) and the receiving port (61) is provided in the laminated part (128) corresponding to at least one of the transmitting filter (112) and the receiving filter (113); a first U-shaped conductor pattern (51a, 52a) provided on a first layer (124) and coupled between at least one of the transmit filter (112) and the receive filter (113) and the at least one of the transmit terminal (62) and the receive terminal (61), which first layer (124) is contained in the laminated part (128) between the filter chip (110) or the transmit and receive filter chips and the at least one of the transmit terminal (62) and the receive terminal (61); a second U-shaped conductor pattern (51b, 52b) provided on a second layer (125) such that it overlaps the first U-shaped conductor pattern (51a, 52a) and is coupled between the first U-shaped conductor pattern (51a, 52a) and the at least one of the transmit terminal (62) and the receive terminal (61), which second layer (125) is contained in the laminated part (128) between the first layer (124) and the at least one of the transmit terminal (62) and the receive terminal (61); and a third U-shaped conductor pattern (51c, 52c) which is provided in one or more layers in the laminated part (128) between the second layer (125) and the at least one of the transmit terminal (62) and the receive terminal (61), coupled between the second U-shaped conductor pattern (51b, 52b) and the at least one of the transmit terminal (62) and the receive terminal (61) and with the same current direction as a current flowing through the second U-shaped conductor pattern (51b, 52b), wherein the first U-shaped conductor pattern (51a, 52a), the second U-shaped conductor pattern (51b, 52b) and the third U-shaped conductor pattern (51c, 52c) are designed such that they do not overlap an earthing terminal (63, 64, 65, 67, 69) in the laminated part (128).

Description

BACKGROUND OF THE INVENTION 1. Field of the invention

[0001] This invention relates generally to duplexers and in particular to a duplexer mounted on a laminated assembly or a laminated substrate. 2. Description of the related technology

[0002] In recent years, mobile devices and minicomputers or personal digital assistants have become widely used in the development of mobile communication systems. These mobile devices utilize high-frequency ranges between 800 MHz and 2.0 GHz. Accordingly, high-frequency filters and antenna duplexers designed for use with these filters have been proposed for mobile communication devices.

[0003] Elastic wave filters, for example, are used as high-frequency filters. Elastic wave filters include surface acoustic wave (SAW) filters, which are small, lightweight, and have an excellent form factor, and film-bulk acoustic resonator (FBAR) filters, which have excellent high-frequency characteristics and can be miniaturized. There are demands for higher performance, miniaturization, and cost reduction in high-frequency filters and duplexers. Accordingly, filters have been proposed in which a filter chip is mounted on the laminated assembly with a laminated part or the laminated substrate, and duplexers in which the filter is contained.

[0004] Publication JP2004336181A discloses a duplexer with a filter chip mounted on a laminated assembly or substrate with a laminated part, wherein a ceramic substrate and the like are laminated. Other conventional techniques exist for miniaturizing the duplexer. A phase-matching transmission line pattern is provided in two layers, as disclosed in JPH0818393A. Multiple phase-matching transmission line patterns are provided, as disclosed in JPH1075153A. Multiple phase-matching transmission line patterns are also provided around the entire chip, as disclosed in JP2001339273A. The phase-matching transmission line pattern is provided in multiple layers, as disclosed in JP2004336181A.

[0005] JPH0818393A describes a two-layer phase-matching line pattern. However, the phase-matching line pattern is only provided on the antenna terminal side, and there is no description of the phase-matching line provided at either the transmit or receive terminal. This is because the technique disclosed in JPH0818393A is used for the 800 MHz band duplexer, which is less affected by parasitic impedance of the assembly than the 2 GHz band duplexer. Therefore, a problem arises if filter tuning or matching in the 2 GHz band high-frequency duplexer is unsuccessful.

[0006] JPH1075153A describes the provision of multiple phase-matching line patterns. However, the phase-matching line, located on either the transmit or receive side, is not implemented in two layers. This creates a problem that cannot be resolved if the filter in the high-frequency duplexer, particularly in the 2 GHz band, is not matched.

[0007] JP2001339273A describes how the multiple phase-matching trace patterns are provided within the chip's perimeter. Consequently, the assembly size increases and cannot be reduced.

[0008] JP2004336181A describes that the power pattern for phase matching is provided in multiple layers. However, it does not describe the direction of the current flowing through the phase-matching conductor pattern. Consequently, problems arise because a large self-inductance cannot be generated in a small space, and the impedance matching cannot be improved by the capacitance between the signal line and ground.

[0009] Furthermore, it is known from DE10234737A1 that a branching section with a plurality of surface acoustic wave filters is provided on a first electrode structure on the front surface of a multilayer substrate. An antenna connection, a transmit connection, and a receive connection are provided on peripheral sections of a fourth electrode structure on the rear surface of the multilayer substrate and are connected to the branching section. A matching network, formed on a third electrode structure in an intermediate layer of the multilayer substrate and connected to the antenna connection, is provided such that it is grounded on at least one side that differs from the side opposite the side where the antenna connection is located.

[0010] US20030025572A1 discloses an antenna duplexer comprising a receive filter with a surface acoustic wave device, a transmit filter with a dielectric resonator, and a matching circuit for matching the receive filter and the transmit filter to each antenna, wherein the transmit filter, receive filter, and matching circuit are integrated together.

[0011] From EP0160972A2 a high-pressure discharge lamp is known with a hermetically sealed outer shell, a sodium-containing arc tube with a section of increased wall thickness arranged inside the shell, and a metal conductor located inside the outer shell and positioned immediately next to the section of increased wall thickness of the arc tube, thereby reducing the sodium loss from the arc tube.

[0012] DE10228328A1 discloses a highly integrated electronic component consisting of at least one chip component, in particular a filter operating with acoustic waves, and a multilayer substrate, wherein the multilayer substrate comprises integrated circuit elements for impedance transformation and further integrated circuit elements and serves as a substrate for chip components and discrete circuit elements arranged on its top surface. This component allows several signal processing functions to be implemented in a compact device, wherein, in particular, the impedance of a chip component arranged on the multilayer substrate is to be changed from one characteristic value to another predetermined value. SUMMARY OF THE INVENTION

[0013] The present invention was made in view of the above circumstances and provides a duplexer for which an inductor or capacitor can be easily used and whose size can be reduced.

[0014] Accordingly, the invention provides a duplexer according to claims 1, 3, 5 and 7. Advantageous further developments thereof are specified in the dependent claims.

[0015] According to the present invention, it is possible to create a duplexer with a small insertion loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Preferred embodiments of the present invention are described in detail with reference to the following drawings, wherein: Fig. 1 a dot diagram of a duplexer according to a first embodiment of the present invention; Fig. 2. Transmittance intensities (higher the closer to the top) with respect to frequencies of the transmit filter and the receive filter (higher the closer to the right side) are shown; Fig. 3 a cross-sectional view of a duplexer according to the first embodiment of the present invention; Fig. 4 a top view of the duplexer according to the first embodiment of the present invention, from which a cap has been removed; Fig. 5A to 5G each show layers in a laminated assembly of the duplexer according to the first embodiment of the present invention; Fig. 6A and Fig. 6B Current directions of U-shaped conductor patterns in the duplexer according to the first embodiment of the present invention are shown; Fig. 7A to Fig. 7D each shows layers in the laminated assembly of the duplexer of a comparative example 1; Fig. 8A to Fig. 8C are graphical representations that depict the characteristics of a transmitting filter used in the first embodiment and in a comparative example 1; Fig. Figures 9A to 9D show variations of the U-shaped conduit pattern; Fig. 10A and Fig. 10B shows other variations of the U-shaped conduit pattern; Fig. 11A to Fig. 11D show the layers in the laminated assembly of the duplexer according to a second embodiment of the present invention; Fig. 12A to Fig. 12B show the layers in the laminated assembly of the duplexer according to a third embodiment of the present invention; Fig. 13A to Fig. 13D show the layers in the laminated assembly of the duplexer according to a fourth embodiment of the present invention; Fig. 14A to Fig. 14D each show the layers in the laminated assembly of a comparison example 2; Fig. Figures 15A to 15C are graphical representations showing the characteristics of a receiving filter used in the fourth embodiment and comparative example 2; Fig. 16A to Fig. 16D each show the layers in the laminated assembly of the duplexer according to a fifth embodiment of the present invention; Fig. 17A to Fig. 17D each show the layers in the laminated assembly of the duplexer according to a sixth embodiment of the present invention; and Fig. 18 is a block diagram of an electronic device according to a seventh embodiment of the present invention. DESCRIPTION OF PREFERRED EXECUTION FORMS

[0017] With reference to the accompanying drawings, a description of the embodiments of the present invention is now provided. Embodiments 1 to 6 describe exemplary examples of a filter and a duplexer incorporating the filter. A receive port and a transmit port of the duplexer correspond to an output port and an input port, respectively, of the filter. An input / output port designates a port that serves as either an input port or an output port. [First embodiment]

[0018] A first embodiment of the present invention uses a filter mounted on a laminated assembly and a duplexer incorporating the aforementioned filter. An inductor is connected in series with the receive terminal (output terminal) and the transmit terminal (input terminal) and an input / output contact point (not shown) of a filter chip. Fig. Figure 1 is a block diagram of the duplexer. Fig. Figure 2 shows pass-through intensities (higher the closer to the top) with respect to frequencies of the transmit filter and the receive filter (higher the closer to the right side). Fig. Figure 3 is a cross-sectional view of the duplexer according to the first embodiment. Fig. Figure 4 is a top view of the duplexer according to the first embodiment. Fig. Figure 4 is a top view from which a cap is 129 away.

[0019] Referring now to Fig. 1. A transmit signal is fed in from a transmit terminal 62. The signal, with a desired frequency, passes through a transmit filter 112 and a matching circuit 132 and is output from a common terminal 68. A received signal is fed in from the common terminal 68 and passes through the matching circuit 132. The signal, with a desired frequency, passes through a receive filter 113 and is output from a receive terminal 61. The common terminal 68 is provided for use with an external circuit that transmits and receives electrical waves via an antenna. A transmit terminal (input terminal) 62 is provided for connecting an external transmit circuit to feed in a signal with a desired center frequency. The receive terminal (output terminal) 62 is provided for connecting an external receive circuit to output a signal with a desired center frequency.

[0020] After Fig. 2. The transmit filter 112 and the receive filter 113 have center frequencies F1 and F2, respectively, with different passbands. F2 is higher than F1. For example, there is a 100 MHz difference in frequency between F1 and F2 on the duplexer with a range of 1.9 GHz.

[0021] After Fig. 3 contains a duplexer 100, a laminated assembly 120, a filter chip 110, and a chip 132 for a phase-matching circuit. The filter chip 110 contains the transmit filter 112 and the receive filter 113.

[0022] After Fig. 4. The filter chip 110 consists of the transmit filter 112 and the receive filter 113. The transmit filter 112 is, for example, a conductor-type SAW filter in which SAW resonators are connected to a port in a conductor. The receive filter 113 is, for example, a dual-mode SAW filter.

[0023] The Filterchip 110 is manufactured as follows. A piezoelectric crystal, such as LiTaO3 (e.g., 42 degrees, Y-cut, X-spreading), is used as the substrate. A metal alloy with a main component of aluminum, such as Al-Cu or Al-Mg, and a multilayer film containing aluminum, such as Al-Cu / Cu / Al-Cu, Al / Cu / Al, Al / Mg / Al, or Al-Mg / Mg / Al-Mg, are formed by sputtering. A specific pattern is created using the standard exposure and etching processes. The Filterchip 110 is then completed.

[0024] The chip 132 for the phase-matching circuit is a chip on which a phase-matching circuit is provided. The phase-matching circuit is designed such that the transmit filter 112 and the receive filters 113 do not degrade their respective filter characteristics. A characteristic impedance Z1 is the characteristic impedance when the transmit filter 112 is viewed from the common terminal 68. A characteristic impedance Z2 is the characteristic impedance when the receive filter 113 is viewed from the common terminal 68. If the frequency of the signal fed in from the common terminal 68 is tuned to F1 by the action of the phase-matching circuit 132, the characteristic impedance Z1 of the transmit filter 112 corresponds to a characteristic impedance of the common terminal 68, the characteristic impedance of the receive filter 113 is infinite, and its reflection coefficient is 1.If the frequency of the signal fed in from the common terminal 68 is tuned to F2, the characteristic impedance of the transmit filter 112 is infinite, its reflection coefficient is 1, and the characteristic impedance Z2 of the receive filter 113 corresponds to the characteristic impedance of the common terminal 68.

[0025] After Fig. Figure 3 contains the laminated assembly 120, comprising six laminated layers 121 to 126, which include a cap mounting layer 121, a cavity layer 122, a semiconductor wafer mounting layer 123, a first conduction pattern layer 124, a second conduction pattern layer 125, and a conduction pattern / foot contact layer 126. The cap mounting layer 121 and the cavity layer 122 form a cavity-forming layer 127. The semiconductor wafer mounting layer 123, the first conduction pattern layer 124, the second conduction pattern layer 125, and the conduction pattern / foot contact layer 126 form a base layer (laminated part) 128. The layers 121 to 126 described above consist of aluminum oxide ceramic or glass ceramic with a relative permittivity of approximately 8–9.5.

[0026] Cap 129 is mounted on layer 121 to seal a cavity in layer 127, which forms a cavity. Filter chip 110 and phase-matching chip 132 are bonded to layer 123 with contact protrusions 130 for mounting semiconductor wafers with the active side facing down. Foot contacts 131 are provided on the underside of the conductor pattern / foot contact layer 126. The foot contacts 131 serve to connect to external components such as an input / output terminal, a connection terminal, or a ground terminal. Connecting channels (side casterations, namely grooves) 133 are provided at the corners of the respective layers 121 to 126.A sealing ring grounding of layer 121 for mounting a cap is connected to the foot contact point 131, which serves as a grounding connection, on the underside of the conductor pattern / contact point layer 126, via the connecting channels 133. The external dimensions of the laminated assembly 120 are, for example, 3 mm x 3.1 mm.

[0027] Fig. Figures 5A to 5G show the respective layers of the laminated assembly 120 according to the first embodiment of the present invention. Fig. 5A is a top view of layer 121 for the assembly of a cap. Fig. 5B is a top view of cavity layer 122. Fig. 5C is a top view of layer 123 for the attachment of semiconductor wafers. Fig. 5D is a top view of the first conductor pattern layer 124. Fig. 5E is a top view of a second performance pattern layer 125. Fig. 5F is a top view of the upper side of the conductor pattern / foot contact layer 126. Fig. 5G is a top view of the underside of the conductor pattern / foot contact layer 126. In this context, vias shown in the figures described above denote bores, holes or receiving protrusions thereof in the layers.

[0028] Back on Fig. Referring to 5A, the cap 129 is mounted on a top surface of layer 121 for mounting a cap. Except for the perimeter, layer 121 is open for mounting a cap and a cavity is formed. Referring to Fig. 5B, with the exception of the perimeter, the cavity layer 122 is opened and the cavity is formed.

[0029] Referring now to Fig. 5C has layer 123 for mounting semiconductor wafers vias 23, 24, 25, 26, 27, 28 and 29 which are connected to the conduction pattern / foot contact layer 126, and also has vias 21a, 22b and 28a which are connected to the first conduction pattern layer 124. The vias 21a, 22a, 23, 24, 25, 26, 27, 28, 28a and 29 are connected to a conductor pattern for a receive 31, a conductor pattern for a transmit 32, a grounding pattern for the receive filter 33, a grounding pattern for the receive filter 34, a grounding pattern for the transmit filter 35, a grounding pattern for the transmit filter 36, a grounding pattern for the phase matching circuit 37, a conductor pattern for the common terminal 38, a conductor pattern for connecting the transmit filter and a common terminal 41, and a grounding pattern for the phase matching circuit 39.Furthermore, a pattern 40 is provided to connect the receiving filter and the phase-matching circuit. In each of the patterns described above, square sections serve as the contact points for forming the contact protrusions 130, which connect the filter chip 110 or the chip 132 of the phase-matching circuit.

[0030] Referring to Fig. In 5D, the first conduction pattern layer 124 also includes vias 23, 24, 25, 26, 27, 28, and 29, which connect layer 123 for semiconductor substrate placement through the conduction pattern / foot contact layer 126. A first U-shaped receive conduction pattern 51a is provided between via 21a, which connects layer 123 for semiconductor substrate placement, and via 21b, which connects the second conduction pattern 125. A first U-shaped transmit conduction pattern 52a is provided between via 22a, which connects layer 123 for semiconductor substrate placement, and via 22b, which connects the second conduction pattern 125. A conductor pattern 58 for connecting the transmit filter and the common terminal is provided between the via 28a, which connects layer 123 for mounting semiconductor chips, and the via 28.

[0031] Referring to Fig. In 5E, the second conduction pattern layer 125 also features vias 23, 24, 25, 26, 27, 28, and 29, which connect layer 123 to the conduction pattern / foot contact layer 126 for the attachment of semiconductor wafers. A second U-shaped conduction pattern 51b for receiving is provided between via 21b, which connects the first conduction pattern layer 124, and via 21c, which connects the conduction pattern / foot contact layer 126. A second U-shaped conduction pattern 52b for transmitting is provided between via 22b, which connects the first conduction pattern 124, and via 22c, which connects the conduction pattern / foot contact layer 126.

[0032] Referring to Fig. 5F also has the top surface of the conduction pattern / foot contact layer 126 the vias 23, 24, 25, 26, 27, 28 and 29 which connect the layer 123 for the attachment of semiconductor wafers through the conduction pattern / foot contact layer 126, and has the vias 21c and 22c which connect the second conduction pattern layer 125.

[0033] Referring to Fig. 5G uses the underside of the conductor pattern / foot contact layer 126, foot contacts 61 to 69. Foot contact 61 serves as the receive (output) terminal 61, which is connected to via 21c. Foot contact 62 serves as the transmit (input) terminal 62, which is connected to via 22c. Foot contacts 63, 64, 65, 67, and 69 serve as the ground terminals 63, 64, 65, 67, and 69, respectively, which are connected to vias 23, 24, 25, 26, 27, and 29, respectively. Foot contact 68 serves as the common terminal 68, which is connected to via 28.

[0034] The filter and duplexer 100 used in the first embodiment comprises the filter chip 110 and the base layer (laminated part) 128, on which the filter chip 110 is mounted. The filter chip 110 contains the transmit filter 112 and the receive filter 113 with different frequency ranges. Furthermore, the filter and duplexer 100 used in the first embodiment includes the receive port (output port) 61 and the transmit port (input port) 62, which are provided on the base layer (laminated part) 128, and also includes the first U-shaped conductor patterns 51a and 52a, which are each coupled to the filter 110 and are formed on the first conductor pattern layer (a first layer) 124 of the base layer (laminated part) 128, arranged between the first conductor pattern layer (first layer) 124 and the receive port (output port) 61 and the transmit port (input port) 62.The filter and duplexer 100 further comprises second U-shaped patterns 51b and 52b, which are formed on the second line pattern layer (second layer) 125 of the base layer (laminated part) 128, arranged between the first line pattern layer (first layer) 124 and the receive port (output port) 61 and the transmit port (input port) 62, such that the second U-shaped patterns 51b and 52b substantially overlap the first U-shaped line patterns 51a and 52a, respectively. The second U-shaped patterns 51b and 52b are coupled to the first U-shaped line patterns 51a and 52a, respectively, and to the receive port (output port) 61 and the transmit port (input port) 62.

[0035] The duplexer 10 according to the first embodiment further comprises the transmit filter 112, which is coupled to the transmit port 62, the receive filter 113, which is coupled to the receive port 61, the common port 68, the phase matching circuit 132, which is coupled to the transmit filter 112 and the receive filter 113 to match the phases of the transmit filter 112 and the receive filter 113, and the laminated part 128 on which the phase matching circuit 132 is mounted.

[0036] The phase-matching circuit 132 is mounted on the base layer (laminated part) 128, which carries the transmit filter 112 and the receive filter 113. That is, the base layer (laminated part) 128 with the phase-matching circuit 132 mounted on it serves as the base layer (laminated part) 128 for both the transmit filter 112 and the receive filter 113.

[0037] In the filter and duplexer used in the first embodiment as described above, an inductor formed by the first U-shaped conductor pattern 51a and the second U-shaped conductor pattern 51b is connected in series with the receive terminal (output terminal) 61 and an output contact point of the filter chip 110. Furthermore, the inductor formed by the first U-shaped conductor pattern 52a and the second U-shaped conductor pattern 52b is connected in series with the transmit terminal (input terminal) 62 and an input contact point of the filter chip 110. The first U-shaped conductor patterns 51a and 52a are configured such that they substantially overlap the second U-shaped conductor patterns 51b and 52b, respectively.

[0038] Essentially overlapping the U-shaped conductor patterns means that the conductor patterns provided on the different layers (e.g., on the first conductor pattern layer 124 and on the second conductor pattern layer 125) of the base layer (laminated part) 128 are arranged in nearly the same positions. This creates a higher inductance than the conductor patterns that are not overlapped. Accordingly, in the inductor connected in series with the receive terminal (output terminal) 61 and the transmit terminal (input terminal) 62, a large inductance of up to 1 nH to 4 nH is available even in an extremely small space. In this way, it is possible to easily use the inductor in impedance matching and to miniaturize the laminated assembly 120, thus enabling a smaller filter or duplexer.

[0039] Fig. Figure 6A shows the first conductor pattern layer 124 used in the first embodiment. Fig. Figure 6B shows the second conductor pattern layer 125 used in the first embodiment. Reference numerals, which are in Fig. 6A and Fig. The ones shown in 6B are the same as those shown in Fig. 5C and Fig. Figure 5E is shown. The directions of the dashed lines indicate the directions of current flow. Current flowing through the first U-shaped conductor patterns 51a and 52a has essentially the same direction as current flowing through the second U-shaped conductor patterns 51b and 52b. In this way, the self-inductance of the conductor pattern is significantly increased, for example, by ensuring that the current flows have essentially the same direction. Consequently, a large inductance can be achieved in a small space, which further reduces the size of the filter and the duplexer.

[0040] Next, a description of a comparative example 1 is provided for comparison with the first embodiment. Fig. 7A to Fig. Figure 7D shows the respective layers of the laminated assembly 120 of comparison example 1. The layers that are in Fig. 7A to Fig. Those not shown in 7D have the same configuration as those shown in Fig. 5A to Fig. 5G are shown. In the Fig. The layer shown in 7A for the attachment of semiconductor wafers corresponds to a via 21 of the in Fig. 5C shows the via 21a, and a via 22 corresponds to the one shown in Fig. 5C shows the via 22a. The other components and configurations, such as those shown in Fig. The reference numbers shown in 7A have the same reference numbers as in Fig. 5C shown.

[0041] Referring to Fig. 7B provides vias 21 and 22 on the first conductor pattern layer 124. Via 21 connects layer 123 for the attachment of semiconductor chips through the conductor pattern / foot contact layer 126. Via 22 connects the first conductor pattern layer 124 through the second conductor pattern layer 125. Conductor pattern 58 for connecting the transmit filter and the common terminal is also provided.

[0042] Referring to Fig. 7C has a via 29a on the second conductor pattern layer 125 and is connected to the conductor pattern / foot contact layer 126, and a linearly arranged conductor pattern 59a for transmitting is also provided between the via 29a and the via 22. The via 22, which is in Fig. As shown in 7C, this is a receiving elevation instead of a bore or hole on the second line pattern layer 125.

[0043] Referring now to Fig. 7D, a linearly arranged pattern 59b is provided for transmitting between the via 29a and the via 22 on the top side of the conductor pattern / foot contact layer 126. The in Fig. The via 29a shown in 7D is a receive ridge rather than a hole or bore on the trace / foot contact layer 126. Current flows through traces 59a and 59b to the respective transmit points, as indicated by the arrows.

[0044] As described in Comparative Example 1, instead of the U-shaped conductor patterns 52a and 52b, the linearly arranged conductor patterns 59a and 59b are positioned to serve as the inductors. The evaluations described below were performed on the transmit filter 112. The inductor used in Comparative Example 1 is only intended for the transmit connection 62. In Comparative Example 1, the conductor patterns are longer to achieve the same inductance as the first embodiment. This increases capacitive components with the ground.

[0045] Fig. 8A to Fig. 8C shows evaluation results. Fig. 8A to Fig. Figure 8C are graphical representations showing the characteristics or curves of the transmitting filter 112 used in the first embodiment and the one used in comparative example 1. The in Fig. The reflection characteristics shown in Figure 8A indicate that the transmit region in Comparative Example 1 is shifted from the center, and there is a capacitive characteristic around the tip of an arrow in Comparative Example 1. That is, there is a large capacitive component associated with grounding. In contrast, the transmit region in the first embodiment is closer to the center by the tip of an arrow in the first embodiment. That is, there is a small capacitive component associated with grounding. Fig. Figure 8B shows the frequency and insertion loss. Fig. Figure 8C is an enlarged view around the passband. The transmit filter 112 used in the first embodiment has a lower insertion loss than the one used in Comparative Example 1. Fig. Figure 8B also shows that there is no deterioration in the suppression in the frequency domain except for the passband in the transmit filter 112 used in the first embodiment, in contrast to the transmit filter 112 used in Comparative Example 1. In this way, according to the first embodiment, the inductance with a small capacitive component can be applied to the transmit terminal (input terminal) or the receive terminal (output terminal), making it possible to create the filter in which the insertion loss is small.

[0046] The U-shaped conductor patterns 51a, 52a, 51b, and 52b are configured to have the shape of a half-loop, and the first U-shaped conductor pattern and the second U-shaped conductor pattern, intended for transmitting and receiving respectively, can substantially overlap. Other examples of their shape are shown in Fig. 9A to Fig. 10B is shown. Fig. 9A to Fig. Via 90 connects layer 123 for the placement of semiconductor wafers and the first conduction pattern 124. Vias 91 and 92 connect the first conduction pattern 124 and the second conduction pattern 125. A via 93 connects the second conduction pattern layer 125 and the conduction pattern / foot contact layer 125. A first conduction pattern 95 is formed between via 90 and via 91. A second conduction pattern 96 is formed between via 92 and via 93. Vias 92 and 93 are connected vias. The current direction is indicated by an arrow in each figure.

[0047] Fig. Figure 9A shows an example of the shape of a half loop formed from a square, in which the corners are rounded. Fig. Figure 9B shows an example of the shape of a half loop formed from a polygon. Fig. Figure 9C shows an example of the shape of a half-loop formed from a circle. Fig. Figure 9D shows an example of the shape of a half-loop formed from a triangle. Fig. Figure 10A shows an example of the shape of a half loop formed from a polygon having interior angles of less than 180 degrees and exterior angles of more than 180 degrees. Fig. Figure 10B shows an example of a half-loop shape formed from an oval. As described, the U-shaped wiring pattern only needs to have a half-loop shape.

[0048] As described above, according to the first embodiment, the first U-shaped conductor pattern 51a and the second U-shaped conductor pattern 52b are arranged such that they substantially overlap and have the same direction of current flow. This allows for a greater self-inductance of the conductor pattern, thereby reducing the size of the laminated portion and resulting in a smaller filter and duplexer. It is also possible to create the filter and duplexer with a small insertion loss, to which the capacitive component is difficult to apply. [Second embodiment]

[0049] A second embodiment of the present invention uses the U-shaped conductor pattern provided in three or more layers, and the inductor is connected in series between the receive terminal (output terminal) and transmit terminal (input terminal) and the (not shown) input / output contact point of the filter chip 110. Fig. Figures 11A to 11D show the respective layers of the laminated assembly 120 used in the second embodiment. Fig. 11A to Fig. Layers 11D that are not shown have the same configuration as corresponding layers shown in Fig. 5A to 5G are shown. The ones in Fig. 11A shows layer 123 for attaching semiconductor wafers which are in Fig. 11B shows the first conductor pattern layer 124 and the one in Fig. The second conductor pattern layer 125 shown in 11C is the same as those shown in Fig. 5A to Fig. Figure 5G shows the components used in the first embodiment. Vias 21d and 22d are provided on the top surface of the conductor pattern / foot contact layer 126. The vias 21d and 22d are connected to the bottom surface of the conductor pattern / foot contact layer 126. Third U-shaped conductor patterns 51c and 52c are formed between the via 21c and the via 21d, and between the via 22c and the via 22d, respectively.

[0050] According to the second embodiment, the third U-shaped conductor patterns 51a and 52c are provided in one or more layers of the base layer (laminated part) 128 between the first conductor pattern layer (first layer) 125 and the receive terminal (output terminal) 61 and the transmit terminal (input terminal) 62, in such a way that the current flowing through the third U-shaped conductor pattern 51c has essentially the same direction as the current flowing through the first U-shaped conductor pattern 51a and the second U-shaped conductor pattern 51b, and the third U-shaped conductor pattern 52c has essentially the same direction as the current flowing through the first U-shaped conductor pattern 52a and the second U-shaped conductor pattern 52b.In this way, an additional U-shaped conductor pattern, designed to overlap the existing U-shaped conductor patterns, increases the inductance of the inductor connected in series with the receive (output) terminal 61, the transmit (input) terminal 62, and the (not shown) input / output contact of the filter chip 110. Even if a high impedance is required for impedance matching, the laminated section can be reduced accordingly, thereby miniaturizing the filter and duplexer, just as in the first embodiment. It is also possible to create the filter and duplexer with minimal capacitive component and low insertion loss. Furthermore, the inductor with higher inductance can be created by laminating the layers with the U-shaped conductor patterns.

[0051] In the first and second embodiments, it is possible to configure the first U-shaped conductor patterns 51a and 52a, the second U-shaped conductor patterns 51b and 52b, or the third U-shaped conductor patterns 51c and 52c such that they substantially overlap the receive terminal (output terminal) 61 or the transmit terminal (input terminal) 62. This can reduce the capacitance to be applied between the U-shaped conductor patterns and ground, thus reducing the insertion loss.

[0052] Furthermore, it is possible to design the first U-shaped conductor patterns 51a and 52a, the second U-shaped conductor patterns 51b and 52b, or the third U-shaped conductor patterns 51c and 52c such that they do not overlap the grounding connections in the base layer (laminated part) 128. This can reduce the capacitance to be applied between the U-shaped conductor patterns and the ground, thus reducing the insertion loss.

[0053] Furthermore, it is possible to configure the first U-shaped conductor patterns 51a and 52a, the second U-shaped conductor patterns 51b and 52b, or the third U-shaped conductor patterns 51c and 52c such that they each have a distance between the conductors that is greater than the conductor width. Here, the distance between the conductors refers to the distance between the conductors in the U-shaped conductor pattern, and the conductor width refers to the width of a conductor. If the distance between the conductors is less than the conductor width, the currents flowing in opposite directions across opposite corners cancel each other out, and the inductance cannot be increased. Accordingly, the inductance of the U-shaped conductor pattern can be increased by making the distance between the conductors greater than the conductor width, thereby reducing the sizes of the filter and the duplexer.

[0054] In the first and second embodiments, the inductor is connected to the receive terminal (output terminal) and the transmit terminal (input terminal), respectively. The inductor can be connected to either the receive terminal (output terminal) or the transmit terminal (input terminal), depending on the need to apply the inductor and match the impedance. [Third embodiment]

[0055] A third embodiment of the present invention uses, by way of example, the inductor which is connected in series with the grounding terminal and a (not shown) grounding contact point of the filter chip 110. The layers that are in Fig. 12A to Fig. Those not shown in 12D have the same configuration as those shown in Fig. 5A to Fig. 5G are shown, which are used in the first embodiment. The via 21 corresponds to the one in Fig. The via 21a shown in 5C corresponds to the via 22 shown in Fig. 5C shows the via 22a, and a via 23a corresponds to the one shown in Fig. 5C shown via 23. The other components and configurations such as those shown in Fig. The reference numbers shown in 12A have the same reference numbers as in Fig. 5C shown.

[0056] Referring to Fig. 12B a first U-shaped grounding pattern 53a is provided on the first conduction pattern layer 124, which is formed between the via 23a connected to layer 123 for the attachment of semiconductor plates and the via 23b connected to the second conduction pattern layer 125.

[0057] Referring to Fig. 12C provides a second U-shaped grounding pattern 53b on the second conductor pattern layer 125 between the via 23b, which is connected to the first conductor pattern layer 124, and the via 23c, which is connected to the top of the conductor pattern / foot contact layer 126. Referring to Fig. 12D is provided on the top side of the conductor pattern / foot contact layer 126 as a grounding pattern 53c for receiving a filter between the via 23c, which is connected to the second conductor pattern layer 125, and the via 23d, which is connected to the bottom side of the conductor pattern / foot contact layer 126.

[0058] The filter and duplexer 100 used in the third embodiment of the present invention comprises the filter chip 110, the base layer (laminated part) 128 on which the filter chip 110 is mounted, and the grounding terminal 63 provided on the base layer (laminated part) 128. The filter and duplexer 100 used in the third embodiment of the present invention further comprises the first U-shaped grounding pattern 53a, which is provided on the first conductor pattern (first layer) 124 in the base layer (laminated section) 128 between the filter chip 110 and the grounding terminal 63, and which is coupled to the filter chip 110.Furthermore, the filter and duplexer 100 used in the third embodiment of the present invention also includes the second U-shaped grounding pattern 53b, which is provided on the second conductor pattern layer (second layer) 125 in the base layer (laminated part) 128 between the first conductor pattern layer (first layer) 124 and the grounding terminal 63 such that it substantially overlaps the first U-shaped grounding pattern 53a, and which is coupled to the first U-shaped grounding pattern 53a and the grounding terminal 63.Furthermore, the filter and duplexer 100 used in the third embodiment of the present invention comprises the linearly arranged grounding pattern 53c, which is provided such that it substantially overlaps a section of the first U-shaped grounding pattern 53a and a section of the second U-shaped grounding pattern 53b on the top side of the conductor pattern / foot contact layer 126 in the base layer (laminated part) 128 between the first conductor pattern (first layer) 124 and the grounding terminal 63.

[0059] The filter and duplexer used in the third embodiment of the present invention has the configuration mentioned above and is configured such that the inductor, consisting of the first U-shaped grounding pattern 35a, the second U-shaped grounding pattern 53b, and the linearly arranged grounding pattern 53c, is connected in series with the grounding terminal 63 and the grounding contact point of the filter chip 110, and the first U-shaped grounding pattern 53a, the second U-shaped grounding pattern 53b, and the linearly arranged grounding pattern 53c are substantially overlapped. Accordingly, a large inductance is available in the inductor connected in series with the grounding terminal 63 and the filter chip 110, even in a very small space. This allows the laminated assembly 120 to be miniaturized. This is particularly advantageous in a mobile phone system where the transmit and receive ranges differ, such as...It is preferable to W-CDMA to provide a large self-inductance on the ground to reduce suppression in the lower frequency range of the passband. Therefore, the filter and duplexer can be miniaturized by using the filter and duplexer employed in the third embodiment for the system described above.

[0060] As described in the first embodiment, it is possible to ensure that the current flowing through the first U-shaped grounding pattern 53a, the current flowing through the second U-shaped grounding pattern 53b, and the current flowing through the linearly arranged grounding pattern 53c have essentially the same direction. This can increase the self-inductance, thereby further miniaturizing the filter and the duplexer.

[0061] As described in the second embodiment, it is possible to provide a third U-shaped grounding pattern on one or more layers in the base layer (laminated part) 128 between the second conductor pattern layer (second layer) 124 and the grounding terminal 63, for example, on the top side of the conductor pattern / foot contact layer 126. The third U-shaped grounding pattern is coupled to the second U-shaped grounding pattern 53b and the grounding terminal 63 to have essentially the same current direction as the current flowing through the second U-shaped grounding pattern 53b. This makes it possible to further miniaturize the filter and the duplexer. It is also possible to form the inductor with a higher inductance by laminating a layer with a U-shaped grounding pattern.

[0062] Furthermore, it is also possible to provide the first U-shaped grounding pattern 53a, the second U-shaped grounding pattern 53b, or a third U-shaped grounding pattern such that they do not overlap an inductive pattern in the base layer (laminated part) 128. The inductive pattern is, for example, a pattern connected to the receive terminal (output terminal) 61, the transmit terminal (input terminal) 62, or the common terminal 68. Specifically, the first U-shaped conductor pattern, the second U-shaped conductor pattern, and the third U-shaped conductor pattern are provided. In a fifth and sixth embodiment, input / output patterns 50 and 51g are also the inductive patterns. In this way, it is possible to reduce the capacitance applied between the receive terminal (output terminal) 61 or the transmit terminal (input terminal) 62 and ground, thereby reducing the insertion loss.

[0063] In the third embodiment, the inductor is coupled to the grounding terminal of the receiver (output terminal). However, it is also possible to couple the inductor to the grounding terminal of the transmitter (input terminal) if required. Furthermore, it is possible to couple the inductors to both grounding terminals of the receiver (output terminal) and the transmitter (input terminal). [Fourth embodiment]

[0064] A fourth embodiment of the present invention uses a capacitor connected between the grounding terminal 62 and the receiving terminal (output terminal) 61. Fig. 13A to Fig. Figure 13D shows the respective layers of the laminated assembly 120 according to the fourth embodiment of the present invention. The layers, which are in Fig. 13A to Fig. Those not shown in 13D have the same configuration as those shown in Fig. 5A to Fig. 5G are shown. In the Fig. The layer shown in 13A for the attachment of semiconductor wafers corresponds to the via 21 of the one shown in Fig. 5C shows the via 21a, and the via 22 corresponds to the one in Fig. 5C shows the via 22a. The other components and configurations, such as those shown in Fig. The reference numbers shown in 13A have the same reference numbers as in Fig. 5C shown, which is described in the first embodiment.

[0065] Referring to Fig. 13B provides a first grounding pattern 53d on the first conductor pattern layer 124 and is connected to the via 23, which is coupled to the first grounding terminal 63. Referring to Fig. 13C is provided with an input / output pattern 51e and is connected to the via 21, which is coupled to the receive (output) terminal 61. Referring to Fig. 13D provides a second grounding pattern 53e and is connected to the via 23, which is coupled to the grounding terminal 63.

[0066] The filter and duplexer 100 used in the fourth embodiment comprises the filter chip 110, the base layer (laminated part) 128 on which the filter chip 110 is mounted, and the grounding terminal 63, which is provided on the base layer (laminated part) 128. The filter and duplexer 100 used in the fourth embodiment also comprises the first grounding pattern 53d, which is coupled to the filter chip 110 and provided on the first conductor pattern layer (first layer) 124 of the base layer (laminated part) 128 between the filter chip and the grounding terminal 163. The filter and duplexer 100 used in the fourth embodiment further comprises the second grounding pattern 53e and the input / output pattern 51e. The second earthing pattern 53e is provided on a third layer in the base layer (laminated part) 128 between the first conductor pattern layer (first layer) 124 and the earthing terminal 63 such that it overlaps with the first earthing pattern 53d.The input / output pattern 51e is provided on the second layer 125 between the first layer 124 and the third layer 126 in the laminated part 128 such that it overlaps the second grounding pattern 53e and is coupled to the filter chip 110 and the receive port (output port) 61.

[0067] Overlapping the grounding pattern or the input / output pattern means that the patterns provided on different layers of the base layer (laminated part) 128, e.g., on the first line pattern layer 124 and the second line pattern layer 125, are located at nearly the same positions. This creates capacitors between the first grounding pattern 53d and the input / output pattern 51d and between the input / output pattern 51e and the second grounding pattern 53e. In other words, capacitors are coupled between the grounding terminal and the receive terminal (output terminal) 61. Accordingly, it is possible to connect a large capacitor in a small space of the filter and duplexer according to the fourth embodiment of the present invention. This allows the laminated section to be reduced in size, thereby miniaturizing the filter and duplexer.

[0068] Now, a comparative example 2 is described to compare it with the duplexer used in the fourth embodiment. The duplexer of comparative example 2 does not contain a capacitor between the ground terminal and the receive terminal (output terminal) 61. Fig. 14A to Fig. Figure 14D shows the respective layers of the laminated assembly 120 of comparison example 2. The layers that are in Fig. 14A to Fig. Those not shown in 14D have the same configuration as those shown in Fig. 5A to Fig. 5G are shown. The first grounding pattern 53d is not on the first line pattern layer 124 in Fig. 14D is provided. The input / output pattern 51e is not on the second line pattern 125 in Fig. 14C is provided. The second earthing pattern 53e is not on the top side of the conductor pattern / foot contact layer 126 in Fig. 14D is provided. In comparative example 2, the other components and configurations have the same reference numbers as in Fig. 13A to Fig. 13D representations, which are described in the fourth embodiment.

[0069] Fig. 15A to Fig. Figure 15C are graphical representations illustrating the characteristics of the receiving filter 113, which is used in the fourth embodiment and in comparative example 2. Fig. 15A shows a reflection characteristic. Fig. 15B shows frequency and insertion loss. Fig. Figure 15C is a magnified view around the passage area. Regarding comparison example 2, it shows... Fig. 15A shows that the lower frequency of the passband lies to the upper left of the center (around the tip of an arrow in Comparative Example 2) and has an inductive characteristic. On the other hand, regarding the fourth embodiment, Fig. 15A, that the lower frequency of the passband is closer to the center (by one tip of an arrow in the fourth embodiment) and moves from an inductive characteristic to a capacitive characteristic, which improves the impedance matching. Consequently, as in Fig. As shown in Figure 15C, the insertion loss in the lower frequency of the passband is improved in the fourth embodiment. Fig. Figure 15B shows that there is no deterioration in frequency-domain suppression, except in the passband, in the fourth embodiment compared to Comparative Example 2. As previously described, according to the fourth embodiment, a capacitor can be coupled between the receive terminal (output terminal) or the transmit terminal (input terminal) and the ground terminal. This facilitates impedance matching. It is also possible to provide a filter with a low insertion loss.

[0070] The second grounding pattern 53e can also serve as the grounding connection 63. This eliminates a layer, thereby allowing the filter and duplexer to be made smaller and cheaper.

[0071] The first grounding pattern 53d or the second grounding pattern 53e can be provided so that it overlaps the receive (output) terminal 61 or the transmit (input) terminal 62 in the laminated part 128. This makes it possible to reduce the capacitance applied between the grounding terminal and the receive (output) terminal 61 or the transmit (input) terminal 62, thereby reducing the insertion loss.

[0072] Furthermore, the input / output pattern 51e can have a smaller area than the area of ​​the first grounding pattern 53 and / or the second grounding pattern 53e. This allows the input / output pattern 51e to be safely positioned between the first grounding pattern 53d and the second grounding pattern 53e, even if the layers are misaligned in the manufacturing process of the base layer (laminated part) 128. This makes it possible to reduce the variation in production capacity. [Fifth embodiment]

[0073] A fifth embodiment of the present invention uses an inductor connected in series with the receive terminal (output terminal) 61 and the output contact point of the filter chip 110, and a capacitor coupled between the ground terminal 63 and the receive terminal (output terminal) 61. Fig. 16A to Fig. Figure 16D shows the respective layers of the laminated assembly 120 used in the fifth embodiment of the present invention. The layers, which are in Fig. 16A to Fig. Those not shown in 16D have the same configuration as those shown in Fig. 5A to Fig. 5G are shown, which were used in the first embodiment. In the Fig. In the layer 123 shown in Figure 16A for the attachment of semiconductor wafers, a via 21f corresponds to the via 21a in Fig. 5C, and the via 22 corresponds to the via 22a in Fig. 5C. The other components and configurations, such as those in Fig. The reference numbers shown in 16A have the same reference numbers as in Fig. 5C shown.

[0074] Referring to Fig. On the first conduction pattern layer 24, 16B provides the first grounding pattern 53d and connects to the via 23, which is coupled to the grounding terminal 63. The via 21f is provided to connect layer 123 to the second conduction pattern layer 125 for the attachment of semiconductor wafers.

[0075] Referring to Fig. 16C provides a first U-shaped conductor pattern 51f on the second conductor pattern layer 125 for receiving, to connect the via 21f and a via 21g. The via 21f is coupled to the semiconductor plate mounting layer 123, and the via 21g is coupled to the conductor pattern / foot contact layer 126. An input / output pattern 51g is also provided and connected to the first U-shaped conductor pattern 51f. Referring to Fig. 16D is a second U-shaped conductor pattern 51x for receiving between via 21g and via 21h. Via 21g is coupled to the second conductor pattern layer 125. Via 21h is coupled to the receive terminal (output terminal) 61 on the underside of the conductor pattern / foot contact layer 126. The second grounding pattern 53e is also provided and connected to via 23, which is coupled to the grounding terminal 63.

[0076] The filter and duplexer used in the fifth embodiment have the configuration mentioned above, in which the capacitors are located between the first ground pattern 53d and the second input / output pattern 51g, and between the input / output pattern 51g and the second ground pattern 50e. An inductor, consisting of the first U-shaped conductor pattern 51f and the second U-shaped conductor pattern 51x, is also connected in series with the receive (output) terminal 61 and the filter chip 110. This allows a large capacitor and inductor to be integrated into such a small space. This enables the laminated section to be reduced in size, thus reducing the overall size of the filter and duplexer. [Sixth embodiment]

[0077] A sixth embodiment of the present invention uses an inductor connected in series with the receive (output) terminal 61 and the output contact point of the filter chip 110, and a capacitor coupled between the ground terminal 63 and the receive (output) terminal 61. The capacitor and the inductor branch off separately from the receive (output) terminal 61. Fig. 17A to Fig. Figure 17D shows the respective layers of the laminated assembly 120 used in the sixth embodiment of the present invention. The layers, which are in Fig. 17A to Fig. Those not shown in 17D have the same configuration as those shown in Fig. 5A to Fig. 5F are shown, which are used in the first embodiment. In the Fig. In the layer 123 shown in 17A for the attachment of semiconductor wafers, a via 21i corresponds to the via 21a in Fig. 5C, and the via 22 corresponds to the via 22a in Fig. 5C. The other components and configurations, such as those in Fig. The reference numbers shown in 17A have the same reference numbers as in Fig. 5C shown.

[0078] Referring to Fig. 17B is provided on the first conductor pattern layer 124, where the first grounding pattern 53d is provided and connected to the via 23, which is coupled to the grounding terminal 63. The via 21i is provided and connected to layer 123 for mounting semiconductor chips and to the second conductor pattern layer 125. Referring to Fig. 17C has a first U-shaped conductor pattern 51i for receiving on the second conductor pattern layer 125 and is connected to the via 21e and a via 21j. The via 21i is coupled to layer 123 for mounting semiconductor chips. The via 21j is coupled to the top of the conductor pattern / foot contact layer 126. The input / output pattern 50 is also connected to a via 20, which is coupled to the receive (output) terminal 61. Referring to Fig. On the top side of conductor pattern / foot contact layer 126, a second U-shaped conductor pattern 51j is provided for receiving and is connected to via 21j and via 21k. Via 21j is connected to the second conductor pattern 125. Via 21k is coupled to the receive (output) terminal 61 on the underside of conductor pattern / foot contact layer 126. The second grounding pattern 53e is provided and connected to via 23, which is coupled to ground terminal 63.

[0079] The filter and duplexer used in the sixth embodiment have the configuration mentioned above, wherein the capacitors are formed between the first ground pattern 53d and the second input / output pattern 50, and between the input / output pattern 50 and the second ground pattern 53e. An inductor consisting of the first U-shaped conductor pattern 51i and the second U-shaped conductor pattern 51j is connected in series with the receive (output) terminal 61 and the filter chip 110. In this way, as described in the fifth embodiment, it is possible to use a large capacitor and inductor in a small space. This allows the laminated section to be reduced in size, thus reducing the dimensions of the filter and duplexer.

[0080] In addition to the configuration used in the fifth embodiment, U-shaped wiring patterns 51i and 52j are also provided. The input / output pattern 50 and the U-shaped wiring patterns 51i and 52j each branch from the receive (output) port 61 and are coupled in parallel to the filter chip 110. The input / output pattern can branch from the U-shaped wiring pattern as described in the fifth embodiment, and the input / output pattern can branch from the receive (output) port 61 or the transmit (input) port 62 as described in the sixth embodiment.

[0081] The fourth to sixth embodiments include the capacitor or inductor coupled to the receive terminal (output terminal) 61. The capacitor or inductor can be coupled to a ground terminal of the transmit terminal (input terminal) as required. The capacitor or inductor can also be connected to both the receive terminal (output terminal) 61 and the transmit terminal (input terminal) 62.

[0082] In the first to sixth embodiments, the respective layers in the base layer 128 preferably have a thickness of 25 µm to 125 µm. If an inductor is connected and the thickness is less than 25 µm, the inductance increases, and the capacitance also increases. Consequently, the insertion loss increases. If the thickness is greater than 125 µm, the capacitance decreases, and the inductance also decreases. This makes it difficult to achieve the goal of miniaturizing the filter and duplexer. If the capacitor is connected and the thickness is less than 25 µm, the capacitance increases, and the inductance also increases. Consequently, the insertion loss increases. If the thickness is greater than 125 µm, the inductance decreases, and the capacitance also decreases. This makes it difficult to achieve the goal of miniaturizing the filter and duplexer.

[0083] Furthermore, in the first to sixth embodiments, the filter chip 110 and the phase-matching circuit 132 are mounted on the laminated assembly 120. However, a laminated substrate or the like can be used if the laminated part contains a ceramic insulating film and the like, and the filter chip 110 can be mounted on the substrate. The receive filter 113 and the transmit filter 112 are formed on an identical chip to serve as the filter chip 110. However, the receive filter 113 and the transmit filter 112 can be formed on different chips and mounted on different laminated parts. Moreover, the filter can enclose either the receive filter chip or the transmit filter chip.

[0084] The filter chip 110 and the phase-matching circuit 132 are also mounted on the laminated part by means of the contact prongs 130. In other words, the filter chip 110 and the phase-matching circuit 132 are bonded with the active side facing downwards. However, the filter chip 110 and the phase-matching circuit 132 can also be mounted on the laminated part by wire bonding. In other words, the filter chip 110 and the phase-matching circuit 132 can be bonded with the active side facing upwards.

[0085] The receive filter 113 and the transmit filter 112 are chips that use SAW filters. However, the chip can also use, for example, a filter with a piezoelectric thin-film resonator. [Seventh embodiment]

[0086] Fig.Figure 18 shows a block diagram of an electronic device according to a seventh embodiment of the present invention. The electronic device serves as a transmitting and receiving system for a mobile phone. The transmitting and receiving system of the mobile phone comprises an RF section 70, a modulator 71, and an IF section 72. The RF section 70 comprises an antenna 73, a duplexer 74, a low-noise amplifier 83, an intermediate filter 84, a mixer 75, a local oscillator 76, an intermediate filter 77, a mixer 78, an intermediate filter 79, and a power amplifier 80. An audio signal, fed in by an audio processing system, is modulated at the modulator 71 and converted into a frequency using an oscillation signal from the local oscillator 97 in the mixer 78 of the RF section 70. The signal output by mixer 78 passes through the intermediate filter 79 and the power amplifier 80 and reaches the duplexer 74.

[0087] The duplexer 74 uses any of the duplexers used in the first through sixth embodiments and comprises a transmit filter 74a, a receive filter 74b, and a phase-matching circuit (not shown). A transmit signal is emitted by the power amplifier 80, passes through the transmit filter 74a of the duplexer 74, and is delivered to the antenna 73. A received signal at the antenna 73 passes through a receive filter 74b of the duplexer 74, through the low-noise amplifier 83 and the intermediate filter 84, and reaches the mixer 75. The mixer 75 receives the oscillation frequency of the local oscillator 76 via the intermediate filter 77, converts the frequency of the received signal, and outputs it to the IF section 72. The IF section 72 receives the aforementioned signal via an IF filter 81, demodulates the signal at a demodulator 82 and outputs the audio signal to the audio processing system.

[0088] The electronic device used in the seventh embodiment utilizes any of the duplexers exemplified in the first to sixth embodiments, thereby creating a miniaturized, cost-effective, high-performance electronic device.

[0089] The filter comprises: a filter chip; a laminated part on which the filter chip is mounted; an input / output port provided in the laminated part; a first U-shaped conductor pattern provided on a first layer and coupled to the filter chip, which first layer is contained in the laminated part between the filter chip and the input / output port; and a second U-shaped conductor pattern provided on a second layer such that it substantially overlaps the first U-shaped conductor pattern and is coupled to the first U-shaped conductor pattern and the input / output port, which second layer is contained in the laminated part between the first layer and the input / output port.

[0090] In the filter described above, a current flowing through the first U-shaped conductor pattern can have the same direction as the current flowing through the second U-shaped conductor pattern. According to the present invention, the self-inductance of the conductor pattern can be further increased. This further reduces the size of the filter and lowers the insertion loss.

[0091] The filter described above can further include a third U-shaped conductor pattern, which is provided in one or more layers in the laminated section between the second layer and the input / output terminal, is coupled to the second U-shaped conductor pattern and the input / output terminal, and has the same current direction as a current flowing through the second U-shaped conductor pattern. According to the present invention, the self-inductance of the conductor pattern can be further increased. This further reduces the size of the filter and lowers the insertion loss.

[0092] In the filter described above, the first, second, and third U-shaped conductor patterns can be configured to overlap the input / output terminal. Alternatively, the first, second, and third U-shaped conductor patterns can be configured to not overlap a grounding pattern in the laminated section. According to the present invention, the capacitance applied between the U-shaped conductor pattern and the ground can be reduced, thereby reducing the insertion loss.

[0093] In the filter described above, the first U-shaped conductor pattern, the second U-shaped conductor pattern, and the third U-shaped conductor pattern each have a distance between conductors that is greater than one conductor width. According to the present invention, the inductance of the U-shaped conductor pattern can be increased, which reduces the size of the filter and the duplexer.

[0094] The filter comprises: a filter chip; a laminated part on which the filter chip is mounted; a grounding terminal provided in the laminated part; a first U-shaped grounding pattern provided on a first layer and coupled to the filter chip, which first layer is contained in the laminated part between the filter chip and the grounding terminal; and a second U-shaped conductor pattern provided on a second layer such that it substantially overlaps the first U-shaped grounding pattern and is coupled to the first U-shaped grounding pattern and the grounding terminal, which second layer is contained in the laminated part between the first layer and the grounding terminal.

[0095] In the filter described above, a current flowing through the first U-shaped grounding pattern can have the same direction as the current flowing through the second U-shaped grounding pattern. According to the present invention, it is possible to increase the self-inductance of the grounding pattern and further reduce the size of the filter.

[0096] The filter described above can further comprise a third U-shaped grounding pattern, which is provided in one or more layers in the laminated part between the second layer and the grounding terminal, is coupled to the second U-shaped grounding pattern and the grounding terminal, and has the same current direction as a current flowing through the second U-shaped grounding pattern. According to the present invention, it is possible to increase the self-inductance of the grounding pattern and to further reduce the size of the filter.

[0097] In the filter described above, the first U-shaped grounding pattern, the second U-shaped grounding pattern, and the third U-shaped grounding pattern can be configured such that they do not overlap a conductive pattern in the laminated part. According to the present invention, it is possible to reduce the capacitance induced between terminals other than the grounding terminal and the ground, and thus to reduce the insertion loss.

[0098] The filter comprises: a filter chip; a laminated part on which the filter chip is mounted; a grounding connection provided in the laminated part; a first grounding pattern provided on a first layer and coupled to the filter chip, which first layer is contained in the laminated part between the filter chip and the grounding connection; a second grounding pattern provided on a third layer such that it substantially overlaps the first grounding pattern and is coupled to the first grounding pattern and the grounding connection, which third layer is contained in the laminated part between the first layer and the grounding connection;and an input / output pattern provided on a second layer such that it substantially overlaps the first grounding pattern and the second grounding pattern, and is coupled to the filter chip and an input / output connector, which second layer is contained in the laminated part between the first layer and the third layer.

[0099] In the filter described above, the first and second grounding patterns can be configured such that they do not overlap an input / output terminal in the laminated section. According to the present invention, the capacitance applied between the grounding pattern and the input / output terminal can be reduced, and the insertion loss can be reduced.

[0100] In the filter described above, the input / output pattern can have a smaller area than at least one of the areas of the first grounding pattern and the second grounding pattern. According to the present invention, it is possible to reliably form the input / output pattern between the first grounding pattern and the second grounding pattern, even if the layers are misaligned during the manufacturing process of the laminated part. It is therefore possible to eliminate the variation in capacitance generation.

[0101] The filter described above can further include a U-shaped wiring pattern coupled to the filter chip and the input / output terminal. In the filter described above, both the input / output pattern and the U-shaped wiring pattern branch off from the input / output terminal. According to the present invention, it is possible to use a capacitor with a large capacitance and an inductor in a small space. This can reduce the size of the laminated part and the filter.

[0102] The filter chip described above can contain a surface acoustic wave filter. The filter chip can also contain a filter with a piezoelectric thin-film resonator.

[0103] The device comprises a duplexer containing a transmit filter coupled to a transmit port; a receive filter coupled to a receive port; a phase-matching circuit coupled to a common port, the transmit port, and the receive port to match the phases of the transmit and receive filters; and a laminated section on which the phase-matching circuit is mounted. The transmit filter and the receive filter may each contain any of the filters described above.

[0104] In the duplexer mentioned above, the laminated section can be used jointly for the transmit filter and the receive filter.

Claims

[1] Duplexer (100) with: a transmit filter (112) coupled between a transmit port (62) and a common port (68); a receiving filter (113) coupled between a receiving port (61) and the common port (68); a phase matching circuit (132) which is coupled to the common terminal (68), the transmit terminal (62) and the receive terminal (61) to match the phases of the transmit filter (112) and the receive filter (113); a laminated part (128) on which the phase matching circuit (132) is mounted; a filter chip (110) or transmit and receive filter chips which is / are mounted on the laminated part (128), wherein the transmit filter (112) and the receive filter (113) are formed in the filter chip (110) or the transmit filter (112) and the receive filter (113) are formed in the transmit and receive filter chips respectively; wherein at least one of the transmitting port (62) and the receiving port (61) is provided in the laminated part (128) corresponding to at least one of the transmitting filter (112) and the receiving filter (113); a first U-shaped conductor pattern (51a, 52a) provided on a first layer (124) and coupled between at least one of the transmit filter (112) and the receive filter (113) and the at least one of the transmit terminal (62) and the receive terminal (61), which first layer (124) is contained in the laminated part (128) between the filter chip (110) or the transmit and receive filter chips and the at least one of the transmit terminal (62) and the receive terminal (61); a second U-shaped conductor pattern (51b, 52b) provided on a second layer (125) such that it overlaps the first U-shaped conductor pattern (51a, 52a) and is coupled between the first U-shaped conductor pattern (51a, 52a) and the at least one of the transmit terminal (62) and the receive terminal (61), which second layer (125) is contained in the laminated part (128) between the first layer (124) and the at least one of the transmit terminal (62) and the receive terminal (61); and a third U-shaped conductor pattern (51c, 52c) which is provided in one or more layers in the laminated part (128) between the second layer (125) and the at least one of the transmit terminal (62) and the receive terminal (61), coupled between the second U-shaped conductor pattern (51b, 52b) and the at least one of the transmit terminal (62) and the receive terminal (61) and with the same current direction as a current flowing through the second U-shaped conductor pattern (51b, 52b), wherein the first U-shaped conductor pattern (51a, 52a), the second U-shaped conductor pattern (51b, 52b) and the third U-shaped conductor pattern (51c, 52c) are designed such that they do not overlap an earthing terminal (63, 64, 65, 67, 69) in the laminated part (128). [2] Duplexer according to claim 1, wherein a current flowing through the first U-shaped conductor pattern (51a, 52a) has the same direction as the current flowing through the second U-shaped conductor pattern (51b, 52b). [3] Duplexer (100) with: a transmit filter (112) coupled between a transmit port (62) and a common port (68); a receiving filter (113) coupled between a receiving port (61) and the common port (68); a phase matching circuit (132) which is coupled to the common terminal (68), the transmit terminal (62) and the receive terminal (61) to match the phases of the transmit filter (112) and the receive filter (113); a laminated part (128) on which the phase matching circuit (132) is mounted; a filter chip (110) or transmit and receive filter chips which is / are mounted on the laminated part (128), wherein the transmit filter (112) and the receive filter (113) are formed in the filter chip (110) or the transmit filter (112) and the receive filter (113) are formed in the transmit and receive filter chips respectively; wherein at least one of the transmitting port (62) and the receiving port (61) is provided in the laminated part (128) corresponding to at least one of the transmitting filter (112) and the receiving filter (113); a first U-shaped conductor pattern (51a, 52a) provided on a first layer (124) and coupled between at least one of the transmit filter (112) and the receive filter (113) and the at least one of the transmit terminal (62) and the receive terminal (61), which first layer (124) is contained in the laminated part (128) between the filter chip (110) or the transmit and receive filter chips and the at least one of the transmit terminal (62) and the receive terminal (61); a second U-shaped conductor pattern (51b, 52b) provided on a second layer (125) such that it overlaps the first U-shaped conductor pattern (51a, 52a) and is coupled between the first U-shaped conductor pattern (51a, 52a) and the at least one of the transmit terminal (62) and the receive terminal (61), which second layer (125) is contained in the laminated part (128) between the first layer (124) and the at least one of the transmit terminal (62) and the receive terminal (61); and a third U-shaped conductor pattern (51c, 52c) which is provided in one or more layers in the laminated part (128) between the second layer (125) and the at least one of the transmit terminal (62) and the receive terminal (61), coupled between the second U-shaped conductor pattern (51b, 52b) and the at least one of the transmit terminal (62) and the receive terminal (61) and with the same current direction as a current flowing through the second U-shaped conductor pattern (51b, 52b), where: the first U-shaped conductor pattern (51a, 52a), the second U-shaped conductor pattern (51b, 52b) and the third U-shaped conductor pattern (51c, 52c) are configured such that they overlap at least one of the transmit terminal (62) and the receive terminal (61); and Small capacitive components are always present with the grounding, and these capacitive components can be compensated by an inductive component in the form of the U-shaped conductor patterns. [4] Duplexer (100) according to claim 3, wherein the small capacitive components are present with the grounding in the laminated part. [5] Duplexer (100) with: a transmit filter (112) coupled between a transmit port (62) and a common port (68); a receiving filter (113) coupled between a receiving port (61) and the common port (68); a phase matching circuit (132) which is coupled to the common terminal (68), the transmit terminal (62) and the receive terminal (61) to match the phases of the transmit filter (112) and the receive filter (113); a laminated part (128) on which the phase matching circuit (132) is mounted; a filter chip (110) or transmit and receive filter chips which is / are mounted on the laminated part (128), wherein the transmit filter (112) and the receive filter (113) are formed in the filter chip (110) or the transmit filter (112) and the receive filter (113) are formed in the transmit and receive filter chips respectively; wherein at least one of the transmitting port (62) and the receiving port (61) is provided in the laminated part (128) corresponding to at least one of the transmitting filter (112) and the receiving filter (113); a first U-shaped conductor pattern (51a, 52a) provided on a first layer (124) and coupled between at least one of the transmit filter (112) and the receive filter (113) and the at least one of the transmit terminal (62) and the receive terminal (61), which first layer (124) is contained in the laminated part (128) between the filter chip (110) or the transmit and receive filter chips and the at least one of the transmit terminal (62) and the receive terminal (61); a second U-shaped conductor pattern (51b, 52b) provided on a second layer (125) such that it overlaps the first U-shaped conductor pattern (51a, 52a) and is coupled between the first U-shaped conductor pattern (51a, 52a) and the at least one of the transmit terminal (62) and the receive terminal (61), which second layer (125) is contained in the laminated part (128) between the first layer (124) and the at least one of the transmit terminal (62) and the receive terminal (61); and a third U-shaped conductor pattern (51c, 52c) which is provided in one or more layers in the laminated part (128) between the second layer (125) and the at least one of the transmit terminal (62) and the receive terminal (61), coupled between the second U-shaped conductor pattern (51b, 52b) and the at least one of the transmit terminal (62) and the receive terminal (61) and with the same current direction as a current flowing through the second U-shaped conductor pattern (51b, 52b), where: the first U-shaped conduit pattern (51a, 52a), the second U-shaped conduit pattern (51b, 52b) and the third U-shaped conduit pattern (51c, 52c) each have a distance between conduits that is greater than a conduit width; and Small capacitive components are always present with the grounding, and these capacitive components can be compensated by an inductive component in the form of the U-shaped conductor patterns. [6] Duplexer (100) according to claim 5, wherein the small capacitive components are present with the grounding in the laminated part. [7] Duplexer (100) with: a transmit filter (112) coupled between a transmit port (62) and a common port (68); a receiving filter (113) coupled between a receiving port (61) and the common port (68); a phase matching circuit (132) which is coupled to the common terminal (68), the transmit terminal (62) and the receive terminal (61) to match the phases of the transmit filter (112) and the receive filter (113); a laminated part (128) on which the phase matching circuit (132) is mounted; a filter chip (110) or transmit and receive filter chips which is / are mounted on the laminated part (128), wherein the transmit filter (112) and the receive filter (113) are formed in the filter chip (110) or the transmit filter (112) and the receive filter (113) are formed in the transmit and receive filter chips respectively; an earthing connection (63, 64, 65, 67, 69) provided in the laminated part (128); a first grounding pattern (53d) provided on a first layer (124) and coupled between at least one of the transmit filter (112) and the receive filter (113) and the grounding terminal (63), which first layer (124) is contained in the laminated part (128) between the filter chip (110) or the transmit and receive filter chips and the grounding terminal (63); a second earthing pattern (53e) provided on a third layer (126) such that it overlaps the first earthing pattern (53d) and is coupled between the first earthing pattern (53d) and the earthing terminal (63), which third layer (126) is contained in the laminated part (128) between the first layer (124) and the earthing terminal (63); and at least one of a transmit pattern and a receive pattern (51g, 50) corresponding to at least one of the transmit filter (112) and the receive filter (113), which is provided on a second layer (125) such that it overlaps the first grounding pattern (53d) and the second grounding pattern (53e), and is coupled between at least one of the transmit filter (112) and the receive filter (113) and at least one of the transmit terminal (62) and the receive terminal (61) corresponding to at least one of the transmit filter (112) and the receive filter (113), which second layer (125) is contained in the laminated part (128) between the first layer (124) and the third layer (126), where: the first and second grounding patterns (53d, 53e) and the at least one of a transmit pattern and a receive pattern (51g, 50) forming a capacitor; and a U-shaped line pattern (51f, 51i) between which at least one of the transmit filter (112) and the receive filter (113) is coupled and at least one of the transmit terminal (62) and the receive terminal (61). [8] Duplexer according to claim 7, wherein the first grounding pattern (53d) and the second grounding pattern (53e) are designed such that they do not overlap the at least one of the transmit terminal (62) and the receive terminal (61) in the laminated part. [9] Duplexer according to claim 7, wherein at least one of a transmit pattern and a receive pattern (51g, 50) has a smaller area than at least one of the areas of the first grounding pattern (53d) and the second grounding pattern (53e). [10] Duplexer according to claim 7, wherein the at least one transmit pattern and receive pattern (51g) and the U-shaped line pattern (51f) are connected on the second layer (125). [11] Duplexer according to claim 7, wherein the at least one transmit pattern and receive pattern (50) and the U-shaped line pattern (51i) each branch off from the at least one transmit terminal (62) and receive terminal (61). [12] Duplexer according to claim 1, wherein the filter chip includes a surface acoustic wave filter. [13] Duplexer according to claim 1, wherein the filter chip includes a filter with a piezoelectric thin-film resonator.

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