Switch

Abstract

Switch (10) which has the following features: a switching transistor (12); a switching resistor (R) that is connected between a control terminal (14) of the switching transistor (12) and a switching control terminal (16) to which a switching control signal is applied; and an accelerator element (18) having a resistance value less than the resistance value of the switching resistor (R), wherein the accelerator element (18) is adapted to be switched in parallel with the switching resistor (R) for a predetermined time period by an accelerator control signal (22) having signal states to switch the accelerator element (18) on or off when the switching transistor (12) switches from a blocking state to a conducting state or when the switching transistor (12) switches from the conducting state to the blocking state, until a voltage at the control terminal (14) of the switching transistor (12) reaches a predetermined value.

Description

[0001] Exemplary embodiments of the invention relate to a switch comprising a switching transistor, a switching resistor and an accelerator element.

[0002] Exemplary embodiments of the invention provide a switch comprising a switching transistor, a switching resistor connected between a control terminal of the switching transistor and a switching control terminal, and an accelerator element having a resistance value lower than the resistance value of the switching resistor, wherein the accelerator element is adapted to be connected in parallel with the switching resistor after the switching transistor has been switched, until a voltage at the control terminal of the switching transistor has reached a predetermined value.

[0003] US Patent 2006 / 0120004 A1 describes a driver circuit and method with reduced dI / dt and delay compensation. The method for driving a power transistor switch includes receiving a drive input signal, converting the drive input signal into a converted drive input signal, and providing a converted gate drive signal to a control electrode of the switch to turn the switch on. The converted drive input signal has three time regions, each with a ramp. A first time region has a first ramp up to a Miller plateau of the switch. A second time region has a second ramp with a reduced slope compared to the first ramp. A third time region has a third slope that is greater than the second slope.This allows the control electrode voltage to quickly reach the Miller plateau voltage, then more slowly a switch threshold voltage, and then, when the switch is essentially fully on, the control electrode voltage increases rapidly. The switching delay time is kept essentially constant by adjusting the transistor control electrode pre-charge voltage.

[0004] US Patent 6,333,665 B1 describes a gate circuit for an insulated-gate semiconductor device. The circuit includes positive and negative control power sources, as well as first and second semiconductor component groups in which a plurality of semiconductor components are connected in series to the positive and negative control power sources. The circuit further includes a switching signal source that provides on / off control signals to semiconductor components of the first and second semiconductor component groups. The circuit also includes delay circuits that delay the on / off control signals supplied to the semiconductor components of the first and second semiconductor component groups for a specified time.

[0005] US Patent 2005 / 0128671 A1 describes a control device for a switching device and a control device for a motor driver circuit. The control device includes a capacitor placed between PN leads, forming a damper circuit. The control device further includes a voltage detection resistor for detecting a voltage between the PN leads, using divider resistors to detect transistor surge voltages. Gate control signals are provided by drivers via variable gate resistors. The variable resistors are variable values, and their resistance values ​​are controlled based on corresponding control signals supplied by a voltage monitoring device.

[0006] JP 2008-017 416 A describes a high-frequency switching component. This component comprises two terminals for receiving and outputting the high-frequency signal, respectively, and a third terminal for applying a control voltage. The switching component includes a switching transistor that selectively applies a high-level or low-level voltage to the third terminal, thereby making a path between a source and a drain electrically conductive or creating a pinch point between the source and drain. The high-frequency switching component includes a variable resistor connected to the gate of the switching transistor and to a fourth terminal. The resistance value can be controlled by a voltage applied to a fifth terminal. The variable resistor changes its resistance value according to the on-state or off-state of the switching transistor.

[0007] German patent DE 10 2005 027 426 A1 describes an electronic high-frequency switch with a gallium arsenide field-effect transistor. In this electronic high-frequency switch with a gallium arsenide field-effect transistor, where the control DC voltage, which can be switched between positive and negative, is supplied to the gate terminal via a gate resistor with a capacitor arranged in parallel, a diode is arranged between the capacitor and the reference potential. This diode is polarized such that it is reverse-biased when the control DC voltage is positive and conducting when the control DC voltage is negative.

[0008] DE 101 51 700 A1 discloses a field-effect semiconductor device in which the switching process is effected by a gate voltage supplied externally via a gate resistor circuit in order to limit charging and discharging currents flowing between an isolated gate and an emitter, wherein the FET semiconductor device comprises: an isolated gate electrode region formed by a gate electrode terminal and a gate electrode isolated from it; the gate resistor circuit is inserted between the gate electrode terminal and the gate electrode in such a way that it is integral with the isolated gate electrode region; and the gate resistor circuit comprises a first gate resistor and a first series circuit connected in parallel with the first gate resistor, which comprises a second gate resistor and a first diode, such that an anode of the first diode is connected to the gate electrode.

[0009] The object of the present invention is to create a switch and a method for switching with improved characteristics.

[0010] The problem is solved by the characteristics of independent claims. Further details can be found in dependent claims.

[0011] Preferred embodiments of the present invention are explained in more detail below with reference to the accompanying drawings. These show: Fig. 1a a circuit diagram of a switch according to an embodiment of the invention; Fig. 1b a circuit diagram of an acceleration element according to an embodiment of the invention, comprising a series connection of a resistor and a switch; Fig. 1c a circuit diagram of an accelerator element according to another embodiment of the invention, comprising a diode; Fig. 1d a circuit diagram of an accelerator element according to another embodiment of the invention, comprising a field-effect transistor (FET); Fig. 2 a circuit diagram of a switch according to another embodiment of the invention; Fig. 3 a timing diagram of the control signals for controlling a switch according to an embodiment of the invention; Fig. 4 a timing diagram of other control signals for controlling a switch according to an embodiment of the invention; Fig. 5 a circuit diagram of a device for controlling a switch according to an embodiment of the invention; and Fig. 6 a circuit diagram of another device for controlling a switch according to an embodiment of the invention.

[0012] Switches, especially switches for switching high-frequency (RF) signals within integrated circuits, are used in wireless communication applications, satellite and cable television. Switching circuits can incorporate RF CMOS (radio frequency complementary metal oxide semiconductor) devices, which are suitable for high-power applications.

[0013] High-power RF CMOS switches can have limitations in terms of switching time, which can be in the range of a few microseconds, due to the use of high-impedance resistors necessary to isolate the large-amplitude RF signal present at the gates from the output of the gate driver circuits. While this is acceptable for static switching, many applications require switching times in the range of tens or hundreds of nanoseconds. The large time constant of the high-impedance resistors, together with the large gate capacitance of the switching transistors, defines the long switching time. This can usually be improved by reducing the gate length, thereby reducing the gate capacitance. However, reducing the value of the gate resistors is only possible if a sufficient margin is available for RF insertion loss and linearity, which is often not achievable due to engineering constraints.

[0014] Therefore, there is a need to improve the switching time without reducing the gate capacitance of the switching transistor or without changing the semiconductor design of the switching transistors.

[0015] Fig. Figure 1a shows a circuit diagram of a switch according to an embodiment of the invention. The switch 10 comprises a switching transistor (FET) 12 and a switching resistor R, which is connected between a control terminal 14 of the switching transistor 12 and a switching control terminal 16. The switch 10 further comprises an accelerator element 18 with a resistance value that is lower than the resistance value of the switching resistor R. The accelerator element 18 can be connected in parallel with the switching resistor R after the switching transistor 12 has been switched, until a voltage at the control terminal 14 of the switching transistor 12 has reached a predetermined value.

[0016] The capacitance at the control terminal is a parasitic capacitance, dependent on the semiconductor material, design, channel length, and gate length. It can be the gate-source capacitance and the Miller capacitance of FET 12. After the gate-source capacitance is charged, a channel is formed in FET 12. Charging the Miller capacitance reduces the depletion region to such an extent that FET 12 is turned on. The response time of FET 12 depends on a time constant formed by the parallel connection of the capacitance at the control terminal (gate-source capacitance and / or Miller capacitance) and a resistance value at the control terminal. The resistance value at the control terminal is formed by the parallel connection of R and the accelerator element 18 and is high when the accelerator element 18 has a high resistance value and low when the accelerator element 18 has a low resistance value.The time constant can be determined by multiplying the resistance value at the control terminal and the capacitance at the control terminal.

[0017] Switch 10 is connected between an input terminal 24 and an output terminal 26. Switch 10 passes a signal received at input terminal 24 to output terminal 26 when it is in a conductive state, and isolates the signal received at input terminal 24 from output terminal 26 when it is in a blocked state. The control terminal 14 of switching transistor 12 receives a switching control signal at control terminal 16 to switch the switching transistor 12 between a conductive state and a blocked state.

[0018] The switching resistor R is dimensioned to isolate a signal received at the input terminal 24 from the switching control terminal 16. The resistance value of the switching resistor R and the capacitance of the control terminal 14 of the switching transistor 12 form an RC time constant of a low-pass circuit, which is responsible for the switching time. Due to technical limitations, the capacitance of the control terminal 14 of the switching transistor 12 should not be varied. Therefore, the switching resistor R defines the switching time. A low value for the switching resistor R results in a fast switching time, whereas a large value for the switching resistor R results in a slow switching time.Since the switching resistor R is used to isolate the signal received at input terminal 24 from the switching control terminal 16, the switching resistance R should not fall below a predetermined value (depending on the signal to be switched and received at input terminal 24). For high-frequency signals, typical values ​​of the switching resistance R range, for example, from approximately 20 kΩ to approximately 300 kΩ. According to embodiments of the invention, the switching resistance can be approximately 30 kΩ. The channel widths of the switching transistors 12 in a typical RF switch are in the range of a few millimeters and determine a large gate volume capacitance in the on-state in the range of a few pF to approximately 100 pF, depending on the transistor size.The combination of a large parasitic capacitance (corresponding to the capacitance at the control terminal 14 of the switching transistor 12) and the high switching resistance values ​​and limited drive voltage amplitude available at the switching control terminal 16 results in switching times as short as a few microseconds. For example, a switching resistance R of 30 kΩ, together with a control terminal 14 capacitance of 100 pF on the switching transistor 12, defines an RC time constant of three microseconds. The switching resistance R has a high resistance value to prevent additional loss and distortion due to insufficient high-frequency isolation between the control terminal 14 of the switching transistor 12 and the switching control terminal 16, which is used to connect low-output impedance control terminal drivers.

[0019] According to exemplary embodiments of the invention, the switch 10 reduces the switching time by connecting an accelerator element 18 in parallel with the switching resistor R, thereby reducing the resistance connected to the control terminal 14 of the switching transistor 12 during switching. The accelerator element 18 has a resistance value lower than that of the switching resistor R, thus reducing the RC time constant of the switching transistor 12 during switching of the switch 10. Connecting the accelerator element 18 in parallel with the switching resistor R reduces the voltage at the control terminal 14 of the switching transistor 12, depending on the RC time constant.

[0020] The switching transistor 12 can be a MOSFET transistor with a gate capacitance equal to the capacitance of the control terminal 14 of the switching transistor 12. The discharge and recharge of the gate capacitance determines the possible switching time of the switching transistor 12. The accelerator element 18 speeds up the discharge or charge of the gate capacitance of the switching transistor 12 due to a reduced gate resistance during switching.

[0021] When the switching transistor 12 changes from a blocking state to a conducting state, the accelerator element 18 is connected in parallel with the switching resistor R, such that the gate capacitance of the switching transistor 12 discharges. After the discharge process is complete, the accelerator element 18 is switched off from the switching resistor R, such that the control terminal 14 exhibits a high resistance value, specified by the switching resistor R, in order to isolate a signal received at the input terminal 24 from the switching control terminal 16.

[0022] When the switching transistor 12 changes from the conducting state to the blocking state, the accelerator element 18 is again connected in parallel with the switching resistor R to allow accelerated charging of the gate capacitance of the switching transistor 12. After the switching transistor 12 has finished charging its gate capacitance, the accelerator element 18 is disconnected from the switching resistor R to provide a high resistance value at the control terminal 14 of the switching transistor 12, in order to isolate the signal received at the input terminal 24 from the switching control terminal 16.

[0023] The switching of the acceleration element 18 can be carried out by the acceleration switch 20, which is controlled by the acceleration control signal 22 (see Fig. 1b to 1d). The acceleration control signal 22 is adapted to adjust the switching of the acceleration element 18 in parallel with the switching resistor R with respect to the discharge and charge process of the gate capacitance of the switching transistor 12. The acceleration control signal 22 can depend on a switching signal received at the switching control terminal 16, which is adapted to switch the switching transistor 12 to switch the signal received at the input terminal 24 to the output terminal 26. The acceleration control signal 22 can further depend on an RC time constant corresponding to the RC time constant of the switching transistor 12. For example, a device using a resistance value similar to that of the switching transistor R and a copy of the gate capacitance of the switching transistor 12 can generate the acceleration control signal 22 depending on the switching signal received at the switching control terminal 16.

[0024] As in Fig. As shown in Figure 1b, the switch 10 can, according to this embodiment, be an accelerator element with an accelerator resistance R. acc and a switch 20 for switching the resistor R acc The switch 20 is controlled by an acceleration control signal 22. The acceleration element 18 is connected in parallel to the switching resistor R between the control terminal 14 of the switching resistor 12 and the switching control terminal 16.

[0025] As in Fig. As shown in Figure 1c, the accelerator element 18 can further comprise a diode 30 with a forward resistance value that is smaller than the resistance value of the switching resistor R. The diode can, for example, be connected in a forward direction in parallel with the switching resistor R after recharging processes of the gate capacitance of the switching transistor 12, and can be connected in reverse direction in parallel with the switching resistor R by the accelerator control signal 22 as soon as the charging / recharging process of the gate capacitance of the switching transistor 12 is complete.

[0026] The diode 30 can comprise a plurality of diodes and / or nonlinear elements that can be switched from a first state with a first (e.g., high) impedance to a second state with a second (e.g., low) impedance by the acceleration control signal 22. The acceleration element 18 is connected in parallel with the switching resistor R between the control terminal 14 of the switching transistor 12 and the switching control terminal 16.

[0027] The diode 30 can comprise two switchable diodes connected in reverse series such that the cathodes of the two switchable diodes are connected together. The two diodes can be switched by the acceleration control signal 22, which is received by the connected cathodes. The diode 30 can also comprise a plurality of the two switchable diodes.

[0028] The acceleration element 18 can further comprise an acceleration transistor (FET) 32, which is controlled by the acceleration control signal 22, as described in Fig. Figure 1d shows an accelerator transistor stack (a plurality of transistors connected in series). The switching of the accelerator element 18 from a first state, indicating a high impedance corresponding to a high channel resistance of the FET 32, to a second state, indicating a low impedance corresponding to a low channel resistance of the FET 32, is controlled by the accelerator control signal 22 being received at a control terminal of the accelerator element 18.

[0029] In Fig. In 1d, the accelerator element 18 has a FET 32. The FET 32 has a first terminal 36 which is connected to the control terminal 14 of the switching transistor 12, a second terminal 38 which is connected to the switching control terminal 16, and a control terminal 40 which is used to receive the accelerator control signal 22.

[0030] The control terminal 40 receives the acceleration control signal 22. The acceleration control signal 22 has signal states for switching the FET 32 on or off. The FET 32 has a channel width that is smaller than the channel width of the switching FET 12, i.e., it has a lower resistance value. The width of the FET 32 is selected such that the resistance value of the FET 32 connected in parallel with the resistor R is smaller than the resistance value of the switching resistor R. The FET 32 is switched on for a time period described above, after the transition of the switching signal at the switching control terminal 16.

[0031] Fig. Figure 2 shows a circuit diagram of a switch according to another embodiment of the invention. The switch 10 has an input terminal INPUT for receiving an input signal and an output terminal OUTPUT, a reference terminal REF connected to a reference voltage, e.g., to ground, a switching control terminal CONTROL 16 for receiving the switching control signal, a first acceleration control terminal Vr for receiving a first acceleration control signal, and a second acceleration control terminal #Vr for receiving a second acceleration control signal.

[0032] Switch 10 comprises four switching transistors N1-N4, four accelerators 101-104, and four switching resistors R1-R4. Switch 10 further comprises a first driver D1, which is connected to the switching control terminal CONTROL, and a second driver D2, which is connected to the switching control terminal CONTROL via an inverter I1.

[0033] The first switching resistor R4 is connected between the control terminal of the first switching transistor N4 and the output of the first driver D1. The second switching resistor R3 is connected between the control terminal of the second switching transistor N3 and the output of the first driver D1, with the input of the first driver D1 connected to the switching control terminal 16. The third switching resistor R1 is connected between the control terminal of the third switching transistor N1 and the output of the second driver D2. The fourth switching resistor R2 is connected between the control terminal of the fourth switching transistor N2 and the output of the second driver D2.

[0034] The acceleration elements 101 - 104 are connected in parallel to the respective switching resistors R4 - R1.

[0035] The first terminal of the first switching transistor N4 is connected to the second terminal of the second switching transistor N3. The second terminal of the first switching transistor N4 is connected to the input terminal INPUT. The first terminal of the second switching transistor N3 is connected to the output terminal OUTPUT. The second terminal of the second switching transistor N3 is connected to the first terminal of the first switching transistor N4. The first terminal of the third switching transistor N1 is connected to the reference terminal REF. The second terminal of the third switching transistor N1 is connected to the first terminal of the fourth switching transistor N2. The first terminal of the fourth switching transistor N2 is connected to the second terminal of the third switching transistor N1. The second terminal of the fourth switching transistor N2 is connected to the output terminal OUTPUT.

[0036] Each of the acceleration elements 101 - 104 has corresponding acceleration transistors N5 - N12 connected in series.

[0037] The first terminal of the first accelerator transistor N10 is connected to the switching control terminal CONTROL via the first driver D1. The second terminal of the first accelerator transistor N10 is connected to the first terminal of the second accelerator transistor N9. The control terminal of the first accelerator transistor N10 is connected to the first accelerator control terminal Vr via a first accelerator resistor R10. The first terminal of the second accelerator transistor N9 is connected to the second terminal of the first accelerator transistor N10. The second terminal of the second accelerator transistor N9 is connected to the control terminal of the first switching transistor N4. The control terminal of the second accelerator transistor N9 is connected to the accelerator control terminal Vr via a second accelerator resistor R9.

[0038] The first terminal of the third accelerator transistor N12 is connected to the CONTROL control terminal via the first driver D1. The second terminal of the third accelerator transistor N12 is connected to the first terminal of the fourth accelerator transistor N11. The control terminal of the third accelerator transistor N12 is connected to the first accelerator control terminal Vr via a third accelerator resistor R12. The first terminal of the fourth accelerator transistor N11 is connected to the second terminal of the third accelerator transistor N12. The second terminal of the fourth accelerator transistor N11 is connected to the control terminal of the second switching transistor N3. The control terminal of the fourth accelerator transistor N11 is connected to the accelerator control terminal Vr via a fourth accelerator resistor R11.

[0039] The first terminal of the fifth accelerator transistor N5 is connected to the second terminal of the sixth accelerator transistor N6. The second terminal of the fifth accelerator transistor N5 is connected, via the second driver D2 and the inverter I1, to the switching control terminal CONTROL. The control terminal of the fifth accelerator transistor N5 is connected, via a fifth accelerator resistor R5, to the second accelerator control terminal #Vr. The first terminal of the sixth accelerator transistor N6 is connected to the control terminal of the third switching transistor N1. The second terminal of the sixth accelerator transistor N6 is connected to the first terminal of the fifth accelerator transistor N5. The control terminal of the sixth accelerator transistor N6 is connected, via a sixth accelerator resistor R6, to the second accelerator control terminal #Vr.

[0040] The first terminal of the seventh accelerator transistor N7 is connected to the second terminal of the eighth accelerator transistor N8. The second terminal of the seventh accelerator transistor N7 is connected, via the second driver D2 and the inverter I1, to the switching control terminal CONTROL. The control terminal of the seventh accelerator transistor N7 is connected, via a seventh accelerator resistor R7, to the second accelerator control terminal #Vr. The first terminal of the eighth accelerator transistor N8 is connected to the control terminal of the fourth switching transistor N2. The second terminal of the eighth accelerator transistor N8 is connected to the first terminal of the seventh accelerator transistor N7. The control terminal of the eighth accelerator transistor N8 is connected, via an eighth accelerator resistor R8, to the second accelerator control terminal #Vr.

[0041] The accelerator transistors N10, N9, N12, and N11 of accelerator elements 101 and 102 are controlled by an accelerator control signal received at the first accelerator control terminal Vr. This accelerator control signal switches the transistors on for a predetermined initial time period following a transition of the switching control signal, thus accelerating the charging or discharging of the gate capacitances of the first and second switching transistors N4 and N3. Similarly, the accelerator transistors N5, N6, N7, and N8 of accelerator elements 103 and 104 are controlled by a second accelerator control signal received at the second accelerator control terminal Vr.The second acceleration control signal switches the transistors on during a second predetermined time period after a transition of the switching control signal in order to accelerate a charging or discharging of gate capacitances of the third and fourth switching transistors N1 and N2.

[0042] The first and second predetermined time periods depend on the RC time constant of the parallel connection of the resistance and capacitance at the control terminal of the corresponding switching transistors and are controlled by the acceleration control signals generated at the transition of a switching control signal received at the CONTROL switching control terminal. The first and second predetermined time periods are described below in Fig. 3 and Fig. 4 described.

[0043] Switch 10 is a single-pole double-throw (SP2T) switch that switches an input signal received at the input terminal INPUT, e.g., a high-frequency (RF) signal, to the output terminal OUTPUT, or a reference signal received at the reference terminal REF, e.g., a ground, to the output terminal OUTPUT, depending on the switching control signal received at the switching control terminal CONTROL. The transistors of switch 100 can be field-effect transistors, metal-oxide-semiconductor transistors, or complementary metal-oxide-semiconductor transistors.

[0044] Switch 10 has an input-output path comprising the first switching transistor N4 and the second switching transistor N3, and a reference output path comprising the third switching transistor N1 and the fourth switching transistor N2. Both the first and second switching transistors N4 and N3, as well as the third and fourth switching transistors N1 and N2, are connected in a stacked configuration. A stacked configuration is a series connection of the switching transistors with respect to their first and second terminals, such that a voltage across the stacked transistors can be divided into voltages across the individual transistors. This results in higher reverse voltage ratings for the stacked configuration of transistors.

[0045] Fig. Figure 2 shows a stacked configuration of two transistors, but any other number of stacked transistors can be used. Depending on the reverse voltage requirements between the input terminal (INPUT) and the output terminal (OUTPUT), a higher number of stacked transistors can also be used. For example, implementing a reverse voltage of approximately 25 volts requires ten stacked transistors if each transistor provides an individual reverse voltage of approximately 2.5 volts. In the reference output path, the third switching transistor (N1) and the fourth switching transistor (N2) are also stacked, depending on the reverse voltage between the output terminal (OUTPUT) and the reference terminal (REF). It may also be possible to have a different number of stacked transistors in the reference output path than in the input-output path, e.g.,If the reference output path requires a different reverse voltage than the input-output path, for example, five stacked transistors are sufficient for a reverse voltage of approximately 12.5 volts in the reference output path, provided each transistor supplies a reverse voltage of approximately 2.5 volts. In addition to the switching transistors, the accelerator transistors can also be arranged in a stacked configuration. Each of the four accelerator elements 101, 102, 103, and 104 can have the same number of stacked transistors or a different number, depending on the reverse voltage required between the control terminals of the respective switching transistors and the output of the respective drivers.The switching resistors R4, R3, R1, R2 isolate voltages at the respective control terminals of the switching transistors N4, N3, N1, N2 from the output of the drivers D1, D2, which may have a low-impedance output.

[0046] The stacking of the switching transistors 12 causes them to dissipate little high-frequency energy through the stacked switching resistors R. The RC time constant formed by the stacked switching resistor and the capacitance of the control terminal 14 of the stacked switching transistors 12 can be designed to be much longer than the period of the high frequency received at the input terminal 24. This arrangement allows a high-frequency voltage drop between the input terminal 24 and the output terminal 26 to be shared equally across the series-connected, stacked switching transistors 12, such that the breakdown voltage across series-connected, or series-connected, stacked switching transistors is increased by the number of stacked switching transistors.

[0047] Fig. Figure 2 shows a switch 10 that has configurations of two stacked switching transistors and two stacked accelerator transistors. Another variant of the switch 10, as shown in Fig. Figure 2 shows configurations of three to nine (or any number of) stacked switching transistors N1 - N4 and three to nine (or any equal or other number of) stacked accelerator transistors N5 - N12.

[0048] To summarize the above, switch 10 reduces the switching time of RF CMOS circuits down to a few hundred nanoseconds without affecting the RF behavior. Switch 10 significantly improves the switching time by bypassing the accelerators 101, 102, 103, 104 to resistors R4, R3, R1, R2. The accelerators 101, 102, 103, 104 can be stacked and are driven by a dedicated control circuit arrangement (see Figure 10). Fig. 5 and Fig. 6), wherein the dedicated or purpose-built control circuit arrangement provides the acceleration control signal received at the acceleration control terminal Vr and the second acceleration control signal received at the second acceleration control terminal #Vr.

[0049] This shunt structure, formed from the accelerator elements 101, 102, 103, 104 connected in parallel to the switching (gate) resistors R4, R3, R1, R2, reduces the RC time constants of the RF switching transistors N4, N3, N1, N2 during switching and thus significantly reduces the switching time.

[0050] Switch 10 allows for improved switching time in RF CMOS switches. Due to the limitations of the threshold and breakdown voltage of CMOS transistors, switching transistors N4, N3, N1, and N2, typically stacked, are used to rectify large RF signals, such as high-frequency signals received at the input terminal INPUT of switch 10. The power handling capability depends on the control voltage V. c , the threshold voltage V th , the system impedance Z o and the number of stacked transistors n and can be expressed by the following equation: Pmax=n⋅(Vc+Vth)2Zo.

[0051] For a number of n = 2 stacked transistors, as in Fig. As shown in Figure 2, the equation can be expressed as follows: Pmax=2(Vc+Vth)2Zo.

[0052] For stacked transistors from one to six, equation (1) can be expressed by replacing n with the number of stacked transistors. For a higher number of stacked transistors than n = 6, parasitic capacitances to the substrate should be considered.

[0053] The drivers D1 and D2, as in Fig. As shown in Figure 2, the conversion of the switching control signal (voltage) received at the CONTROL control terminal into gate signals for the switching transistors (FETs) N4, N3, N1, and N2 with corresponding signal levels required to control the FETs is performed. A positive switching control signal (voltage) turns N3 and N4 on and (due to inverter I1) turns N1 and N2 off. A negative switching control signal (voltage) turns N3 and N4 off and turns N1 and N2 on. Turning on corresponds to a conducting state of the respective transistor, while turning off corresponds to a blocking state. The switching transistors N1 to N4 are implemented as n-channel FETs, but can also be implemented as p-channel FETs. A DC voltage is applied to the FET gates via high-value resistors.During switching, the DC voltage drop across the resistors is reduced by connecting a transistor in parallel with the switching resistors of the FETs. This connection reduces the RC time constant during switching and thus increases the voltage drop across the gates.

[0054] Typically, the (switching) control voltage received at the CONTROL terminal is selected close to the breakdown limit to minimize the number of stacked transistors and, consequently, the area of ​​the integrated circuit (IC). Gate resistors R1 to R4 have high values ​​to prevent additional loss and distortion due to insufficient RF isolation between the gates of the switching transistors (N4, N3, N1, N2) and the low-output gate drivers (D1, D2). Transistor widths in a typical RF switch are on the order of a few millimeters, resulting in a large gate bulk capacitance in the on-state, on the order of several tens of picofarads. The combination of this large parasitic capacitance and the high gate resistance values ​​(e.g.,(in the range of several tens of kilohms) and the limited drive voltage amplitude (the drivers D1, D2) result in switching times of up to a few microseconds. Switch 10 reduces the switching time and uses similar but much smaller accelerator elements 101, 102, 103, 104 in parallel with the gate resistors R4, R3, R1, R2, compared to the switching structures with stacked transistors (N4, N3, N1, N2) used to switch the RF signal, in order to avoid additional distortion of the signal in the main path. The accelerator element 101, 102, 103, 104 can also be implemented as a multi-gate NMOS transistor. An example with two switching transistors (N4, N3 and N1, N2, respectively) is shown in [reference missing]. Fig. Figure 2 shows that in switches with high linearity, a larger number of stacked transistors can be used in the main path and in parallel with the gate resistors to ensure low linearity operation.

[0055] Since the channel width and gate capacitances of the accelerator transistors (N5-N12) are relatively small compared to the channel widths of the switching transistors (N1-N4), switching the accelerator transistors (N5-N12) is faster than switching the switching transistors (N1-N4). The accelerator transistors (N5-N12) are switched on synchronously with the rising and falling edges of the main control signal (the switching control signal received at the CONTROL terminal) for a short period until the gates of the main transistors (the switching transistors N1-N4) are recharged. In the case of switching the transistors (N1-N4) in the main path (gate voltage can be changed from positive to negative), e.g.,During the rising edge of the (switching) control signal, the voltage at the accelerating transistor gates should also rise and be held high, along with the main path signal, which is high (as shown by time slice 2 in ). Fig. 3 is shown). Once the gate capacity on the main path reaches V r - V th loads (V th The threshold voltage of accelerator transistors N5-N12 switches them off. When the main path is switched off, the (switching) control voltage of accelerator transistors N5-N12 should be held high for a sufficient time after the falling edge of the (primary) switching control signal so that the accelerator transistors (N5-N12) can switch on at the falling edge of the (primary) switching control signal and switch off when the gate capacitance of the main path recharges to -V. r + V th During time slice 3, as in Fig. As shown in Figure 3, the accelerator transistors N5 - N12 are switched on.

[0056] Fig. Figure 3 shows a timing diagram of control signals for controlling a switch according to an embodiment of the invention. The figure shows timing diagrams of four control signals: a switching control signal Vctrl, a low-pass filter output signal V c1 , an acceleration control signal Vr and a second acceleration control signal #Vr. A first timing diagram shows the switching control signal Vctrl, which can be received at the switching control terminal CONTROL, as shown in Fig. 2 is shown, or that can be received at the switching control terminal 16, as shown in Fig. 1a, Fig. 1b, Fig. 1c, Fig. Figure 1d shows a second timing diagram showing a low-pass filter output signal V. c1, which corresponds to a low-pass filtered version of the switching control signal Vctrl, as shown in the first timing diagram. A third timing diagram shows the acceleration control signal Vr, which can be received at the acceleration control terminal Vr, as shown in Fig. 2 is shown, or at the control terminal 40 of the accelerator transistor 32, as in Fig. 1d is shown, or that the acceleration control signal 22 of the acceleration switch 20 can be, as in Fig. Figure 1b shows a fourth timing diagram. This diagram shows the second accelerometer control signal #Vr, which can be received at the second accelerometer control terminal #Vr, as shown in Figure 1b. Fig. 2 is shown, or at the control terminal 40 of the accelerator transistor 32, as in Fig. 1d is shown, or which can correspond to the acceleration control signal 22 of the acceleration switch 20, as in Fig. 1b is shown.

[0057] The switching control signal Vctrl exists in a first state 200 between time t and time t2, and in a second state 201 before time t1 and after time t2. The first state 200 can cause a conductive state of the switching transistors N4 and N3, and a blocked state of the switching transistors N1 and N2, as shown in Fig. Figure 2 shows that the first state 200 can cause the switching transistor 12 to be conductive, as shown in Figure 2. Fig. The second state 201 can cause a blocking state of the switching transistors N4, N3 and a conducting state of the switching transistors N1, N2, as shown in Fig. 2 is shown, or correspondingly a blocking state of the switching transistor 12, as in Fig. Figure 1a shows the low-pass filter output signal V. c1is a low-pass filtered version of the switching control signal Vctrl with a rising edge when the switching control signal Vctrl transitions to the first state, and a falling edge when the switching control signal Vctrl transitions to the second state. The rising and falling edges depend on the time constant of the low-pass filter used to filter the switching control signal Vctrl.

[0058] The acceleration control signal Vr is 200 in the first state between times t1 and t2, and additionally between t2 and t3. The third time t3 can be derived from the low-pass filter output signal V. c1 t3 is the time at which a falling edge of the low-pass filter output signal V occurs. c1A threshold V0 is crossed, as shown in the second timing diagram. The threshold V0 can be a threshold value, for example, of a Schmitt trigger circuit. The acceleration control signal Vr is in the second state 201 at time t1 and after t3. A first time slice 1 corresponds to times when the acceleration control signal Vr is in the second state 201, and time slices 2 and 3 correspond to times when the acceleration control signal Vr is in the first state 200. Time slice 2 corresponds to times when the acceleration control signal Vr is in the same state as the switching control signal Vctrl. Time slice 3 corresponds to times when the acceleration control signal Vr is in a different state than the switching control signal Vctrl.

[0059] The fourth timing diagram shows the timing of the second acceleration control signal #Vr, which is in a first state 200 at times less than t1 and at times greater than t2. The second acceleration control signal #Vr is additionally in the first state 200 between times t1 and t1 + t3, corresponding to a third time slice 3 associated with the second acceleration control signal #Vr. This time slice 3 is different from the time slice 3 associated with the acceleration control signal Vr, as shown in the third timing diagram. A second time slice 2 associated with the second acceleration control signal #Vr denotes times when the second acceleration control signal #Vr is in the same state as the inverted switching control signal Vctrl.A first time slice 1, assigned to the second acceleration control signal #Vr, denotes times when the second acceleration control signal #Vr is in the same state as the inverted switching control signal Vctrl. The first time slice 1 differs from the second time slice 2 in different states of the second acceleration control signal #Vr. The third time slice 3, assigned to the second acceleration control signal #Vr, denotes times when the second acceleration control signal #Vr corresponds to the switching control signal Vctrl such that its state is equal to the first state 200. The third time slice 3, assigned to the acceleration control signal Vr, differs from the third time slice 3, assigned to the second acceleration control signal #Vr, and depends on the switching control signal Vctrl.The third time slices 3 of both acceleration control signals Vr, #Vr represent times at which capacities of the.

[0060] Switching transistors are charged or discharged depending on the switching control signal Vctrl.

[0061] For a single-pole double-throw (SP2T) switch, as in Fig. As shown in Figure 2, both acceleration control signals are used to control the charging and discharging of the switching transistors, whereas for the single-pole single-throw (SPST) toggle switch, as shown in Figure 2, the accelerator control signals are used to control the charging and discharging of the switching transistors. Fig. 1a, Fig. 1b, Fig. 1c, Fig. Figure 1d shows that one of the acceleration control signals, e.g. the acceleration control signal Vr, is used to control the charging and discharging of the switching transistor 12.

[0062] Fig. Figure 4 shows another timing diagram of control signals for controlling a switch according to an embodiment of the invention. The figure corresponds to Fig. The number of timing diagrams and their labels are 3. A first timing diagram represents the switching control signal Vctrl, and a second timing diagram represents the low-pass filter output signal V. c1 A third timing diagram denotes the acceleration control signal Vr, and a fourth timing diagram denotes the second acceleration control signal #Vr. In contrast to Fig. 3. The switching control signal Vctrl is a periodic signal that, in the first state 200, is periodic within a first period (t1, t2) of the switching control signal and, in the second state 201, is periodic within a second signal period (t0, t1) of the switching control signal Vctrl. The low-pass filter output signal V c1is a periodic signal corresponding to a low-pass filtered version of the switching control signal Vctrl. The acceleration control signal Vr is in the first state on time slices 2, in the second state 201 on time slices 1, and additionally in the first state 200 on time slices 3, where on time slices 2 the acceleration control signal Vr, which is in the first state 200, corresponds to the switching control signal Vctrl, while on time slices 3 the acceleration control signal Vr is in the first state 200 and the switching control signal Vctrl is in the second state 201. The time slices 3, where the acceleration control signal Vr is in the second state 200, correspond to the charging and discharging times of the switching transistors to which the acceleration elements 101, 102, 103, 104 are connected, as shown in Fig. 2 is shown, connected in parallel to the switching resistors R4, R3, R1, R2 to accelerate the charging or discharging process of the switching transistors.

[0063] A fourth timing diagram shows the timing of the second switching control signal #Vr. The time slices 3 assigned to the second switching control signal #Vr do not correspond to the time slices 3 assigned to the acceleration control signal Vr.

[0064] The acceleration control signal Vr controls the switching of a corresponding acceleration element in parallel with a corresponding switching resistor. The parallel connection is maintained for a time period corresponding to time slice 3, as shown in the third timing diagram, after the switching control signal Vctrl switches from the first state 200 to the second state 201. The second acceleration control signal Vr controls the switching of a corresponding acceleration element in parallel with a corresponding switching resistor. The parallel connection is maintained for a time period corresponding to time slice 3, as shown in the fourth timing diagram, after the switching control signal Vctrl switches from the second state 201 to the first state 200.The two acceleration control signals Vr, #Vr achieve synchronous charging and discharging of the gate capacitances of the switching transistors assigned to the switching control signal Vr and the switching transistors assigned to the second acceleration control signal #Vr.

[0065] Fig. Figure 5 shows a circuit diagram of a device for controlling a switch according to an embodiment of the invention. The device 300 has a switching control terminal Vctrl to receive a switching control signal 302 and an acceleration control terminal Vr to provide an acceleration control signal 303. The device 300 further includes a low-pass filter 301, an inverter I2, a Schmitt trigger I6, and a NAND gate I3. The inverter I2 inverts the switching control signal 302 to provide an inverter output signal 304. The low-pass filter 301 has a resistor R1 connected between a low-pass filter input and a low-pass filter output, and a capacitor C1 connected between the low-pass filter output and a reference (ground) node. The low-pass filter input receives the switching control signal 302, and the low-pass filter output provides a low-pass filter output signal 305.The low-pass filter 301 low-pass filters the switching control signal 302 to provide the low-pass filter output signal 305.

[0066] The Schmitt trigger I6 converts the low-pass filter output signal 305 into a Schmitt trigger output signal 306. The Schmitt trigger I6 is an inverted Schmitt trigger. The Schmitt trigger provides the Schmitt trigger output signal 306, which is in a first state when the low-pass filter output signal 305 exceeds an upper threshold, until the low-pass filter output signal 305 falls below a lower threshold, and is in a second state when the low-pass filter output signal 305 falls below the lower threshold, until the low-pass filter output signal 305 exceeds the upper threshold.

[0067] The NAND gate I3 combines the inverter output signal 304 and the Schmitt trigger output signal 306 using a NAND logic gate to provide the acceleration control signal 303. The device 300 may have an additional input terminal In, which is connected to the switching control signal Vctrl.

[0068] The switching control signal 302 can correspond to the switching control signal Vctrl, as shown in Fig. 3 and Fig. Figure 4 shows that the acceleration control signal 303 can correspond to the acceleration control signal Vr or the second acceleration control signal #Vr, as shown in Figure 4. Fig. 3 and Fig. 4 is shown.

[0069] The device 300 can be used to receive a switching control signal from a switch, as shown in Fig. 1a, Fig. 1b, Fig. 1c, Fig. The device 300 and the switch 10 are shown in Figure 1d and are used to provide an acceleration control signal for a switch, as shown in the same figures. The device 300 and the switch 10 can be integrated into the same electronic circuit, such as the same semiconductor device, and can be manufactured using the same semiconductor processing steps. The device 300 can, for example, be implemented on a controller of an electronic circuit or a microprocessor to provide the control signals (Vr, #Vr) for the switch 10.

[0070] Fig. Figure 6 shows a circuit diagram of a device for controlling a switch according to another embodiment of the invention. The device 400 has corresponding components as the device 300, which is described in Fig. Figure 5 shows the reception of the switching control signal 302 and the delivery of the acceleration control signal 303. The low-pass filter 301 corresponds to the low-pass filter 301 shown in Fig. As shown in Figure 5, the Schmitt trigger I6 corresponds to the Schmitt trigger I6, which is shown in Fig. As shown in 5, inverter I2 corresponds to inverter I2, which is in Fig. 5 is shown, and the NAND gate I3 corresponds to the NAND gate I3 that is in Fig. 5 is shown.

[0071] Device 400 further comprises a second inverter I1 and a second NAND gate I4. Device 400 also has a second acceleration control terminal #Vr to provide a second acceleration control signal 307. The second inverter I1 inverts the Schmitt trigger output signal 306 to provide a second inverter output signal 308. The second NAND gate I4 combines the switching control signal 302 and the second inverter output signal 308 by means of a NAND gate logic gate to provide the second acceleration control signal 307.

[0072] The device 400 can be used to supply the acceleration control signal 303 and the second acceleration control signal 307 to the switch 100, as shown in Fig. Figure 2 shows that the device 400 and the switch 10 can be integrated into the same electronic component.

[0073] A method for switching a switching transistor having a switching resistor connected to a control terminal of the switching transistor includes the step of "switching an accelerator element having a resistance value less than a resistance value of the switching transistor, in parallel with the switching resistor after switching the switching transistor, until a voltage of the control terminal of the switching transistor has reached a predetermined value".

[0074] Switch 10, as it is in Fig. Figure 2 shows that the system can alternatively or additionally have acceleration elements 101, 102, 103, 104 corresponding to the acceleration elements 18, as shown in Figure 2. Fig. 1a, Fig. 1b, Fig. 1c, Fig. Figure 1d shows that the acceleration elements 18 can be arranged in stacked structures, i.e., series connections of corresponding acceleration elements 18. A stacked structure can furthermore have series connections or series circuits of an acceleration element 18, as shown in Fig. 1a, Fig. 1b, Fig. 1c and / or Fig. Figure 1d shows that the switching transistors N1-N4 can be arranged in stacked structures. The number of elements in a stacked structure of switching transistors N1-N4 can differ from the number of elements in a stacked structure of accelerator elements 101, 102, 103, 104.

[0075] The switching transistors N1-N4 and the accelerator transistors N5-N12 can be implemented as MOSFET transistors. Other embodiments of the invention feature MESFETs (metal epitaxial semiconductor field-effect transistors), HEMTs (high electron mobility transistors), or pHEMTs (pseudomorphic high electron mobility transistors) for implementing the switching transistors N1-N4 and the accelerator transistors N5-N12. Another embodiment uses JFETs (junction field-effect transistors) as the accelerator transistors N5-N12. Each type of the aforementioned switching transistors N1-N4 can be combined with each type of the aforementioned accelerator transistors N5-N12.

[0076] Using bipolar switching transistors N1-N4 and accelerator transistors N5-N12 is also a possible way to implement the switch. However, the switch implemented with the transistor types mentioned above provides improved linearity compared to an implementation using bipolar transistors.

[0077] Switch 10 can further have input terminals for implementing single-pole multi-throw switches. Devices 300 and 400 are embodiments for supplying the signals as described in Fig. 3 and Fig. Figure 4 shows that you can include other logical functional blocks for implementing the signals, as shown in Figure 4. Fig. 3 and Fig. 4 is shown.

[0078] The features described in the following claims are interchangeable. A combination of features in the dependent claims does not preclude other features described in other claims.

Claims

[1] Switch (10) which has the following features: a switching transistor (12); a switching resistor (R) that is connected between a control terminal (14) of the switching transistor (12) and a switching control terminal (16) to which a switching control signal is applied; and an accelerator element (18) having a resistance value less than the resistance value of the switching resistor (R), wherein the accelerator element (18) is adapted to be switched in parallel with the switching resistor (R) for a predetermined time period by an accelerator control signal (22) having signal states to switch the accelerator element (18) on or off when the switching transistor (12) switches from a blocking state to a conducting state or when the switching transistor (12) switches from the conducting state to the blocking state, until a voltage at the control terminal (14) of the switching transistor (12) reaches a predetermined value. [2] Switch (10) according to claim 1, wherein the switching transistor (12) is adapted to be switched by the switching control signal at the switching control terminal (16), and the acceleration control signal (22) is supplied to switch the acceleration element (18) in parallel with the switching resistor (R) for the predetermined time period after a switching control signal transition between two states of the switching control signal. [3] Switch (10) according to claim 2, wherein the predetermined time period depends on an RC time constant of a circuit comprising the switching transistor (12), the switching resistor (R) and the accelerator element (18). [4] Switch (10) according to claim 2 or 3, wherein the switching control signal has a first signal state which causes a conductive state of the switching transistor (12) and a second signal state which causes a blocking state of the switching transistor (12); the acceleration control signal (22) has a first signal state which switches the acceleration element (18) in parallel with the switching resistor (R) during the predetermined time period after a transition of the switching control signal between the first and the second state. [5] Switch (10) according to claim 4, wherein the acceleration control signal (22) is adapted to change a second signal state which disconnects the acceleration element (18) from the switching resistor (R) in response to the elapsed predetermined time period. [6] Switch (10) according to any one of claims 1 to 5, further comprising an acceleration switch which is controlled by the acceleration control signal (22) and adapted to switch the acceleration element (18) in parallel with the switching resistor (R). [7] Switch (10) according to claim 6, wherein the accelerator element (18) has an accelerator resistor which is connected between the control terminal (14) of the switching transistor (12) and the switching control terminal (16). [8] Switch (10) according to any one of claims 1 to 7, wherein the accelerator element (18) has a diode (30) which is connected between the control terminal (14) of the switching transistor (12) and the switching control terminal (16), wherein the diode (30) is adapted to be controlled by the accelerator control signal (22). [9] Switch (10) according to any one of claims 1 to 8, wherein the accelerator element (18) has an accelerator transistor having a first terminal connected to the control terminal (14) of the switching transistor (12), a second terminal connected to the switching control terminal (16), and a control terminal, wherein the control terminal is adapted to receive the accelerator control signal (22). [10] Switch (10) according to claim 9, wherein the accelerator transistor has a channel width that is smaller than a channel width of the switching transistor (12). [11] Switch (10) according to any one of claims 1 to 10, wherein the accelerator element (18) has a plurality of accelerator transistors connected in series between the control terminal (14) of the switching transistor (12) and the switching control terminal (16), wherein the control terminals of the plurality of accelerator transistors are adapted to receive the accelerator control signal (22). [12] Switch (10) according to claim 11, comprising the following features: a plurality of switching transistors connected in series; and a plurality of switching resistors, wherein each of the switching resistors is assigned to one of the plurality of switching transistors; where each of a plurality of acceleration elements is assigned to one of the switching resistors. [13] Switch (10) according to claim 12, comprising the following features: an input terminal and an output terminal, wherein the majority of the switching transistors are connected between the input terminal and the output terminal; a further switching transistor that is connected between the output terminal and a reference terminal with respect to the channel terminals of the further switching transistor; a further switching resistor, which is connected between a control terminal of the further switching transistor and a further switching control terminal; and a further accelerator element having a resistance value smaller than the resistance value of the further switching resistor, wherein the further accelerator element is adapted to be connected in parallel with the further switching resistor, after the further switching transistor has been switched, until a voltage at the control terminal of the further switching transistor has reached a predetermined value. [14] Switch (10) according to claim 13, comprising the following features: a plurality of additional switching transistors; a plurality of further switching resistors, each assigned to one of the plurality of further switching transistors; and a plurality of further acceleration elements, each of which is assigned to one of the plurality of further switching resistors. [15] Switch (10) according to claim 13 or 14, wherein the further switching transistor is adapted to be switched by a switching control signal at the further switching control terminal, and a further acceleration control signal is supplied to switch the further acceleration element in parallel with the further switching resistor for a second predetermined time period, after a switching control signal transition between two states of the switching control signal. [16] Switch (10) according to claim 15, wherein the second predetermined time period depends on an RC time constant of a circuit comprising the further switching transistor, the further switching resistor and the further accelerator element. [17] Switch (10) according to claim 15 or 16, wherein the switching control signal has a first signal state that causes a conductive state of the further switching transistor and a second signal state that causes a blocking state of the further switching transistor; wherein the further acceleration control signal has a first signal state that switches the further acceleration element in parallel with the further switching resistor during the second predetermined time period, following a transition of the switching control signal between the first and the second state. [18] Switch (10) according to claim 17, wherein the further acceleration control signal is adapted to change a second signal state, which separates the further acceleration element from the further switching resistor, in response to the elapsed time of the second predetermined period. [19] Switch (10) according to any one of claims 1 to 18, wherein the switching transistors and the accelerator transistor comprise CMOS-FETs or wherein the accelerator transistor comprises a JFET. [20] Switch (10) having the following features, an input port; an output port a switching control connection (16); a first switching transistor (N3, N4) that is connected between the input terminal and the output terminal; a first switching resistor (R3, R4) that is connected between a control terminal of the first switching transistor (N3, N4) and the switching control terminal (16) to which a switching control signal is applied; a first accelerator element (101, 102) which has a resistance value that is smaller than a resistance value of the first switching resistor (R3, R4); a second switching transistor (N1, N2) that is connected between a reference terminal and the output terminal; a second switching resistor (R1, R2) connected between a control terminal of the second switching transistor (N1, N2) and the switching control terminal (16); and a second accelerator element (103,104) which has a resistance value that is smaller than a resistance value of the second switching resistor (R1, R2), wherein the first and second accelerator elements (101 - 104) are adapted to be switched in parallel with the first and second switching resistors (R1 - R4) for a predetermined time period when the first switching transistor (N3, N4) switches from a blocking state to a conducting state or when the first switching transistor (N3, N4) switches from the conducting state to the blocking state, and the second switching transistor (N1, N2) switches from a blocking state to a conducting state or when the second switching transistor (N1, N2) switches from the conducting state to the blocking state, by an accelerator control signal having signal states to switch the first and second accelerator elements (101 - 104) on or off, until voltages at the control terminal of the first and second switching transistors (N1 - N4) have reached corresponding predetermined values. [21] Switch (10) according to claim 20, wherein the first switching transistor (N3, N4), the second switching transistor (N1, N2), the first accelerator element (101, 102) and the second accelerator element (103, 104) have a plurality of FETs connected in series; where the channel width of the FETs of the first and second accelerator element (101 - 104) is smaller than the channel width of the FETs of the first and second switching transistors N1 - N4), and in which the first and second acceleration elements (101 - 104) are connected in parallel to the corresponding switching resistors (R1 - R4), responding to a first acceleration control signal and a second acceleration control signal; in which the first and second acceleration control signals transition to a first state, responding to a transition of the switching control signal at the switching control terminal (16) between a first state and a second state, wherein the first state of the first and second acceleration control signals causes a parallel connection of the acceleration element (101 - 104) to the corresponding switching resistors (R1 - R4); and where the first and second acceleration control signals are in the first state during the first and second predetermined time periods after the transition of the switching control signals remain, with the time periods being determined by an RC constant of a circuit that includes the corresponding switching transistors (N1 - N4), the corresponding switching resistors (R1 - R4) and the corresponding accelerator elements (101 - 104). [22] Switch (10) according to claim 20 or 21, comprising a control unit adapted to receive the switching control signal and to supply an acceleration control signal, wherein the control unit comprises the following features: an inverter adapted to invert the switching control signal in order to provide an inverter output signal; an RC low-pass filter adapted to low-pass filter the switching control signal in order to provide a low-pass filter output signal; a Schmitt trigger circuit adapted to convert the low-pass filter output signal into a Schmitt trigger circuit output signal; and a NAND gate adapted to combine the inverter output signal and the Schmitt trigger circuit output signal through a logical NAND combination to provide the acceleration control signal. [23] Switch (10) according to claim 22, wherein the control has the following features: a second inverter adapted to invert the Schmitt trigger circuit output signal to provide a second inverter output signal; and a second NAND gate adapted to combine the switching control signal and the second inverter output signal through a logical NAND combination to provide a second acceleration control signal. [24] Method for switching a switching transistor (12) having a switching resistor (R) connected to a control terminal of the switching transistor (12), the method comprising the following steps: Switching an accelerator element (18) having a resistance value less than the resistance value of the switching resistor (R) in parallel with the switching resistor (R) when switching the switching transistor (12) when the switching transistor (12) changes from a blocking state to a conducting state or when the switching transistor (12) changes from the conducting state to the blocking state, for a predetermined time period until a voltage at the control terminal of the switching transistor (12) reaches a predetermined value, wherein the acceleration element (18) is switched by an acceleration control signal (22) which has signal states for switching the acceleration element (18) on or off. [25] Switch (10) which has the following features, an input port; an output port a switching control connection (16); a first switching transistor (N3, N4) that is connected between the input terminal and the output terminal; a first switching resistor (R3, R4) that is connected between a control terminal of the first switching transistor (N3, N4) and the switching control terminal (16); a first accelerator element (101, 102) which has a resistance value that is smaller than a resistance value of the first switching resistor (R3, R4); a second switching transistor (N1, N2) that is connected between a reference terminal and the output terminal; a second switching resistor (R1, R2) connected between a control terminal of the second switching transistor (N1, N2) and the switching control terminal (16); and a second accelerator element (103, 104) which has a resistance value that is smaller than a resistance value of the second switching resistor (R1, R2), wherein the first and second accelerator elements (101 - 104) are adapted to be connected in parallel to the first and second switching resistors (R1 - R4) respectively, after switching the first and second switching transistors (N1 - N4), until voltages at the control terminal of the first and second switching transistors (N1 - N4) have reached corresponding predetermined values; wherein the switch has a controller adapted to receive a switching control signal and to supply an acceleration control signal, wherein the controller has the following features: an inverter adapted to invert the switching control signal in order to provide an inverter output signal; an RC low-pass filter adapted to low-pass filter the switching control signal in order to provide a low-pass filter output signal; a Schmitt trigger circuit adapted to convert the low-pass filter output signal into a Schmitt trigger circuit output signal; and a NAND gate adapted to combine the inverter output signal and the Schmitt trigger circuit output signal through a logical NAND combination to provide the acceleration control signal.

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