Semiconductor chip and methods for manufacturing semiconductor chips

Abstract

semiconductor chip (3) comprising a semiconductor body (4) with a sequence of semiconductor layers (400) and a support (1) with a first principal surface (11) and a second principal surface (12) opposite the first principal surface, wherein - the semiconductor body (4) is arranged on the first main surface (11) of the support (1) and a diode structure (2) is formed between the first main surface (11) and the second main surface (12), which electrically isolates the first main surface (11) from the second main surface (12) at least for one polarity of an electrical voltage; - the diode structure (2) is fully formed in the support (1); - the semiconductor layer sequence (400) has an active region (40) intended for generating radiation; - the semiconductor layer sequence (400) is electrically isolated from the second main surface (12) by means of the diode structure (2); and - in the carrier a protective diode (18) is formed between the first main surface and the diode structure.

Description

[0001] The present application relates to a semiconductor chip with a support formed from a substrate and to a method for manufacturing semiconductor chips.

[0002] Documents US 2006 / 0261356A1, US 2006 / 0056123A1, US 2009 / 0218598A1 and US 2005 / 0242358A1 disclose a substrate and a method for manufacturing semiconductor chips.

[0003] In optoelectronic semiconductor chips such as LEDs, it may be desirable, for example, for individual control of the semiconductor chips, to electrically insulate the radiation-emitting area from the mounting element to which the semiconductor chips are attached. However, electrical insulators often also have a comparatively low thermal conductivity, so that such a material between the radiation-emitting area and the mounting element hinders efficient dissipation of the heat generated during operation. This can lead to performance losses and / or a reduced lifespan.

[0004] One challenge is to achieve efficient heat dissipation while simultaneously providing electrical insulation. Furthermore, a method for the simple and reliable production of efficient semiconductor chips should be presented.

[0005] This task is solved by the subject matter of the independent patent claims. Further developments and refinements are the subject matter of the dependent patent claims.

[0006] One embodiment is based on a support substrate for a sequence of semiconductor layers, comprising a first main surface and a second main surface opposite the first main surface. A diode structure is formed between the first main surface and the second main surface, electrically isolating the first main surface from the second main surface at least for one polarity of an electrical voltage.

[0007] In other words, the diode structure prevents at least unidirectional electric current flow in a direction perpendicular to the first main surface.

[0008] Advantageously, the support substrate is designed such that, at least with respect to one polarity, there is no electric current path through the support substrate connecting any point on the first main surface and any point on the second main surface.

[0009] The diode structure is formed across the entire surface of the substrate, particularly in a plane running parallel or substantially parallel to the first main surface. Viewed from above, the diode structure is therefore unstructured and extends over the entire lateral extent of the substrate.

[0010] The substrate is designed for the application or formation of a semiconductor layer sequence during the production of multiple semiconductor chips, particularly before singulation into individual chips. The diode structure electrically isolates the semiconductor layer sequence located on the first main surface of the substrate from the second main surface.

[0011] In a preferred embodiment, the diode structure isolates the first main surface from the second main surface for both polarities, in particular across the entire surface. The electrical isolation is therefore bidirectional and independent of the polarity of the electrical voltage.

[0012] In a further preferred embodiment, the diode structure comprises a first diode and a second diode. The first diode and the second diode are advantageously arranged vertically one above the other. The first diode and the second diode are preferably oriented oppositely to each other with respect to their forward direction.

[0013] In a further preferred embodiment, the support substrate contains a preferably single-crystal semiconductor material. Semiconductor materials are characterized by a comparatively high thermal conductivity. Silicon, germanium, or gallium arsenide are particularly suitable.

[0014] In a preferred further development, the diode structure is formed by layer-wise doping of the support substrate. In this context, layers of the support substrate are generally understood to be regions of the support substrate that are arranged vertically above one another.

[0015] Preferably, the diode structure comprises at least two layers with different conductor types. A pn ​​junction as a diode is thus easily implemented.

[0016] For the electrical isolation of the first main surface from the second main surface, the diode structure can, in principle, be arranged at any point in the vertical direction. The diode structure can therefore be vertically spaced from the first main surface and / or from the second main surface.

[0017] Furthermore, one of the doped layers of the diode structure can be directly adjacent to the first or the second main surface of the substrate. For example, a doped layer adjacent to the first main surface can also be intended for electrical contacting.

[0018] In a preferred embodiment, the diode structure comprises at least three successive layers, alternating with respect to their conduction type, for example, in the form of a pnp or npn layer sequence. Two pn junctions connected in series with opposite forward bias directions are thus easily implemented. The doped layers of the diode structure can be directly adjacent to one another. Furthermore, increasing the number of diodes in the vertical direction can increase the reverse breakdown field strength.

[0019] At least one layer of the support substrate can be nominally undoped. In particular, a nominally undoped layer can be arranged between at least two of the doped layers, such that these doped layers are spaced apart from each other.

[0020] A protective diode is integrated into the substrate. This protective diode shields a semiconductor chip with such a substrate from damage caused by electrostatic discharge (ESD). The protective diode is positioned between the first main surface and the diode structure.

[0021] An optoelectronic semiconductor chip comprises a semiconductor body with a sequence of semiconductor layers and a substrate with a first main surface and a second main surface opposite the first main surface. The semiconductor body is located on the first main surface of the substrate. A diode structure is formed between the first and second main surfaces, electrically isolating the first main surface from the second main surface for at least one polarity of an electrical voltage.

[0022] The semiconductor layer sequence includes an active region designed to generate coherent, partially coherent, or incoherent radiation. The semiconductor chip can be configured, in particular, as a light-emitting diode (LED) or a laser diode. Alternatively or additionally, the semiconductor chip can also be configured as a radiation receiver.

[0023] Heat generated during the operation of the semiconductor chip can be dissipated via the substrate. Furthermore, the active area is electrically isolated from the electrical potential applied to the second main surface of the substrate by means of the junction.

[0024] The semiconductor layer sequence of the semiconductor body is preferably epitaxially deposited on a growth substrate, for example by means of MOCVD or MBE.

[0025] In one embodiment, the carrier serves as the growth substrate for the semiconductor layer sequence.

[0026] In an alternative embodiment, the support is different from the growth substrate. The support serves primarily to mechanically stabilize the semiconductor layer sequence, so that the growth substrate is no longer required and can be removed.

[0027] A semiconductor chip with the growth substrate removed is also called a thin-film semiconductor chip. A thin-film semiconductor chip, especially a thin-film LED chip, is characterized by the following features: - a reflective layer is applied or formed on a first main surface of a radiation-generating epitaxial layer sequence facing the support, which reflects at least some of the electromagnetic radiation generated in the epitaxial layer sequence back into it; - the epitaxial layer sequence has a thickness in the range of 20 µm or less, particularly in the range of 10 µm; and - the epitaxial layer sequence contains at least one semiconductor layer with at least one surface that has a mixing structure which ideally leads to an approximately ergodic distribution of light in the epitaxial layer sequence, i.e. it exhibits a scattering behavior that is as ergodic and stochastic as possible.

[0028] A basic principle of a thin-film light-emitting diode chip is described, for example, in I. Schnitzer et al., Appl. Phys. Lett. 63 (16), October 18, 1993, 2174 - 2176, the disclosure content of which is hereby incorporated by reference.

[0029] A thin-film LED chip is, to a good approximation, a Lambertian surface emitter and is therefore particularly well suited for use in a headlight.

[0030] The substrate is preferably metallurgically bonded to the semiconductor layer sequence. In a metallurgical bond, the bonding partners, preferably prefabricated, are held together by atomic and / or molecular forces. A metallurgical bond can be achieved, for example, by means of a bonding layer, such as an adhesive layer or a solder layer. As a rule, separation of the bond is accompanied by the destruction of the bonding layer and / or at least one of the bonding partners.

[0031] In a preferred embodiment, one side surface of the substrate is provided with a passivation layer. This prevents the risk of unintended electrical bridging of the diode structure, for example, due to solder or an electrically conductive adhesive during the assembly of the semiconductor chip. Furthermore, the passivation layer is preferably opaque, and in particular absorbent, to electromagnetic radiation, especially radiation with an energy above the substrate's band gap energy, such as radiation in the infrared, visible, and / or ultraviolet spectral range. This prevents or at least reduces an unintended reduction in the electrical resistance of the diode structure due to radiation-induced photoconductivity. Alternatively, the side surface of the substrate can be left exposed. This simplifies the substrate's fabrication.

[0032] In a process for manufacturing a plurality of semiconductor chips, a substrate is provided with a first main surface and a second main surface opposite the first. A diode structure is formed between the first and second main surfaces, the diode structure electrically isolating the first main surface from the second main surface for at least one polarity of an electrical voltage. A protection diode is formed in the substrate, positioned between the first main surface and the diode structure.

[0033] A sequence of semiconductor layers is arranged on the first main surface of the substrate. This sequence of semiconductor layers is electrically isolated from the second main surface of the substrate by means of the diode structure.

[0034] The substrate containing the semiconductor layers is separated into a plurality of semiconductor chips. During separation, a carrier for each semiconductor chip is created from the substrate, on which a semiconductor body is arranged.

[0035] In one embodiment, the diode structure is formed before singulation, in particular before the arrangement of the semiconductor layer sequence. The semiconductor chips therefore already exhibit the diode structure at the singulation stage.

[0036] In an alternative design variant, the diode structure is formed only after singulation. This allows only those semiconductor chips to be selectively provided with a diode structure where the semiconductor layer sequence is to be electrically isolated from the second main surface of the substrate.

[0037] In a preferred embodiment, the diode structure is formed by doping the entire surface of the substrate. This can be achieved, for example, by alloying, diffusion, or implantation. For this full-surface doping, a photolithographic masking process for lateral structuring, for example, is unnecessary.

[0038] In one embodiment, the semiconductor layer sequence is deposited on a growth substrate, and the growth substrate is removed after the layers have been arranged on the support substrate.

[0039] In an alternative embodiment, the semiconductor layer sequence is epitaxially deposited onto the support substrate. The support substrate thus serves as the growth substrate.

[0040] The described substrate is particularly suitable for the process. Furthermore, the process is especially suitable for manufacturing a described semiconductor chip. Features implemented in connection with the substrate or the semiconductor chip can therefore also be used for the process, and vice versa.

[0041] Further features, advantageous designs and practical applications will become apparent from the following description of the exemplary embodiments in conjunction with the figures.

[0042] They show: Fig. 1 A first embodiment of a support substrate in schematic sectional view; the Fig. 2, Fig. 3 and Fig. 4 a first, second and third embodiment of a semiconductor chip with a carrier, each in schematic sectional view; the Fig. 5A and Fig. 5B a section of a second embodiment of a support substrate in schematic top view ( Fig. 5A) and associated sectional view ( Fig. 5B); Fig. 6 A fourth embodiment of a semiconductor chip in schematic sectional view; the Fig. 7 and Fig. 8 a first and second embodiment of a component in schematic sectional view; and the Fig. 9A to 9C show an embodiment of a method for manufacturing a plurality of semiconductor chips using intermediate steps shown schematically in sectional view.

[0043] Identical, similar, or similarly effective elements in the figures are marked with the same reference symbols. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements may be exaggerated for clarity and / or better understanding.

[0044] A first embodiment of a carrier substrate is described in Fig. Figure 1 shows a schematic sectional view. The support substrate 10 extends in a vertical direction between a first main surface 11 and a second main surface 12 running parallel to the first main surface.

[0045] A diode structure 2 is formed between the main surfaces, extending across the entire surface of the support substrate 10 in a lateral direction.

[0046] The diode structure 2 comprises a first layer 21, a second layer 22, and a third layer 23. The first layer forms the first main surface of the substrate. The first layer 21 and the third layer 23 are each doped with p-type diodes, and the second layer 22 is doped with n-type diodes. A first diode 24 and a second diode 25 are formed by means of the pn junctions between these layers. The diodes 24 and 25 are oriented oppositely to each other with respect to their forward direction. The remaining part of the substrate 10 can be doped or undoped.

[0047] By means of the diode structure 2, the first main surface 11 and the second main surface 12 are electrically isolated from each other, the electrical isolation by means of the diodes 24, 25 being independent of the polarity of an applied electrical voltage.

[0048] The support substrate 10 is preferably based on a semiconductor material. Silicon, germanium, or gallium arsenide are suitable examples.

[0049] In the described embodiment, the diode structure is formed by means of a sequence of directly adjacent layers alternating with respect to the conductor type. Alternatively, a nominally undoped layer can be arranged between at least two doped layers. Furthermore, the diode structure can also comprise more than two diodes, which are expediently connected in series.

[0050] A first embodiment of a semiconductor chip, exemplified as an LED semiconductor chip, is described in Fig. Figure 2 is shown in a schematic sectional view. The semiconductor chip 3 has a support 1 which, during the manufacture of the semiconductor chip 3, is formed from a support substrate, as described in connection with Fig. 1 is described and executed.

[0051] The semiconductor chip 3 has a semiconductor body 4. A sequence of semiconductor layers forming the semiconductor body includes an active region 40 intended for generating radiation, which is arranged between a first semiconductor layer 41 and a second semiconductor layer 42.

[0052] A growth substrate for the epitaxial semiconductor body 4 has been removed and is therefore in Fig. 2 not shown. The semiconductor chip 3 is therefore designed as a thin-film semiconductor chip in which the diode structure 2 is integrated into the support 1 of the thin-film semiconductor chip.

[0053] The semiconductor body 4 is mechanically and electrically connected to the first main surface 11 of the support by means of a connecting layer 6, for example a solder layer or an adhesive layer.

[0054] During operation of the semiconductor chip 3, charge carriers can be injected from different sides into the active area 40 by applying an external electrical voltage between a first contact 51 and a second contact 52 of the semiconductor chip 3, and recombine there with the emission of radiation.

[0055] The first contact 51 is formed on the first main surface 11 of the support 2, so that the charge carriers are injected into the semiconductor body 4 via the first layer 21 of the support 1. Thus, by means of the diode structure 2, electrical insulation can be achieved from the second main surface 12 of the support despite a current flowing through the support 1.

[0056] Furthermore, the carrier 1 is characterized by a high thermal conductivity, especially in comparison to a carrier made of an electrically insulating material such as sapphire, so that the waste heat generated in the semiconductor body 4 during operation of the semiconductor chip 3 can be efficiently dissipated from the semiconductor body.

[0057] A reflective layer 7 is arranged between the semiconductor body 4 and the support 1. The preferably metallic reflective layer is designed to reflect radiation generated in the active region and emitted towards the support 1, so that this radiation component can exit through a radiation exit surface 45 of the semiconductor body 4 facing away from the support 1. For example, silver or aluminum are suitable for the reflective layer 7 in the visible spectral range, while gold exhibits high reflectivity in the infrared spectral range.

[0058] In this embodiment, a side surface 13 of the carrier, which bounds the carrier 1 in a later direction, is exposed. Therefore, a coating of the side surface 13 created during the singulation of the carrier substrate is not required. However, to protect against an unintended electrical bridge across the diode structure 2 during the assembly of the semiconductor chip 3, a coating, for example in the form of a passivation layer, can be provided.

[0059] The in Fig. The second embodiment of a semiconductor chip shown in section 3 essentially corresponds to the one described in connection with Fig. 2 described in the first embodiment. In contrast, the carrier 1 has a diode structure 2 with only one diode. With respect to its forward bias, the diode is configured such that it is reverse-biased when an operating voltage is applied to contacts 51, 52. Electrical isolation of the first main surface 11 from the second main surface 12 of the carrier 1 is thus ensured with respect to one polarity. Furthermore, unlike in the first embodiment, the first contact 51 is arranged on the first semiconductor layer 41. The injection of charge carriers from the first contact into the first semiconductor layer can therefore occur independently of the carrier 1.

[0060] A third embodiment of a semiconductor chip is described in Fig. 4 shown in a schematic sectional view. In contrast to the ones related to the Fig. 2 and Fig. In the embodiments described in Figure 3, the support 1 forms the growth substrate for the semiconductor layers of the semiconductor body 4. The semiconductor body is therefore not metallurgically bonded to the support 1, but epitaxially deposited on the support. To increase the radiant power emitted from the radiation exit surface 45, a mirror can be formed in the semiconductor body 4, for example in the form of a Bragg mirror (not explicitly shown).

[0061] In the Fig. 5A and Fig. Figure 5B shows a section of a support substrate according to a second embodiment. The section corresponds to a region of the support substrate 10 that serves as a support for a semiconductor body. Advantageously, the support substrate has a plurality of such regions, preferably arranged in a matrix.

[0062] The substrate 10 has a protection diode 18 in addition to the diode structure 2. The protection diode is formed between the first main area 11 and the diode structure 2 in the substrate 10. The protection diode 18 is formed by a first sub-area 181 and a second sub-area 182. The sub-areas differ in their conductor type, so that a pn junction is formed between the sub-areas. The second sub-area 182 is completely surrounded by the first sub-area 181.

[0063] An insulating layer 17 is formed on the first main surface 11. The insulating layer can, for example, contain or consist of an oxide, such as silicon oxide, a nitride, such as silicon nitride, or an oxynitride, such as silicon oxynitride. The insulating layer 17 has a first opening 191 and a second opening 192. Looking at the support substrate 10, the first opening 191 overlaps the first sub-area 181, and the second opening 192 overlaps the second sub-area 182. A first contact surface 15 and a second contact surface 16 are arranged on the insulating layer and are electrically connected through the openings to the second sub-area 182 and the first sub-area 181, respectively.

[0064] The diode structure 2 borders the second main surface 12 of the support substrate 10. Alternatively, the diode structure can also be spaced away from the second main surface.

[0065] An embodiment of a semiconductor chip in which the support consists of a support substrate according to the one described in connection with the Fig. 5A and Fig. The embodiment described in 5B is carried out in Fig. 6 shown. As in connection with Fig. As described in Figure 2, the semiconductor body 4 is attached to the substrate 1 by means of a connection layer 6. The semiconductor body 4 has a recess 47 that extends from the substrate 1 through the first semiconductor layer 41 and the active region 40 into the second semiconductor layer 42. To prevent an electrical short circuit of the active region 40, one side of the recess 47 is covered by an insulating layer 48. A first connection layer 43 is arranged between the semiconductor body 4 and the substrate 1. This first connection layer 43 adjoins the first semiconductor layer 41 facing the substrate and is electrically connected to it. A first contact 51 of the semiconductor chip 3 is arranged on the first connection layer 43. The second semiconductor layer 42 is electrically connected to a second connection layer 44 that extends through the recess 47.

[0066] The first connection layer 43 extends in certain areas between the semiconductor body 4 and the second connection layer 44. An insulating layer 48 is formed between the connection layers 43 and 44 to prevent an electrical short circuit. A second contact 52 is formed on the second connection layer 44. The semiconductor chip 3 is thus electrically connected by means of two electrical contacts 51 and 52 spaced laterally from the semiconductor body 4. The radiation emission surface 45 of the semiconductor body is free of electrical contacts, thus preventing any shadowing of the radiation emission surface.

[0067] To increase the emitted radiation power, the radiation exit surface 45 is provided with a structure 46, for example a roughening.

[0068] Contacts 51 and 52 remain connected to the protection diode 18. The active region 40 and the protection diode 18 are connected antiparallel to each other with respect to their forward bias. For example, the second semiconductor layer 42 adjacent to the second contact 52 can be n-type and the first subregion 181 p-type, or vice versa. In the event of a reverse bias voltage applied to the active region 40, charge carriers can flow away via the protection diode. Thus, a protection diode is integrated into the semiconductor chip 3, in particular into the carrier 1 as part of the semiconductor chip, which protects the semiconductor body from damage by electrostatic discharge.

[0069] The first contact 51 is connected to the second sub-area 182 of the protection diode 18 via the first connection layer 43, the interconnection layer 6, and the first contact surface 15. The second contact 52 is electrically connected to the first sub-area 181 of the protection diode 18 via the second connection layer 44, the interconnection layer 6, and the second contact surface 16. To prevent an electrical short circuit, a gap 85 is formed between a sub-layer 431 connected to the first connection layer 43 and the second connection layer 44.

[0070] The side surfaces 13 of the carrier 1 are provided with a passivation layer 8. This reduces the risk of an electrical short circuit of the diode structure 2 during the assembly of the semiconductor chip 3, for example, using solder or an electrically conductive adhesive. Furthermore, the passivation layer is opaque to radiation, in particular absorbing radiation, so that a reduction in the electrical resistance of the diode structure 2 due to radiation-induced photoconductivity can be avoided or at least reduced. One of the materials mentioned in connection with the insulating layer 17 is particularly suitable for the passivation layer. For example, silicon nitride can exhibit a comparatively low transmission for radiation in the ultraviolet and visible spectral ranges.The passivation layer 8 can of course also be provided in a semiconductor chip according to the further described embodiments.

[0071] A first embodiment of a component is shown in Fig. Figure 7 is shown in a schematic sectional view. The semiconductor chip 3 of the component 9 can be designed in particular as described in connection with the previously described embodiments.

[0072] The surface-mount device (SMD) 9 has a housing 90 that encloses a conductor frame with a first terminal 91 and a second terminal 92. The housing can, for example, be designed as a molded plastic body.

[0073] The housing body 90 further forms a thermal connection conductor 93. The thermal connection conductor 93 can, for example, contain a metal, such as copper. The semiconductor chip 3 is mounted on the thermal connection conductor. The contacts 51, 52 of the semiconductor chip 3 are electrically connected to the connection conductors 91, 92 via connecting conductors 94, for example, wire bonds. As an alternative to wire bonds, a contact method can also be used, for example, by means of solder balls, vias, a planar, layered contact structure, or so-called castellations.

[0074] The semiconductor chip 3 is laterally surrounded by a suitably electrically insulating reflector layer 98, for example made of a plastic containing reflective particles, such as titanium oxide particles, such as an epoxy or a silicone. This further increases the total radiant power emitted from the radiation emission surface 45 of the semiconductor chip. Furthermore, the reflector layer prevents photons coupled into the substrate 1 from outside the semiconductor chip from increasing the conductivity in the diode structure 2 and thus impairing the electrical insulation provided by the diode structure.

[0075] The housing body 90 is arranged on a mounting plate 95, which has connection areas 96. The mounting plate can be designed, for example, as a printed circuit board (PCB) or as a metal core printed circuit board (MCPCB).

[0076] The connecting conductors 91 and 92 are each electrically connected to a connecting area 96. The thermal connecting conductor 93 can also be connected to a connecting area. This improves the dissipation of heat loss to the environment. Unlike the connecting conductors 91 and 92, the thermal connecting conductor 93 and the adjacent connecting area do not serve for the electrical contacting of the semiconductor chip 3, but rather for efficient heat dissipation from the semiconductor chip. The active area of ​​the semiconductor chip 3, intended for generating radiation, is electrically isolated from the mounting plate 95 by means of the diode structure 2.

[0077] A second embodiment of a component is shown in Fig. Figure 8 is shown schematically in sectional view. In contrast to the first embodiment, the component 9 is designed as a module in which a plurality of semiconductor chips 3 are attached to the mounting plate 95 without a housing.

[0078] For electrical isolation of the connection areas 96, an insulating layer 97 is formed between the mounting plate 95 and the connection areas 96. The insulating layer 97 ensures that the semiconductor chips 3 can be individually electrically connected even on an electrically conductive mounting plate, such as a metal plate. Alternatively, the semiconductor chips can be at least partially electrically interconnected, for example in a parallel or series connection.

[0079] In contrast, the semiconductor chips 3 can be attached directly to the mounting plate 95, since the electrical insulation of the active areas of the semiconductor chips is ensured by the diode structure 2 of the semiconductor chips. An insulating layer between the semiconductor chips and the mounting plate is therefore unnecessary, thus reducing thermal resistance and improving heat dissipation from the semiconductor chip.

[0080] An embodiment of a method for manufacturing semiconductor chips is described in the Fig. 9A to 9C are shown using schematically depicted intermediate steps in a sectional view, with an example being the production of a semiconductor chip, which, as in connection with Fig. 2 is described and executed.

[0081] As in Fig. Figure 9A shows a support substrate 10 having a diode structure 2. For the sake of simplicity, only a portion of the support substrate 10 is shown, from which exactly one support for a semiconductor chip is produced during manufacturing.

[0082] A semiconductor layer sequence 400 with an active region 40 intended for generating radiation, which is arranged between a first semiconductor layer 41 and a second semiconductor layer 42, is epitaxially deposited on a growth substrate 49, for example by means of MOVPE or MBE.

[0083] The formation of the diode structure 2 is achieved by doping the entire surface of the support substrate 10. The doped layers of the support substrate 10 can be produced, for example, by alloying, diffusion and / or implantation.

[0084] As in Fig. As shown in Figure 9B, the semiconductor layer sequence 400 is mechanically stably connected to the support substrate 10 by means of a bonding layer 6. After fixation, the support substrate serves to mechanically stabilize the semiconductor layer sequence, so that the growth substrate for the semiconductor layer sequence can be removed. This can be done, for example, by coherent radiation, such as using a laser lift-off process, mechanically, such as by grinding, lapping or polishing, or chemically, such as by wet or dry chemical etching.

[0085] To electrically contact the first semiconductor layer 41, the semiconductor layer sequence is partially removed, exposing the first main surface 11 of the support substrate 10. The electrical contacts 51, 52 can be applied, for example, by vapor deposition or sputtering.

[0086] For singulation in semiconductor chips, the semiconductor layer sequence 400 is cut together with the substrate 10, resulting in semiconductor chips 3, each comprising a semiconductor body 4 and a substrate 1. Singulation can be achieved, for example, by coherent radiation, such as a laser cutting process; mechanically, such as by sawing, breaking, or splitting; or chemically, such as by wet or dry chemical etching. A completed semiconductor chip is in Fig. 9C shown.

[0087] In contrast to the described embodiment, the formation of the diode structure 2 can also take place only after the semiconductor layer sequence 400 has been arranged on the substrate 10. In particular, the diode structure can also be formed only after the semiconductors have been isolated in semiconductor chips. In this way, the diode structure can only be formed in semiconductor chips where the semiconductor body 4 is to be electrically insulated from the second main surface 12 of the substrate 1. Furthermore, the substrate 10 can also serve as a growth substrate for the semiconductor layer sequence 400. In this case, a transfer to a different substrate is unnecessary.

[0088] With the described method, the semiconductor bodies 4 of the semiconductor chips can be electrically isolated from a mounting surface for the semiconductor chips by forming the diode structure, without significantly increasing the thermal resistance, since, for example, the electrically insulating depletion zone in a pn junction only causes a slight reduction in thermal conductivity.

Claims

[1] Semiconductor chip (3) comprising a semiconductor body (4) with a sequence of semiconductor layers (400) and a support (1) comprising a first principal surface (11) and a second principal surface (12) opposite the first principal surface, wherein - the semiconductor body (4) is arranged on the first main surface (11) of the support (1) and a diode structure (2) is formed between the first main surface (11) and the second main surface (12), which electrically isolates the first main surface (11) from the second main surface (12) at least for one polarity of an electrical voltage; - the diode structure (2) is fully formed in the support (1); - the semiconductor layer sequence (400) has an active region (40) intended for generating radiation; - the semiconductor layer sequence (400) is electrically isolated from the second main surface (12) by means of the diode structure (2); and - in the carrier a protective diode (18) is formed between the first main surface and the diode structure. [2] Semiconductor chip (3) according to claim 1, wherein the diode structure (2) electrically isolates the first main area (11) from the second main area (12) for both polarities. [3] Semiconductor chip (3) according to claim 1 or 2, wherein the diode structure (2) comprises a first diode (24) and a second diode (25), wherein the first diode (24) and the second diode (25) are oriented oppositely to each other with respect to their forward direction. [4] Semiconductor chip (3) according to any of the preceding claims, wherein the carrier (1) contains a semiconductor material. [5] Semiconductor chip (3) according to one of the preceding claims, wherein the diode structure (2) has at least two layers (21, 22) with different conduction types. [6] Semiconductor chip (3) according to one of the preceding claims, wherein the diode structure (2) has at least three successive layers (21, 22, 23) which are configured to alternate with respect to their conduction type. [7] Semiconductor chip (3) according to claim 6, wherein the carrier (1) is metallurgically bonded to the semiconductor layer sequence (400). [8] Semiconductor chip (3) according to claim 6 or 7, wherein a side surface of the carrier (1) is provided with a passivation layer (8). [9] Method for manufacturing a plurality of semiconductor chips (3) comprising the steps: a) Providing a support substrate (10) with a first main surface (11) and a second main surface (12) opposite the first main surface (11); b) Forming a diode structure (2) over the entire surface of the substrate (10) between the first main surface (11) and the second main surface (12), wherein the diode structure (2) electrically insulates the first main surface (11) from the second main surface (12) at least for one polarity of an electrical voltage, and wherein a protection diode (18) is formed in the substrate (10) and is arranged between the first main surface (11) and the diode structure (2); c) Arranging a semiconductor layer sequence (400) on the first main surface (11) of the support substrate (10); wherein the semiconductor layer sequence (400) has an active region (40) for generating radiation, and the semiconductor layer sequence (400) is electrically isolated from the second main surface (12) of the support substrate (10) by means of the diode structure (2); and d) Separating the carrier substrate (10) with the semiconductor layer sequence (400) into a plurality of semiconductor chips (3). [10] Method according to claim 9, wherein step b) is carried out before step d). [11] Method according to claim 9, wherein step b) is carried out after step d). [12] Method according to any one of claims 9 to 11, wherein the diode structure (2) is formed by means of full-surface doping of the support substrate (10). [13] Method according to any one of claims 9 to 12, wherein the semiconductor layer sequence (400) is deposited on a growth substrate (49) and the growth substrate (49) is removed after step c). [14] Method according to any one of claims 9 to 12, wherein the semiconductor layer sequence (400) is epitaxially deposited on the support substrate (10) in step c).

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