System and method for background calibration of time-interleaved analog-to-digital converters

Abstract

Nested analog-to-digital converter (ADC) comprising: a reference ADC (310) coupled to receive an analog signal (302), the reference ADC (310) generating a digital reference output (305); a plurality of sub-ADCs (104; 304) coupled to receive the analog signal (302), the plurality of sub-ADCs (104; 304) sampling the analog signal (302) at sampling positions responsive to a clock (402, 404, 406) and generating a plurality of digital signals corresponding to a sampled portion of the analog signal (302); a calibration block (108; 308; 1016) coupled to receive the plurality of digital signals and the digital reference output (305), wherein the calibration block (108; 308; 1016) identifies at least one error value (506) between the plurality of digital signals and the digital reference output (305); and wherein a correlation basis function (510; 702) is applied to the at least one error value (506) to generate an error estimate signal (516) used to compensate for the at least one error value (506), the error value (506) being determined by a difference between at least one of the plurality of digital signals and the digital reference output (305).

Description

BackgroundTechnical area

[0001] The present invention relates to analog-to-digital converters and, more particularly, to systems, apparatus, and methods for calibrating channel-to-channel mismatch errors caused by one or more sources in interleaved analog-to-digital converters. Background of the invention

[0002] Time-interleaved analog-to-digital converter (I-ADC) technology enables energy-efficient and high-speed sampling and digitization of analog input signals. Single-channel ADC architectures typically balance three competing parameters: 1) accuracy, 2) speed, and 3) power. An I-ADC architecture allows the requirements for achieving high accuracy to be separated from the requirements for operating at high speeds. This allows the power consumption required to achieve a given sampling rate to be optimized. In general, I-ADC technology is the preferred option for achieving extremely high sampling rates.

[0003] An I-ADC is a type of converter array with multiple parallel sampling channels. The sampling frequency of each channel does not need to satisfy the Nyquist criterion individually; rather, the sampling frequency of the combined output of all channels in the I-ADC should satisfy the Nyquist criterion. Under ideal conditions, the sampling rate of the I-ADC increases proportionally with the number of interleaved parallel ADC channels. In practice, each ADC channel introduces a number of component errors, such as phase shift errors in the clock signals. I-ADCs are known to introduce new, performance-limiting errors caused by transmission path inconsistencies (e.g., propagation delays), gain, and skew inconsistencies between the multiple ADC channels. Such a converter array is known, for example, from US 2009 / 0167575 A1, in which errors are determined using multiple reference voltages before correction.The respective reference error is applied to a digital output range. For errors of neighboring reference voltages in the same direction, the average value is used; for errors in opposite directions, the value is zero. The digital output variable is corrected by subtracting the reference error.

[0004] The types of imbalances requiring calibration can generally be classified into time skew imbalances, bandwidth imbalances, offset imbalances, gain imbalances, and static nonlinearity imbalances. The combined channel imbalance error can modulate nonlinearly with the unknown analog input signal, creating signal-dependent error terms that further limit I-ADC performance. Furthermore, temperature fluctuations, power supply voltage, and other environmental conditions can alter the imbalance error over time, necessitating additional imbalance calibration.

[0005] Although many solutions have been proposed to minimize, compensate, or calibrate the various sources of inequality, inequality error remains a bottleneck for high-accuracy and fast sampling of high-frequency input signals.

[0006] To correct each inequality error, a method is required that correlates the error of interest with an observable output signal, which is often the digital output signal of one or more channels that make up the array in the I-ADC. To achieve convergence, the correlation of each inequality error with its observable output signal must be sufficiently large for the analog input signal applied to the ADC input. In addition, the inequality error must be sufficiently independent of other inequality errors.

[0007] To overcome the disadvantages described above, systems, devices and methods for background calibration of I-ADC circuits are needed. Summary of the invention

[0008] Various embodiments of the invention provide background calibration of I-ADCs. This calibration reduces channel-to-channel mismatch errors, such as timing skew, gain errors, DC offset errors, static nonlinearities, and others, caused by a number of sources within fast I-ADCs.

[0009] In certain embodiments of the invention, channel-to-channel imbalance errors are corrected by comparing the output of a pre-calibrated reference ADC with the output of sub-ADCs, combining the difference with a known error signature, and feeding a correction signal back to the I-ADCs to correct specific channel-to-channel imbalance errors.

[0010] Certain embodiments of the invention utilize information derived from the input signal to define a function representing a known inequality error. The function is correlated with a calculated inequality error to generate an estimate for each type of inequality error. Based on the estimate, a control circuit within a sub-ADC generates a correction signal that is used to minimize or correct the inequality error.

[0011] In various embodiments, the reference ADC samples the analog input signal in a predetermined temporal relationship with respect to the sub-ADCs such that the sample positions of the reference ADC coincide with corresponding sample positions of the sub-ADCs at predetermined intervals. Brief description of the drawings

[0012] With reference to embodiments of the invention, examples thereof are illustrated in the accompanying figures. These figures are intended to be illustrative, not restrictive. Although the invention is generally described in connection with these embodiments, it is to be understood that the scope of the invention is not limited to these specific embodiments. Figure 1 is a block diagram of a prior art I-ADC device. Fig. 2 is a block diagram of another interleaved ADC device according to the prior art. Fig. 3 is a block diagram of an interleaved ADC device according to various embodiments. Fig. 4 is a timing diagram of calibration of an interleaved ADC according to various embodiments. Fig. 5 is a diagram illustrating the correlation of channel-to-reference errors with a correlation basis function according to various embodiments. Fig. Figure 6 is a block diagram of a prior art subranging (or line) ADC stage. Fig. 7 illustrates an example set of correlation basis functions for static inequality errors for an ADC according to various embodiments. Fig. Figure 8 shows a relation of time skew to channel-to-reference error. Fig. 9 illustrates an expected correlation between the actual slope of a single-tone input and the estimated slope derived from a discrete-time differentiation of the sampled input signal, according to various embodiments. Fig. 10 is a block diagram of an interleaved ADC device according to various embodiments. Fig. 11 is a flowchart of an illustrative process for calibrating an I-ADC device according to various embodiments of the invention. Detailed description of the preferred embodiments

[0013] In the following description, for the purpose of explanation, specific details are set forth in order to aid in an understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention described below may be practiced in a variety of ways and using a variety of means. One skilled in the art will also recognize additional modifications, applications, and embodiments included within the scope of the invention, as well as additional areas in which the invention may be useful. Accordingly, the embodiments described below are illustrative of specific embodiments of the invention and are intended to avoid obscuring the invention.

[0014] Reference in the specification to "a particular embodiment" or "any embodiment" means that a particular feature, structure, characteristic, or function described in connection with that embodiment is included in at least one embodiment of the invention. The appearance of the phrases "in a particular embodiment," "in any embodiment," or similar terms in various places in the specification does not necessarily mean that they all necessarily refer to the same embodiment.

[0015] Furthermore, connections between components or between method steps in the figures are not limited to direct connections. Instead, the connections between components or method steps depicted in the figures may be modified or otherwise altered by the addition of intervening components or method steps without departing from the teachings of the present invention.

[0016] Fig. Figure 1 shows an optimization technique using a prior art I-ADC device 100 to perform background calibration of an inequality error. A common input signal 102 is input to M interleaved sub-ADCs 104. Each sub-ADC samples the input signal 102 once per M composite ADC samplers. IRAWdesignated digital output data 106 of the sub-ADCs 104 are then input to a digital calibration block 108 which performs an open-loop background calibration of inequality errors on the nested sub-ADCs 104.

[0017] Since the ordinary input signal 102 is unknown, assumptions are made regarding the statistical properties of the input signal 102 for calibration in order to converge. Unfortunately, the statistical properties of the input signal 102 may change over time, or the input signal 102 may contain the same frequency at which a particular inequality distortion manifests itself (for example, F s / M). Furthermore, it can be very difficult to identify the inequality error causing the corresponding distortion tones in the spectrum, and even more difficult to minimize it. As a result, a practical ADC calibration using this optimization technique may be poorly designed and result in a non-convergent system that fails to minimize or correct the inequality error.

[0018] Recent work has acknowledged this limitation by introducing a new observable output to the I-ADC system that describes the ADC input signal. When combined with the outputs of the existing M ADC channels, this extra output can potentially lead to a convergent system, provided the extra output introduces sufficient new information into the system.

[0019] Fig. Figure 2 is a block diagram of a prior art I-ADC device employing comparator-based background calibration. A digital calibration block 202 uses feedback information 204 to calibrate errors in the sub-ADCs 206, such as a delay proportional to the phase of each sample time. The use of an auxiliary comparator 208 aims to minimize channel-to-channel mismatch error caused by skew. With a single sampler as the temporal reference, periodic sample positions of the auxiliary ADC occur at integer multiples of the period defined by the overall sample rate.

[0020] Fig. Figure 3 is a block diagram of an interleaved ADC device with background calibration according to various embodiments. Calibration occurs in the background and without interrupting the conversion process. In one embodiment, the ordinary input signal 302 is input to M interleaved sub-ADCs 304 used for M-fold interleaving. The reference ADC 310 is a multi-bit analog-to-digital converter with an accuracy equal to or greater than the accuracy of the sub-ADCs 304. The reference ADC samples the input signal 302 in a predetermined temporal relationship with respect to each sub-ADC 304, as shown in Fig. 4. The reference ADC 310 may receive the clock signals through a variable delay cell (not shown). The delay may be controlled by a digital feedback message from the digital calibration block 308.

[0021] Adding the reference ADC 310 results in a total of M+1 ADC channels. Each channel converts the input signal 302 to a digital output, resulting in a set of M+1 digital ADC outputs, which may have any form containing information about the input signal 302. The information assists in correcting channel-to-channel mismatch errors. In particular, reference ADC parameters, such as sample time, offset, gain, integral nonlinearity, or the like, may be defined to serve as reference data against which the sub-ADC parameters are calculated to calibrate the sub-ADCs 304. The reference ADC's own parameters may be calibrated in the foreground or background using any technique known to those skilled in the art.

[0022] A digital data output 306 from each sub-ADC channel 304 is forwarded to the digital calibration block 308. In one embodiment, the digital calibration block 308 is placed in the feedback from the reference ADC 310 and the sub-ADC 304 (or equivalently, a digital calibration block for each channel). The digital calibration block 308 is coupled to receive the M digital outputs 306 of the sub-ADCs 304 and the output data 305 of the reference ADC channel 310. For each type of inequality error to be corrected and for each channel, the digital calibration block 308 can store and adjust an estimate of the specific inequality error. Each of the sub-ADC channels 306 is coupled to receive analog or digital feedback control signals 312 for each inequality error from the digital calibration block 308.The feedback control signals 312 are used to correct the inequality errors within each interleaved sub-ADC 304 using either suitable analog or digital methods. In another embodiment, the digital calibration block 308 corrects inequality errors without feedback control signals such that the inequality errors are corrected by the digital calibration block 308 in the digital domain.

[0023] In one embodiment, all ADCs 304, 310 receive an analog input signal 302 for sampling, either directly or indirectly through an input signal conditioning circuit, such as a buffer (not shown). The buffer can be used to limit noise resulting from the fast sampling process.

[0024] Fig. Figure 4 is a timing diagram of a calibration of an interleaved ADC according to various embodiments, illustrating the sampling period of the sub-ADCs relative to the sampling period of the reference ADC. In one embodiment, each ADC samples the analog input signal continuously once per M composite ADC samplers, such that each sample edge of the clock signal 402 is separated by a period T s which is separated in a sampling time of MT s for each ADC channel. The reference ADC channel samples the analog input signal at a frequency equal to or less than MT ssuch that the sample positions of the reference ADC at the clock signal 406 sequentially match the sample positions of the clock signal 404 for each of the M sub-ADC channels over time. For example, if the reference ADC samples once every M+1 composite samples, and assuming that the time delay between the clock generator and the sample position is comparable for the reference channel and the sub-ADC channels, then the sample position of the reference ADC will rotate through each of the approximate sample positions for each of the sub-ADC channels over a period of M-(M+1) composite samples. Those skilled in the art will understand that a very wide set of different sampling frequencies, fixed or variable, exist for the reference ADC that can perform this function.

[0025] Returning to Fig. 3, after the reference ADC 310 finishes converting its sampled input, it outputs digital data 306, which is then input to the digital calibration block 308. The digital output data 305 and 306 may be in any form containing information about the analog input signal 302, including redundant information regarding the stage bit decisions if the sub-ADC 304 is a subranging (or line) ADC.

[0026] Fig. 5 is a diagram illustrating the correlation of channel-to-reference errors with a correlation basis function according to various embodiments. In one embodiment, digital output data 502 encoded by the reference ADC is subtracted from all sub-ADC output data 504, with the difference 506 (also called channel-to-reference error) representing errors due to a mismatch between the corresponding sub-ADC channel and the reference ADC. Reference ADC parameters, such as sample time, offset, gain, integral nonlinearity, or the like, may be defined to serve as parameters against which sub-ADC output data 504 is measured. For all sub-ADC output data 504, the channel-to-reference error 506 is input to distinguish multipliers 508 to correlate against the parameters of the reference ADC.In particular, the channel-to-reference error 506 for each disparity error of interest is multiplied by a correlation basis function 510 specific to that error to produce a correlation output 512 P. ij ; where i denotes the channel index and j denotes the inequality index.

[0027] The multiplication can be performed within the digital calibration block and with various levels of accuracy, from 1 bit to more than 16 bits. Additionally, the multiplication can be trivial or simply indicated by the choice of the correlation basis function 510. However, to achieve good convergence, the correlation output is preferably large in magnitude for strong correlations, small in magnitude for weak correlations, and the sign of the correlation output 512 should indicate the polarity of the inequality error. For inequality sources that are independent of each other, when determining the correlation basis function 510 for a given error, all other inequality errors are assumed to be zero, and each correlation basis function 510 is ideally orthogonal to other correlation basis functions.The correlation basis function 510 may depend on any information regarding the signal or a quantized output of interest, such as slope, frequency, ADC decisions, or the like.

[0028] The correlation outputs 512 may be filtered by a low-pass filter 514 (e.g., an integrator) to provide a large degree of data oversampling or averaging. Each filter output describes an estimate 516 of the inequality error as translated by the control circuitry in each sub-ADC channel. The error estimates 516 are fed back to the corresponding control circuitry such that the specific error is subtracted or canceled using direct or indirect methods. Over time, the error estimate 516 will converge to a steady-state value that is ideally equal to or close to the actual inequality error. Thus, each sub-ADC is corrected to match the characteristics of the reference ADC.To the extent that the reference ADC is suboptimal in terms of offset, gain, and linearity, the calibration loop for each sub-ADC will settle to the error present in the reference ADC. As previously described, the inequality parameters of the reference ADC (e.g., offset, gain, linearity, or similar) can be calibrated in the foreground or background. In one embodiment, the bandwidth of the calibration block is set only large enough to initially settle within a reasonable time and track deviations (e.g., in temperature, power supply voltage, or similar). Typical values ​​for a closed-loop bandwidth are between 1 kHz and 20 kHz.

[0029] Fig. Figure 6 is a block diagram of a prior art subranging (or line) ADC stage. A classic subranging (or line) ADC with a typical 600 stage is shown in Fig. 6. It is well known to those skilled in the art that one of the dominant sources of integral nonlinearity in a line ADC is random capacitor mismatch in the first-stage conversion. Capacitor mismatch in the DAC stage causes nonlinearity in the analog-to-digital conversion and can be thought of as a channel-to-reference skew error localized to the decision of the bit decision comparator 604 (BDC, also called FLASH). Each time a particular BDC decision 606 is made, a non-optimal amount of charge is subtracted from the charge representing the input signal 602. Therefore, knowing the BDC decision 606 and the optimal quantization output (i.e., the output from the reference ADC), the correlation circuit will measure or estimate the amount of non-optimal charge added for each corresponding BDC decision 606.Once the error estimate is known, the correction can be performed in an analog (subtracting the BDC-dependent charge in the stage) or digital way (subtracting values ​​from the output message).

[0030] Fig. Figure 7 illustrates a set of correlation basis functions for static inequality errors, such as gain, skew, or nonlinearity, for an exemplary ADC with a 2.5-bit first stage, according to various embodiments. In one embodiment, each possible BDC decision 704 has a correlation basis function 702 that is equal to 1 for the corresponding BDC decision 704 and 0 otherwise. As a result, multiplying the channel-to-reference error by the correlation basis function 702 can be performed, for example, with clock blanking. Other sources of static nonlinearity in the ADC, along with the capacitor inequality error, can be reduced piecewise, and boundaries of segments can be demarcated by BDC decisions 704. It is also possible that the piecewise function can be extended to have a larger or smaller number of segments, with or without regard to BDC decisions 704.

[0031] The output-referred offset for a sub-ADC is equal to the mean output of the sub-ADC with a zero voltage input subtracted from an optimal output message, which is the reference ADC output. Thus, the correlation basis function 702 can be set to 1 for an offset error. However, this choice of correlation basis function 702 is not orthogonal to the nonlinearity correlation basis function described previously. If more than one inequality error is to be estimated, cross-correlations between the inequality errors should be avoided. To illustrate, a BDC decision 704 of +1 and a channel-to-reference error of -2 would cause a non-zero P for both the offset and nonlinearity correlations, so the calibration block would attempt to calibrate each type of inequality error. A number of solutions can be employed to deal with the nonlinearity.In one embodiment, the offset estimate can be taken as the average of the nonlinear corrections and simply subtracted from the ADC output message. Alternatively, the nonlinearity calibration can assume full responsibility for the offset correction. In both cases, the offset correlation basis function is unnecessary and can be eliminated entirely.

[0032] Since the offset correlation basis function of Figure 1 is not orthogonal to each correlation basis function 702, a similar orthogonality problem exists for the gain correlation basis function for correlating the channel-to-reference error with the gain error. The channel-to-reference error is linearly dependent on the gain error in both sign and magnitude. Therefore, this approach could affect the nonlinearity estimates, even though the gain error correlation basis function 702 could simply be set to the reference ADC output. In one embodiment, the gain error is estimated by taking a weighted sum of the nonlinear estimates. In an alternative embodiment where nonlinearity calibration is not employed, the previously described gain and offset correlation basis functions are orthogonal and can be used to resolve both inequality errors.Gain correction can be performed by digitally multiplying the ADC output message, by modulating the reference voltage used within the ADC, or by other methods.

[0033] Fig. Figure 8 illustrates a relationship between time skew error and channel-to-reference error. In one embodiment, the correlation basis function for the time skew error indicates the magnitude of the time skew error 802 as well as the polarity. The time skew error 802 is defined as the absolute time of the i-th sub-ADC channel sample 804 subtracted from the absolute time of the reference ADC sample 806. If ΓIN (t) is the slope of the ADC input signal at the sample position of the reference ADC, and assuming that the frequencies of the ADC input signal have periods that are very large compared to the time skew, then the channel-to-reference error 808 is calculated according to Δi ≈ ΓIN ·δti. Given that δti ≈ Δi / ΓIN, to find the actual time skew error 802, the channel-to-reference error 808 can be correlated with an estimate of the slope of the ADC input signal at the time the reference ADC is sampled.

[0034] To construct a correlation basis function that contains information about the input slope ΓIN (t), many existing pieces of information can be used, and many circuits are known that can be devised to estimate an input slope. In one embodiment, the existing information regarding the input signal can be used in such a way that no additional analog circuitry is required in the ADC. For this purpose, it can be helpful to use knowledge of the maximum frequency of the input signal. If the input frequency is significantly below the first Nyquist zone (i.e., the maximum input frequency is significantly smaller than F s / 2), then the polarity of the slope can be estimated by a discrete-time differentiation of the entire ADC output.

[0035] Fig. 9 illustrates an expected correlation, according to one embodiment, when comparing the actual slope of a single-tone input with the estimated slope derived from a discrete-time differentiation of the sampled input signal. The expected correlation p 902 between the actual input slope of a single-tone input and the estimated slope derived from a discrete-time differentiation of the sampled input signal is plotted against the input frequency normalized to the sampling frequency.

[0036] As in Fig. As shown in Figure 9, this approach establishes a good expected correlation r 902 between the actual slope and an estimated slope generated without additional analog circuitry. Consequently, for input frequencies contained in the first Nyquist zone, we can now define a possible correlation basis function for the time skew error as B skew =D ADC [n]-DADC [n-1], which is a simple first-order difference equation describing the time skew error in terms of the difference between the current ADC output message and the previous ADC output message. Note that this basis function is preferred because it gives a good indication of both the polarity and the magnitude of the slope, which in turn is proportional to the error resulting from time skew.

[0037] Although Fig. 9 illustrates the effectiveness of a simple basis function without additional hardware, it is based on the assumption that the input frequency is relatively small compared to the Nyquist frequency. In applications where the input frequency requirements lie in higher Nyquist zones, for example, in the direct digitization of a radio frequency input signal, and if the Nyquist zone is known, then the correlation basis function can simply be calculated for the second or even Nyquist zones (F s / 2-F s , 3F s / 2-2F s , and so on) or for odd Nyquist zones (0-F s / 2, F s -3F s / 2, and so on).

[0038] In one embodiment, additional circuitry, such as variable delay elements, comparators, differentiators, and additional ADCs, can be used to more accurately estimate the slope of the input signal. For example, time delay elements can be combined with one or more comparators to increase the effective sampling rate by the sample positions of the reference ADC, which can then be used to estimate the polarity of the slope. As shown in Fig. 10, additional information 1014 may then be passed to the digital calibration block 1016 for use in defining the correlation basis function.

[0039] Fig. 10 is a block diagram of an interleaved ADC device with additional slope detection circuitry used for timing skew calibration, according to various embodiments. For each timing skew calibration embodiment, the timing skew error can be corrected by any known analog or digital techniques. In one embodiment, the variable delay element is controlled by the error estimation signal. Other techniques for generating accurate clock phases are also applicable, for example, by weighting the sum of the squared clock phases. Post-processing the ADC output signal to digitally correct the timing skew is significantly more complex but may be preferable for scaled CMOS technologies.

[0040] Fig.Figure 11 is a flowchart of an illustrative process for calibrating an I-ADC device comprising a reference ADC and multiple sub-ADCs, according to various embodiments of the invention. In step 1102, an analog input signal is sampled by a number of sub-ADCs at consecutive sample positions in response to consecutively phased clock signals. The clock signals can generally be generated internally or externally and can be delayed, for example, by a variable delay cell prior to sampling.

[0041] In step 1104, each sub-ADC converts the analog input signal into a digital output signal.

[0042] In step 1106, the analog input signal is sampled by a reference ADC at successive sample positions in response to continuous clock signals. The sample positions of the reference ADC are chosen to match the sample positions of each of the sub-ADCs in such a way that the sample positions of the reference ADC overlap over time with the sample positions for each of the sub-ADCs. Those skilled in the art will recognize that the sample positions can be selected from a wide range of different sequences, allowing the reference ADC to match each sub-ADC.

[0043] In step 1108, the reference ADC converts the analog input signal to a digital output signal. Those skilled in the art will recognize that steps 1102 and 1106, and steps 1104 and 1108, may be performed concurrently.

[0044] In step 1110, a channel-to-reference mismatch error is determined from a difference between the digital output signal and the reference digital output signal, for example, by subtracting the digital output signal encoded by the reference ADC from each sub-ADC output signal.

[0045] In step 1112, each channel-to-reference error is correlated with one or more predetermined correlation basis functions to generate an estimate for each type of error. The correlation basis functions include information derived from the analog input signal, such as information about the input slope of the analog input signal at the time the reference ADC is sampled.

[0046] In step 1114, control circuits in the sub-ADC channels generate correction signals from the estimate values. The correction signals can be used to correct inequality errors, such as offset inequalities, gain inequalities, and static nonlinearity inequalities.

[0047] In step 1116, the correction signals are fed back to the corresponding control circuits of each sub-ADC to minimize the channel-to-reference errors between each sub-ADC and the reference ADC.

[0048] It will be appreciated by those skilled in the art that the foregoing examples and embodiments are exemplary and are provided for purposes of clarity and explanation, and do not limit the scope of the present invention. All permutations, extensions, equivalents, combinations, and improvements thereto that will become apparent to those skilled in the art upon reading the specification and studying the drawings are intended to be included within the spirit and scope of the present invention. Therefore, it is intended that the claims in the future non-provisional application encompass all such modifications, permutations, and equivalents as fall within the spirit and scope of the present invention.

Claims

[1] Nested analog-to-digital converter (ADC) comprising: a reference ADC (310) coupled to receive an analog signal (302), the reference ADC (310) generating a digital reference output (305); a plurality of sub-ADCs (104; 304) coupled to receive the analog signal (302), the plurality of sub-ADCs (104; 304) sampling the analog signal (302) at sampling positions responsive to a clock (402, 404, 406) and generating a plurality of digital signals corresponding to a sampled portion of the analog signal (302); a calibration block (108; 308; 1016) coupled to receive the plurality of digital signals and the digital reference output (305), wherein the calibration block (108; 308; 1016) identifies at least one error value (506) between the plurality of digital signals and the digital reference output (305); and wherein a correlation basis function (510; 702) is applied to the at least one error value (506) to generate an error estimate signal (516) used to compensate for the at least one error value (506), the error value (506) being determined by a difference between at least one of the plurality of digital signals and the digital reference output (305). [2] The ADC of claim 1, wherein the correlation basis function (510; 702) comprises information regarding a slope of the analog signal (302). [3] The ADC of claim 1, wherein the at least one error value (506) is representative of a sample offset error, a synchronization error, a bandwidth error, a gain error, or a static nonlinearity error. [4] The ADC of claim 1, wherein the reference ADC (310) is calibrated. [5] The ADC of claim 1, further comprising a multiplication circuit (508) coupled to receive the at least one error value (506) and the correlation basis function (510; 702) to produce the error estimation signal (516). [6] The ADC of claim 5, wherein the error estimation signal (516) is a weighted sum of a plurality of other estimation signals. [7] The ADC of claim 5, further comprising a correction circuit coupled to receive the error estimation signal (516) to reduce the error value (506) for at least one of the sub-ADCs (104; 304) in the plurality of sub-ADCs (104; 304). [8] A method for calibrating an interleaved analog-to-digital converter (ADC), the method comprising the following steps: Continuously sampling an analog signal (302) at a plurality of sampling positions; Sampling the analog signal (302) at reference sampling positions that correspond to the plurality of sampling positions in a predetermined sequence; Converting the analog signal (302) sampled at the sampling positions into a plurality of digital outputs; Converting the analog signal (302) sampled at the reference sampling positions into a digital reference output (305); Determining at least one error value (506) from a difference between at least one of the plurality of digital outputs and the reference digital output (305); Correlating the at least one error value (506) with at least one correlation error function to generate at least one error estimation signal (516); Generating a correlation signal (512) in response to the at least one error estimation signal (516); and Applying the correlation signal (512) to a sub-ADC (104; 304) within the ADC to reduce the at least one error value (506). [9] The method of claim 8, wherein reducing the at least one error value (506) is performed by a correction circuit within the sub-ADC (104; 304). [10] The method of claim 8, wherein reducing the at least one error value (506) is achieved by a least-mean-square calculation process. [11] The method of claim 8, wherein the correction signal corrects a gain imbalance by digitally adjusting a reference voltage within the ADC. [12] The method of claim 8, comprising the step of determining the at least one error value (506) by subtracting the digital reference output (305) from one of the plurality of digital outputs. [13] The method of claim 8, wherein the step of correlating comprises multiplying the at least one error value (506) by a correlation basis function (510; 702) to generate the at least one error estimation signal (516). [14] The method of claim 8, further comprising the step of estimating a slope of the analog signal (302). [15] The method of claim 14, further comprising the step of determining a polarity of the estimated slope by performing a discrete-time differentiation of the digital output value. [16] The method of claim 8, further comprising the step of post-processing the digital output value to digitally correct the error value (506). [17] The method of claim 8, further comprising the step of filtering the error estimate signal (516) by a low-pass filter (514) to provide a large degree of data oversampling or averaging. [18] The method of claim 8, further comprising the step of calibrating the digital reference output value in the foreground prior to generating the correction signal. [19] The method of claim 8, wherein the correlation error function is inverted for even Nyquist zones. [20] Analog-to-digital converter (ADC) system, comprising: a clock generator for generating a plurality of clock signals; a reference ADC (310) coupled to receive an analog signal (302), the reference ADC (310) generating a digital reference output (305); a plurality of sub-ADCs (104; 304) coupled to receive the analog signal (302), the plurality of sub-ADCs (104; 304) sampling the analog signal (302) at sampling positions responsive to a clock (402, 404, 406) and generating a plurality of digital signals corresponding to a sampled portion of the analog signal (302); a calibration block (108; 308; 1016) coupled to receive the plurality of digital signals and the digital reference output (305), wherein the calibration block (108; 308; 1016) identifies at least one error value (506) between the plurality of digital signals and the digital reference output (305), wherein a correlation basis function (510; 702) is applied to the at least one error value (506) to generate an error estimate signal (516) used to compensate for the at least one error value (506); a multiplication circuit (508) coupled to receive the at least one error value (506) and the correlation basis function (510; 702) to generate the error estimation signal (516); and a low-pass filter (514) to filter the error estimation signal (516). [21] The ADC system of claim 20, comprising a variable delay cell coupled to an input of at least one of the plurality of ADCs to delay a transmission time of the clock signal (402, 404, 406). [22] The ADC system of claim 20, further comprising circuitry to generate a slope estimate of the analog signal (302).

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