System for a coreless transformer

Abstract

Transformer (200) which has the following features: a first coil (204, 404) formed in a first conductive layer in a first plane, wherein the first coil has a first end (212, 412) arranged within an outer circumference of the first coil; a second coil (202, 402) formed in a second conductive layer in a second plane, wherein the second plane is arranged parallel to the first plane and at a first distance in a vertical direction from the first coil, wherein the second coil has a first end (206, 410) arranged within an outer circumference of the second coil; a first crossing (209) arranged in the second conductive layer, wherein the first crossing is directly connected to the first end of the first coil and extends past the outer circumference of the first coil; and a second crossing (207) arranged in the first conductive layer, wherein the second crossing is directly connected to the first end of the second coil and extends past the outer circumference of the second coil; wherein the first end of the second coil is arranged outside the outer circumference of the first coil; and wherein the first end of the first coil is arranged outside the outer circumference of the second coil.

Description

[0001] The present invention relates generally to semiconductor circuits and methods, and more particularly to a system for a coreless transformer.

[0002] US 2007 / 0 268 106 A1 describes an on-chip transformer balun. It includes a primary winding as the input terminal of the on-chip transformer balun and a secondary winding as the output terminal of the on-chip transformer balun. Either the primary winding or the secondary winding is formed from a plurality of metal layers in which a spiral conductor section, excluding an underpass, is arranged on mutually different layers to form an asymmetric structure.

[0003] US 7,570,144 B2 describes an integrated transformer structure with a first coil element connected to a transverse axis, wherein the first coil element has at least one turn. The first coil element comprises a first portion provided on a first lateral plane and a second portion provided on a second lateral plane. The first and second lateral planes are spaced apart from each other along said transverse axis.

[0004] US 2009 / 0 284 339 A1 describes a transformer with a fully symmetrical structure, comprising a primary coil assembly and a secondary coil assembly. The primary coil assembly comprises a plurality of primary coils formed in a plurality of metal layers and a first interlayer connection unit for connecting the primary coils. The secondary coil assembly comprises a plurality of secondary coils formed in a plurality of metal layers and a second interlayer connection unit for connecting the secondary coils. The primary and secondary coils, which are formed in the same metal layer, are concentric and axially symmetric with respect to a diametrical line passing through a planar center.

[0005] US 7,362,205 B2 describes a common-mode filter comprising a first conductor layer, a second conductor layer, and an insulating layer disposed between the first and second conductor layers. The first conductor layer has a first spiral portion configured to draw a turn and a first conductor electrode extending from one end of the first spiral portion. The second conductor layer has a second spiral portion configured to draw a turn and a second conductor electrode extending from one end of the second spiral portion.

[0006] US 2005 / 0 116 793 A1 describes a thin-film common-mode filter comprising: magnetic plates, upper / lower coil conductors spirally wound between the plates, upper / lower lead conductors connected to the coil conductors and extending to outer portions; upper / lower lead terminals connected to the lead conductors; upper / lower coil terminals connected to the coil conductors; and wherein each lead terminal consists of stacked conductor layers incorporated into the lead and coil conductors to ensure conductivity.

[0007] US 2007 / 0 045 773 A1 describes an integrated electronic device. It comprises a substrate, passive components, pads for external connections, and three-dimensional wiring. The passive components include a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils arranged in multiple layers. Mutually adjacent coil wires are spaced apart from each other.

[0008] Galvanic isolation is used in many electronic systems to separate different sections of the system. For example, isolation may be used in a device coupled to a data communications line, such as those found in wired local area networks, to prevent common-mode currents due to potential differences between remote transceivers. Galvanic isolation can also be used in medical facilities used to treat or monitor patients to safely separate low-current circuits from a high-voltage power supply to prevent electric shock. In addition, switching power supplies often use galvanic isolation to separate control circuitry from a high-power output.In addition, connections from one electronic system or subsystem to another electronic system or subsystem often use galvanic isolation to isolate the system for safety reasons.

[0009] Generally, discrete transformers and optocouplers are used to transmit signals from one electrical circuit to another without direct electrical contact between the two circuits. However, discrete transformers and optocouplers can be relatively large, heavy, and expensive. In the case of optocouplers, there can be problems related to the aging of optical components.

[0010] Another way to transmit signals from one electrical circuit to another without direct electrical contact is to use a coreless transformer. While a discrete transformer includes a core to direct the magnetic flux, the coils of a coreless transformer can be placed in close proximity to each other to achieve adequate magnetic coupling. In many cases, the coils of the transformer can be separated by a thin dielectric. However, when coils are placed in close proximity, there may be a risk of dielectric material breaking down in the presence of high voltages such as those encountered during electrostatic discharge events. There may also be a safety risk associated with the coils being placed in close proximity to each other.

[0011] According to one embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed within its respective coil and a second end disposed at an outer periphery of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer periphery of the first coil. Additionally, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer periphery of the second coil.

[0012] According to one embodiment, a transformer includes a first dielectric layer, a first coil disposed on a first conductive layer on a first side of the first dielectric layer, and a second coil disposed on a second conductive layer on a second side of the first dielectric layer opposite the first side. The first coil has a first end disposed within the first coil and a second end disposed at an outer periphery of the first coil, and the second coil has a first end disposed within the second coil and a second end disposed at an outer periphery of the second coil. The transformer also includes a first crossover disposed within the second conductive layer and a second crossover disposed within the first conductive layer.The first crossover is directly connected to the first end of the first coil and extends past the outer periphery of the first coil; and the second crossover is directly connected to the first end of the second coil and extends past the outer periphery of the second coil.

[0013] The first end of the second coil may be disposed outside the outer periphery of the first coil; and the first end of the second coil may be disposed outside the outer periphery of the second coil. In some embodiments, a first lateral distance between the first crossover and a nearest portion of the second coil is not less than a first critical distance; and a second lateral distance between the second crossover and a nearest portion of the first coil is not less than a second critical distance. The first critical distance and the second critical distance may be the same distance or they may be different distances. In one embodiment, the first critical distance is between about two and about five times a width of the first dielectric layer. Alternatively, critical distances outside this range may be used.

[0014] In some embodiments, the transformer is configured to withstand a potential difference of at least 2.5 kV between the first coil and the second coil. In further embodiments, the transformer may be configured to withstand a higher voltage, such as 4.5 kV, between the first coil and the second coil. In one embodiment, the first coil and the second coil may be implemented using a spiral inductor and / or the first coil and the second coil may each include at least two turns. In some embodiments, the first conductive layer, the first dielectric layer, and the second conductive layer are disposed on an integrated circuit.

[0015] In one embodiment, the first conductive layer, the first dielectric layer, and the second conductive layer comprise layers in a wafer-level package. The wafer-level package may contain only two conductive layers and at least one non-conductive layer, such that the only two conductive layers are the first conductive layer and the second conductive layer. In some embodiments, the wafer-level package includes at least one integrated circuit disposed on the second metal layer.

[0016] In one embodiment, the wafer-level package includes a redistribution layer, at least one integrated circuit disposed on the redistribution layer, and an encapsulation layer disposed over the at least one integrated circuit such that the first conductive layer is disposed over the encapsulation layer. The wafer-level package may further include encapsulation vias coupling the redistribution layer to the first conductive layer and the second conductive layer. In another embodiment, the wafer-level package includes at least one integrated circuit disposed over the first metal layer, wherein the first dielectric layer is formed as an encapsulation layer disposed over the at least one integrated circuit, and the second conductive layer is formed over the encapsulation layer.

[0017] According to another embodiment, a wafer-level package includes a first dielectric layer, a first conductive layer disposed on a first side of the first dielectric layer, and a second conductive layer disposed on a second side of the first dielectric layer such that the second side is opposite the first side. The wafer-level package also includes a first coil disposed in the first conductive layer and a second coil disposed in the second conductive layer. The first coil includes a first end disposed in the first coil and a second end disposed at an outer periphery of the first coil. Likewise, the second coil includes a first end disposed in the second coil and a second end disposed at an outer periphery of the second coil. A first crossover is disposed in the second conductive layer and a second crossover is disposed in the first conductive layer.The first crossover is directly connected to the first end of the first coil and extends past the outer periphery of the first coil, and the second crossover is directly connected to the first end of the second coil and extends past the outer periphery of the second coil. According to the invention, the first coil and the second coil form a transformer. The transformer can be an isolation transformer configured to withstand a potential difference of at least 2.5 kV between the first coil and the second coil.

[0018] According to the invention, the first end of the second coil is arranged outside the outer circumference of the first coil, and the first end of the second coil is arranged outside the outer circumference of the second coil. In some embodiments, a first lateral distance between the first crossover and the nearest portion of the second coil is not less than a first critical distance, and a second lateral distance between the second crossover and a nearest portion of the first coil is not less than a second critical distance. The first critical distance may be the same as or different from the second critical distance.

[0019] In one embodiment, the wafer-level package also includes an integrated circuit coupled to the first coil. The wafer-level package may include redistribution layers with only two conductive layers and at least one non-conductive layer, wherein the only two conductive layers include the first conductive layer and the second conductive layer. In one embodiment, at least one integrated circuit is disposed over the second conductive layer, and an encapsulation material is disposed over the at least one integrated circuit. The first coil and the second coil may be disposed in a fan-out region of the wafer-level package.

[0020] In one embodiment, the wafer-level package further includes at least one integrated circuit disposed over the first conductive layer, wherein the first dielectric layer comprises an encapsulation material disposed over the at least one integrated circuit. The wafer-level package may also include encapsulation vias coupling the first conductive layer and the second conductive layer at the first crossover and the second crossover.

[0021] In one embodiment, the wafer-level package further includes at least one integrated circuit disposed over a redistribution layer and an encapsulation material disposed over the at least one integrated circuit such that the first conductive layer, the first dielectric layer, and the second conductive layer are disposed over the encapsulation material.

[0022] According to another embodiment not encompassed by the claimed invention, a method of forming a transformer comprises: forming a second coil in a second conductive layer; forming a first crossover in the second conductive layer; forming a first dielectric layer over the second conductive layer; forming a first coil in a first conductive layer disposed over the first dielectric layer, and forming a second crossover in the first conductive layer. The first coil includes a first end disposed within the first coil and a second end disposed at an outer periphery of the first coil; and the second coil includes a first end disposed within the second coil and a second end disposed at an outer periphery of the second coil.The first crossover is coupled to the first end of the first coil and extends past the outer perimeter of the first coil; and the second crossover is coupled to the first end of the second coil and extends past the outer perimeter of the second coil. In one embodiment, forming the second conductive layer includes forming a wafer-level package including only two conductive layers and at least one non-conductive layer that includes the first conductive layer, the second conductive layer, and the first dielectric layer.

[0023] Advantages of embodiments of systems and methods include the ability to implement coreless transformers capable of withstanding high voltages using only two metal layers, allowing for inexpensive and compact isolation transformers. Other advantages include improving yield by reducing the number of layers and reducing the number of processes required to fabricate layers.

[0024] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Further features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims.

[0025] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. In the drawings: Fig. 1 a transformer according to the state of the art; Fig. 2 an embodiment of a transformer; Fig. 3 is a cross-sectional view of an embodiment of a transformer; Fig. 4 shows a transformer according to another embodiment; Fig. 5a-d an embodiment of wafer-level packages; Fig. 6a-b an embodiment of separate transceivers and Fig. 7 is a flowchart of a method for forming an embodiment of a transformer.

[0026] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise noted. The figures have been drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate particular embodiments, a figure number may be followed by a letter indicating variations of the same structure, material, or process step.

[0027] The making and using of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed merely illustrate specific ways of making and using the invention and do not limit the scope of the invention.

[0028] The present invention will be described with respect to embodiments in a specific context, namely a coreless transformer. Embodiments of the present invention are not limited to coreless transformers and can also be applied to other types of circuits that utilize inductive elements.

[0029] Coreless transformers can be used in applications where galvanic isolation is required to separate one side of the transformer from the other. One way to construct a coreless transformer is to place planar coils in close proximity to each other. This can be done, for example, on an integrated circuit or on a substrate, in which insulating dielectric layers are distributed between multiple conductive layers. However, in many applications, high-voltage isolation is required, in which case the transformer is designed so that the dielectric separation between the primary and secondary coils of the transformer does not break down under high-voltage conditions.In some cases, the system in which the transformer is housed may not be configured to operate continuously under high voltage conditions; nevertheless, the coreless transformer may be specified to withstand high voltages of up to 4.5 kV, for example, in the event of an electrostatic discharge.

[0030] One way coreless transformers have been configured to withstand high voltages is by using multiple metal layers and dielectric layers that can withstand high-voltage conditions. However, the use of multiple metal layers can be expensive in low-cost, high-volume applications.

[0031] Fig. 1 illustrates a conventional coreless transformer 100 having a first winding 104 on a first metal layer, disposed over a second winding 102 on a second metal layer. A lead 106 on a third metal layer connects an inner winding terminal 108 of the second winding 102 to a point on the circumference of the second winding 102 along an outer winding terminal 114. Similarly, a lead 110 on the third metal layer connects an inner winding terminal 112 of the first winding 104 to a point outside the circumference of the first winding 104 along the outer winding terminal 116. It should be understood that the coreless transformer 100 requires at least three metal layers and at least two dielectric layers: two metal layers for the first and second windings 102 and 104, and at least one metal layer for connecting the metal segments 106 and 110.

[0032] In one embodiment, a coreless transformer is implemented using only two metal layers and at least one dielectric layer between each of the two metal layers. By geometrically spacing crossover sections so that a minimum distance is maintained between two structures on the same metal layer that may experience a high potential difference, high-voltage isolation can be maintained without dielectric breakdown or device damage.

[0033] Fig. 2 illustrates a coreless transformer 200 according to an embodiment of the present invention. The coreless transformer 200 includes a first winding 204 on a first metal layer, disposed over a second winding 202 on a second metal layer. An inner terminal 206 of the second winding 202 is routed via a metal segment 207 on the first metal layer to the outer periphery of the second winding 202. Similarly, the inner terminal 212 of the first winding 204 is routed via a metal segment 209 on the second metal layer to the outer periphery of the first winding 204. In one embodiment, the inner terminal 206 of the second winding 202 is located outside the outer periphery of the first winding 204; and the inner terminal 212 of the first winding 204 is located outside the outer periphery of the second winding 202.Thus, only two metal layers may be used to implement the coreless transformer 200, and an additional metal layer is not required.

[0034] In the embodiment of Fig. 2, a portion 220 of the first winding 204 is shaped such that the inner terminal 206 of the second winding 202 is disposed outside the perimeter of the first winding 204; and the portion 222 of the second winding 202 is shaped such that the inner terminal 212 of the first winding 204 is disposed outside the perimeter of the second winding 202. It should be understood that in alternative embodiments of the present invention, other geometries may be used to position inner winding terminals of one winding outside the perimeter of the other winding.

[0035] In one embodiment, lateral dielectric breakdown is prevented by ensuring that portions of windings are maintained a minimum distance away from connecting segments on the same metal layer. For example, connecting segment 207 on the first metal layer is maintained at a minimum distance 208 from first winding 204; and connecting element 209 on the second metal layer is maintained at a minimum possible distance 210 from winding 202. In one embodiment, distances 208 and 210 are determined by the properties of the materials, such as a dielectric, disposed between the segments.

[0036] Fig. 3 illustrates a cross-section 300 of one embodiment of a coreless transformer. Cross-section 300 shows a first metal layer containing an inner winding 312, outer windings 320 and 322, and an inner winding connection 304 for an upper layer coil. A second metal layer contains windings 306 and 307 of a lower layer coil. A second layer segment 302 connects the inner winding 312 to the inner winding connection 304. Cross-section 300 also shows an upper layer dielectric 315, a first dielectric layer 314, and a lower layer dielectric 316.

[0037] In one embodiment, the voltage breakdown between the first and second coils depends on the vertical dielectric strength of the dielectric layer 314 between the top surface of the windings 306 and 307 and the bottom surface of the inner winding 312. The thickness of this distance is referred to as the length "d." The voltage breakdown also depends on the horizontal dielectric strength of the interface between the dielectric layers 314 and 316 across the horizontal distance "b" between the winding 306 and the second layer segment 202, which connects the inner winding 312 to the inner winding connection 304. The horizontal dielectric strength per µm is less than the vertical dielectric strength due to issues at the interface between the dielectric layers 314 and 316.These problems may include contamination and the potential for delamination due to thermomechanical loads caused by mechanisms such as thermal cycling and power cycling. In some embodiments, the ratio of the vertical dielectric strength to the horizontal dielectric strength is a factor between about 2 and 5. However, in some cases, this factor may be outside the range of 2 to 5. For example, the range of the ratio may be between 1 and 10 and greater. In one embodiment, the minimum horizontal distance b is determined by the relationship b = a * d. Typical values ​​for the vertical dielectric strength of the dielectric layer 314 may be between about 100 V / µm and about 500 V / µm. Values ​​for polyimide are in the range of about 200 V / µm and about 300 V / µm. Alternatively, dielectrics may exist with vertical dielectric strengths outside this range.

[0038] In one embodiment, the distance "d" may be between about 10 µm and 50 µm, and the distance b may be between about 20 µm and about 500 µm, and typically between about 100 µm and about 300 µm for embodiments using die embedding technologies where a fan-out region surrounds the die. In such embodiments, the first coil and the second coil can withstand voltages of, for example, up to about 2.4 kV. Other distances outside these ranges may also be used depending on the embodiment and its respective specifications.Chip embedding technologies that utilize an embodiment include, but are not limited to: wafer-level packaging, in which packaging connections are made directly over the wafer using redistribution layers; technologies such as eWLB, in which a fan-out region in the redistribution layers extends beyond the perimeter of the die and may surround the die; and other chip embedding technologies such as "chip in substrate," in which a region is also created around the chip. In some embodiments, this substrate region may be used for a redistribution layer.

[0039] Fig. 4 illustrates a coreless transformer 400 according to another embodiment. The coreless transformer includes a first coil 404 implemented in a first metal layer and a second coil 402 implemented in a second metal layer. Coils 402 and 404 are offset from each other such that inner terminal 410 of the second coil is at least a distance 408 from first coil 404 and inner terminal 412 of first coil 404 is at least a distance 406 from second coil 402. Distances 406 and 408 may be determined based on the lateral breakdown strength of dielectric layers used as well as the high voltage requirements of transformer 400. Distances 406 and 408 may be the same or different depending on the dielectric layers used. In one embodiment, coils 402 and 404 each have two turns and an octagonal geometry.Alternatively, other geometries and / or more or fewer turns may be used. In some embodiments, the first coil 404 and the second coil 402 may have a different number of turns to achieve different coupling ratios.

[0040] The Fig. 5a-d illustrate an embodiment of wafer-level packages on which an embodiment of transformers can be implemented. For example, Fig. 5a shows a wafer-level package 500 with redistribution layers 504 arranged beneath an integrated circuit 502. Solder balls 506 may be coupled to the redistribution layer 504 to implement WLB (Wafer Level Ball Grid Array) packages, as shown. Alternatively, bump connections or wire bonds may be used instead of solder balls 506. In further embodiments, any type of embedded package may include an embodiment of the Fig. 5a-d. An embodiment of coreless transformers may be fabricated in the layers of redistribution layer 504. In some embodiments, redistribution layer 504 has only two conductive layers and one or more insulating layers, so the transformer embodiment not shown is implemented using only two metal layers, as described above.

[0041] Fig. 5b illustrates an embedded chip package 520 with a redistribution layer 504 that extends beyond the horizontal dimensions of the integrated circuit 502. The encapsulation material 508 may be disposed on the integrated circuit 502 and the redistribution layer 504. One or more coreless transformer embodiments may be implemented within the redistribution layer 504 as described above. In alternative embodiments, an embodiment of coreless transformers may be implemented in the substrates of encapsulated parts, substrates of hybrid packages, a semiconductor circuit such as a silicon integrated circuit, or using other structures. In further embodiments, the redistribution layer 504 may include multiple transformers.

[0042] Fig. 5c shows an embedded chip package 530 with a chip 502a and chip 502b arranged within the encapsulation material 508 on the redistribution layer 510. Further layers 512 with two metal layers and an insulation layer between the metal layers are arranged on the encapsulation material 508. In one embodiment, the redistribution layer 510 carries chip pad connections to solder balls 506 and to encapsulation vias 532, which are coupled to an embodiment of transformers arranged in further layers 512. In one embodiment, a transformer can be used in further layers 512 to establish a galvanically isolated connection between chip 502a and chip 502b. Encapsulation vias may be formed by attaching a via bar to the redistribution layer 510 and then forming an encapsulant 508 around the via bar and around the chips 502a and 502b.Alternatively, the encapsulant 508 may be formed first, after which holes are drilled, for example, with a laser. The holes are then filled with a conductive material, such as metal.

[0043] Fig. 5d illustrates an embedded chip package 540 with chip 502a and chip 502b disposed within encapsulation material 508 on redistribution layer 540. A top layer 516, including, for example, a metal layer and a passivation layer, is disposed on encapsulation material 508. In some embodiments, the one metal layer is disposed on encapsulation material 508 and the passivation layer is deposited thereon. Redistribution layer 514 includes a first winding of a transformer, and top layer 516 includes a second winding of the transformer, constructed according to embodiments described herein. Connections to the second winding, including one embodiment of crossover connections, are implemented by encapsulation vias 532. Here, encapsulant 508 serves as a dielectric between the first winding and the second winding of the transformer.In some embodiments, the encapsulant 508 may be an epoxy material with a filler material such as SiO2. Alternatively, other filler materials may be used. The thickness of the encapsulant 508 may range between about 250 μm and about 1000 μm. Alternatively, other thicknesses outside this range may be used. In some embodiments, packaging may be implemented using systems and methods described in US Patent No. 8,093,711 B2.

[0044] The Fig. 6a and Fig. 6b illustrate an embodiment of separate transceivers. Fig. Figure 6a illustrates a separate integrated transceiver circuit 600 having a first transceiver 602 including a transmitter 606 and a receiver 608, and a second transceiver 604 including a receiver 610 and a transmitter 612. In one embodiment, the transmitter 606 of the first transceiver 602 is coupled to the receiver 610 of the second transceiver 604 via transformer 614. Similarly, the transmitter 612 of the second transceiver 604 is coupled to the receiver 608 of the first transceiver 602 via transformer 616. The first transceiver 602 is referenced to supply nodes VDD1 and GND1, and the second transceiver 604 is referenced to supply nodes VDD2 and GND2.In one embodiment, supply nodes VDD1 and GND1 may be coupled to a first power supply or a first electronic system or subsystem, and supply nodes VDD2 and GND2 may be coupled to a second power supply or a second electronic system or subsystem that is separate from the first power supply.

[0045] The transformers 614 and 616 may be implemented using coreless transformers according to the embodiments described above. In one embodiment, the transformers 614 and 616 are implemented using two metal layers and at least one dielectric layer of the integrated circuit 600. In one embodiment, the at least one dielectric layer may be a SiO2 layer.

[0046] Fig. Figure 6b illustrates a separate transceiver module 620 having a first transceiver circuit 622, a second transceiver circuit 634, and a transformer circuit 636. The transmitter 626 of the first transceiver 622 is coupled to the receiver 630 of the second transceiver 634 via a transformer substrate 638. Similarly, the transmitter 632 of the second transceiver 634 is coupled to the receiver 628 of the first transceiver 622 via the transformer 640. In one embodiment, the first and second transceivers may be implemented using integrated circuits, and the transformer substrate may be implemented on a printed circuit board (PCB) or a hybrid substrate on which the circuits 622 and 634 are disposed.

[0047] Fig.7 illustrates a flowchart 700 of a method for forming one embodiment of a transformer. First, in step 702, a substrate is provided, which may be a semiconductor substrate, a fan-out wafer-level package, a hybrid, a PCB, or other substrate. A first coil and a first crossover for the second coil are formed in a first conductive layer over the substrate (step 704). The first conductive layer may be formed from a metal such as aluminum or copper using methods known in the art. Alternatively, other conductive materials may be used. Step 704 may be performed by semi-additive, subtractive processing, contact printing, or any other processing.Next, in step 706, a dielectric material, such as SiO2, polymer material, or other insulating material, with openings at relevant positions is formed over the first conductive layer. A second coil and a second crossover for the first coil are then formed in a second conductive layer over the dielectric material (step 708). The second crossover for the first coil is coupled to an inner end of the first coil and extends past the perimeter of the first coil. Similarly, the first crossover for the second coil is coupled to an inner end of the second coil and extends past an outer perimeter of the second coil. An optional insulating material, such as nitride passivation, polymer material, or other insulating material, may be formed over the second conductive layer in step 710.

Claims

[1] Transformer (200) comprising: a first coil (204, 404) formed in a first conductive layer in a first plane, the first coil having a first end (212, 412) disposed within an outer periphery of the first coil; a second coil (202, 402) formed in a second conductive layer in a second plane, the second plane being parallel to the first plane and spaced a first distance in a vertical direction from the first coil, the second coil having a first end (206, 410) disposed within an outer periphery of the second coil; a first crossover (209) disposed in the second conductive layer, the first crossover being directly connected to the first end of the first coil and extending past the outer periphery of the first coil; and a second crossover (207) disposed in the first conductive layer, the second crossover being directly connected to the first end of the second coil and extending past the outer periphery of the second coil; wherein the first end of the second coil is arranged outside the outer circumference of the first coil; and wherein the first end of the first coil is arranged outside the outer circumference of the second coil. [2] Transformer (200) according to claim 1, wherein: a center of the first coil (204, 404) is laterally offset from a center of the second coil (202, 402). [3] Transformer (200) according to claim 2, wherein: wherein a majority of a surface area of ​​the first coil (204, 404) is not directly opposite a majority of a surface area of ​​the second coil (202, 402) in the vertical direction. [4] Transformer (200) according to one of claims 1 to 3, wherein the first crossover (209) is laterally spaced from a nearest region of the second coil (202, 402); and wherein the second crossover (207) is laterally spaced from a nearest region of the first coil (204, 404). [5] Transformer (200) according to one of claims 1 to 4, wherein the first coil (204, 404) and the second coil (202, 402) each have at least two turns. [6] Transformer (200) according to one of claims 1 to 5, further comprising: a first dielectric layer (314) disposed between the first coil (204, 404) and the second coil (202, 402). [7] The transformer (200) of claim 6, wherein the first conductive layer, the first dielectric layer (314) and the second conductive layer comprise layers in a wafer-level package. [8] The transformer (200) of claim 6 or 7, wherein the first dielectric layer (314) comprises a polymer material. [9] Transformer (200) according to one of claims 1 to 8, wherein the first conductive layer and the second conductive layer are arranged on an integrated circuit.

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