Circuit on thin substrate for use in waveguides and manufacturing processes

Abstract

Method for producing a substrate-based circuit (31) with a carrier substrate (2) and with at least one conductor track (7) and / or antenna element (8) arranged on the carrier substrate (2), characterized by, the following procedural step: - applying by deposition (S1) of at least one fastening element (20) to an outer region of the carrier substrate (2), wherein the at least one fastening element (20) projects beyond an edge of the carrier substrate (2), wherein the at least one fastening element (20) is designed such that the carrier substrate (2) can be clamped in a waveguide (40) via the parts of the fastening element (20) which protrude beyond the outer region of the carrier substrate (2), wherein the waveguide (40) is formed from two waveguide segments (411, 412) which are firmly connected to one another, wherein each waveguide segment (411, 412) has a groove (421, 422), and wherein the at least one fastening element (20) is clamped between both waveguide segments (411, 412) so that the substrate-based circuit (31) is arranged centrally within the waveguide (40) formed from both grooves (421, 422).

Description

[0001] The invention relates to a method for producing a circuit having at least one conductor track arranged on the carrier substrate, as well as to a substrate-based circuit having such a thin carrier substrate and a corresponding waveguide having a substrate-based circuit.

[0002] In microwave technology, electromagnetic waves are typically transmitted in coaxial cables up to a frequency of 110 GHz. Above this frequency, waveguides are used. Signal processing (frequency filtering, frequency multiplication, attenuation, amplification, mixing, combining (e.g., diplexing)) takes place on substrate-based circuits. For this purpose, the wave must be coupled into and out of the substrate. With increasing frequency—especially for the terahertz range (0.1 to 100 THz)—the requirements for these substrate-based circuits become more stringent. Small dimensions, tighter tolerances, and excellent electrical properties are required. Semiconductor components (or generally nonlinear components) are required for the signal processing steps of multiplication and mixing, and these components must be integrated into the substrate-based circuit accordingly.The carrier substrate used must be permeable to the intended frequency range, i.e., have low attenuation. This is the only way the electromagnetic waves can be coupled to the substrate-based circuit and guided via corresponding lines on the substrate-based circuit within a waveguide. The substrate-based circuit must be very thin for this to work, which can easily lead to cracks within the substrate-based circuit.

[0003] EP 0 760 536 A1 discloses a self-supporting device for microwave transmission and a method for its production. EP 0 760 536 A1 discusses the problem that the carrier substrate, which is also referred to as the membrane, can easily tear during assembly. EP 0 760 536 A1 therefore recommends that a so-called reinforcing element, which can be an electronic component, is placed on the membrane and firmly soldered to it, whereby this reinforcing element is wider than the cavity located beneath the membrane in which the high-frequency waves propagate. A disadvantage of EP 0 760 536 A1 is that the membrane can only be prevented from tearing by placing an electronic component on it before the cavity is created. However, such an electronic component is not required in all cases. If, for example, the electromagnetic wave is to beIf only filtering is required, this can be done with an appropriate line structure, so that the use of an additional electronic component is not necessary.

[0004] It is therefore the object of the present invention to provide a method for producing a substrate-based circuit that exhibits high mechanical stability. A further object of the invention is to provide a waveguide in which a substrate-based circuit can be used particularly easily.

[0005] These objects are achieved by the features of the independent claims. The dependent claims advantageously develop the central idea of the invention.

[0006] The outer region preferably has a width of 500 µm, particularly preferably 300 µm or less than 300 µm. Attachment by deposition ensures that the mechanical stability of the carrier substrate is increased. The carrier substrate can also be referred to as a membrane, which exhibits no or only very low attenuation for the frequency range of the high-frequency microwave signal. This is achieved by the choice of material (e.g., epsilon r Si3N4 from 5.5 to 7.4 and tan delta around 0.025 and epsilon r diamond 5.6 and tan delta less than 0.001 depending on the frequency range) and the carrier thickness. Very thin carriers are therefore advantageous.

[0007] The fastening element can be in the form of a fastening strip or a fastening fin. The fastening element can also be referred to as a so-called beam lead. The fastening element is preferably arranged parallel to the conductor track formed on the carrier substrate and can establish a good ground connection. The fastening element also allows the carrier substrate to have not only high stability but also very good thermal contact.

[0008] It is particularly advantageous that an adhesive layer is applied underneath the contact layer so that the contact layer adheres optimally to the carrier substrate.

[0009] The use of photolithography for structuring and the very small thickness of the contact layer allows very fine structures to be realized.

[0010] The dimensions of the carrier substrates that can be produced range, for example, from 50 µm to 10 mm in width and 50 µm to 10 mm in length. The edge can, for example, have a range from 600 µm to preferably 200 µm, or more preferably less than 100 µm.

[0011] The outer region in which the fastening element is deposited on the carrier substrate can be adjusted as desired. This outer region does not always have to have the same dimensions. It preferably has a width of 600 µm to 200 µm, preferably less than 100 µm. The fastening element is preferably arranged parallel to the at least one conductor track consisting of the contact layer.

[0012] Various embodiments of the invention are described below by way of example with reference to the drawings. Identical objects have the same reference numerals. The corresponding figures of the drawing show in detail: Fig. 1A shows an embodiment of a layer structure from which the carrier substrate according to the invention with a circuit arranged thereon is created; Fig. 1B the layer structure in which a contact layer is structured; Fig. 1C shows the layer structure in which an adhesive layer exposed beneath the contact layer is structured; Fig. 1D shows the layer structure in which the exposed contact layer, the partially exposed adhesion layer and a partially exposed carrier substrate are coated with a solder resist layer; Fig. 1E the layer structure in which the solder resist layer is structured; Fig. 1F shows the layered structure in which an outer edge of the carrier substrate is removed to reveal an underlying second sacrificial carrier; Fig. 1G the layer structure in which the exposed second sacrificial carrier, the exposed carrier substrate, as well as the exposed adhesion layer, the exposed contact layer and the outer solder resist layer are coated with a further adhesion layer; Fig. 1H the layer structure in which the further adhesive layer is coated with a further contact layer; Fig. 1I the layer structure in which the further adhesive layer and the further contact layer are structured in such a way that the further adhesive layer and the further contact layer remain only at the locations where the fastening elements are to be formed on the outer region of the carrier substrate and on the second sacrificial carrier, and at the locations where the border is to be formed on the second sacrificial carrier, which border connects all fastening elements to one another via webs; Fig. 1J the layered structure in which a first sacrificial carrier has been removed; Fig. 1K the layered structure in which a second sacrificial carrier has been removed; Fig. 1L shows the layer structure in which at least a part of the adhesive layer arranged on the removed second sacrificial carrier has been removed; Fig. 2A shows a further embodiment of a layer structure in which a solder stop layer and / or the further adhesive layer are enclosed between the contact layer and the further contact layer, thereby forming a capacitance; Fig. 2B shows an embodiment of a plan view of the carrier substrate according to the invention with a conductor track and a support surface for an electrical component; Fig. 3A shows a further embodiment of a plan view of the carrier substrate according to the invention with an applied circuit structure, which shows, in addition to four fastening elements, also a border that connects the four fastening elements to one another via two webs each; Fig. 3B shows an embodiment of a plan view of the carrier substrate according to the invention with an applied circuit structure, which has four fastening elements whose webs were separated by means of a laser; Fig. 4A shows an embodiment of a spatial view of a waveguide according to the invention, which consists of two segments into which the carrier substrate according to the invention with the applied circuit structure is inserted; Fig. 4B shows a further embodiment of a further spatial view of the waveguide according to the invention, which consists of two segments into which the carrier substrate according to the invention with the applied circuit structure is inserted; Fig. 5A shows an embodiment of a flow chart for the method according to the invention for producing the carrier substrate; Fig. 5B shows a further embodiment of a flow chart for the method according to the invention, which explains the structure of the layer structure; Fig. 5C shows a further embodiment of a flow chart for the method according to the invention, which explains the construction of the layer structure; Fig. 5D shows a further embodiment of a flowchart for the method according to the invention, which explains the structuring of the circuit; Fig. 5E shows a further embodiment of a flow chart for the method according to the invention, which explains the passivation of the surface in the vicinity of a receiving surface; Fig. 5F shows another embodiment of a flowchart for the method according to the invention, which explains the removal of sacrificial carriers; Fig. 5G shows a further embodiment of a flow chart for the method according to the invention, which explains the production of fastening elements; Fig. 5H shows a further embodiment of a flowchart for the method according to the invention, which explains the cutting out of the substrate-based circuit; and Fig. 5I shows a further embodiment of a flow chart for the method according to the invention, which explains the production of a capacitor on a substrate layer.

[0013] Fig. 1A shows a layer structure 1 from which the carrier structure 2 according to the invention with a circuit arranged thereon is created. The layer structure 1 consists of a commercially available wafer, preferably made of silicon (Si). The Si layer is preferably a first sacrificial layer 3, as will be explained later. The silicon wafer can have a size of, for example, 2 inches or larger.

[0014] A second sacrificial layer 4 is preferably applied to the first sacrificial layer 3. The second sacrificial layer 4 is preferably made of silicon oxide (SiO2). The subsequent freestanding carrier substrate 2 is applied to the second sacrificial layer 4. The carrier substrate 2 is preferably silicon nitride (Si3N4) or diamond. The selection of the respective material is specifically defined by the specific electrical, thermal, and mechanical stresses.

[0015] An adhesive layer 5 is applied to the carrier substrate 2. The adhesive layer 5 preferably consists of titanium (Ti) or titanium tungsten (TiW) and / or chromium (Cr). This adhesive layer can be applied, for example, by a deposition process.

[0016] A contact layer 6 is then applied to the adhesive layer 5. The contact layer 6 is preferably made of gold.

[0017] The thickness of the contact layer 6 is, for example, 100 nm to 500 nm. The thickness of the adhesive layer is preferably 10 nm to 50 nm. The thickness of the carrier substrate is preferably 1 µm to 20 µm, more preferably 5 µm to 20 µm. The carrier substrate 2 is therefore significantly thinner than conventional ceramic circuit carriers or the individual layers of a printed circuit board, which each consist of individual foils bonded together. The layer thickness for the first sacrificial carrier 3 and the second sacrificial carrier 4 is selected such that processing is as error-free as possible.

[0018] The layered structure 1 itself can take any shape. Possible shapes include rectangles, squares, or L-shaped shapes, but circular or elliptical segments are also feasible. There are also no limitations on the length and width of the layered structure 1, from which the carrier substrate 2 later emerges.

[0019] Fig. 1B shows the layer structure in which the contact layer 6 is patterned. It is clearly visible that the contact layer 6 has been removed, with the exception of the part that forms the at least one conductor track 7 and / or the at least one antenna element 8 or the part that is formed as a support surface 9 of at least one electrical component 10. The contact layer 6 is patterned using photolithography and wet-chemical etching steps. Residues of a photoresist 111 are clearly visible on the part of the contact layer 6 that has not been removed.

[0020] Fig. 1C shows the layer structure 1, in which an adhesive layer 5 exposed beneath the contact layer 6 is patterned. The adhesive layer 5 is removed, with the exception of a first portion 51, which lies beneath the portion of the contact layer 6 on which the at least one conductor track 7 and / or the at least one antenna element 8 is formed. Furthermore, the portion of the adhesive layer 5 can optionally be removed, with the exception of at least a second portion 52, which is at a defined distance from a support surface 9 on the contact layer 6, which is configured to receive at least one electrical component 10. The second portion 52 of the adhesive layer 5 provides the adhesion to a solder resist layer or the dielectric of a capacitor, as will be explained below.

[0021] Also clearly visible is a photoresist 112, which is applied to the second part 52 of the adhesion layer 5, as well as to the remaining contact layer 6. This photoresist 112 can then be easily washed off. For the sake of clarity, the use of additional photoresists is no longer shown in the subsequent structuring steps. The carrier substrate 2, as well as the first and second sacrificial carriers 3, 4, remain unchanged.

[0022] Fig. 1D shows the layer structure 1, in which the exposed contact layer 6, the partially exposed adhesion layer 5, and a partially exposed carrier substrate 2 are coated with a solder resist layer 12. The carrier substrate 2, together with the second part 52 of the adhesion layer 5 and the contact layer 6, is coated with the solder resist layer 12. Such a solder resist layer, also referred to as solder resist, serves, on the one hand, to protect against corrosion and mechanical damage and, on the other hand, prevents the surfaces coated with it on the circuit board from becoming wetted with solder during soldering. The solder resist layer is preferably made of Si3N4 and has a thickness of, for example, 500 nm to, for example, 1500 nm. Other materials and other thicknesses, in particular for adjusting a capacitance, as will be explained below, are also possible.

[0023] Fig. 1E shows the layer structure 1 in which the solder resist layer 12 is structured. In this case, the solder resist layer 12 is removed with the exception of the areas that lie at least partially on the second part 52 of the adhesive layer 5 and / or that lie in a region between the second part 52 of the adhesive layer 5 and the support surface 9 and / or that lie at least partially on the support surface 9. It is clearly visible in the example from Fig. 1E shows that the solder resist layer 12 has been partially removed in the area of the support surface 9. This allows the soldering of an electrical component 10 onto the support surface 9. It is also clearly visible that the areas between the second part 52 of the adhesive layer 5 and the support surface 9 are lower and form a type of depression, which later serves to absorb the material of the solder resist layer 12 liquefied by the soldering process, so that the electrical component 10 can be optimally soldered.

[0024] In the event that no solder barriers in the form of a second part 52 of the adhesive layer 5 are required, these can also be omitted. This is possible in particular next to the contact layer 6 formed as a conductor track 7 or next to the contact layer 6 formed as an antenna element 8. In this case, the at least one conductor track 7 and / or the at least one antenna element 8 is preferably completely covered with the solder stop layer 12, which leads to a passivation of the surface and protects against corrosion. Even if Fig. 1E shows, for reasons of compactness, the application of the Si3N4 solder resist layer 12 onto the Si3N4 carrier substrate 2, there is a separating layer (not shown) between the two layers, which is Fig. 1E has already been removed.

[0025] Not shown is that the contact surface 9 not covered by the solder resist layer 12 can be filled again by applying an additional contact layer, which is preferably also made of gold, such that the height of the contact surface 9 corresponds to the height of the solder resist layer 12, so that the electrical component 10 can be optimally aligned and soldered. The carrier substrate 2, as well as the first and second sacrificial carriers 3, 4 are in Fig. 1E has not been changed.

[0026] Fig. 1F shows the layer structure 1, in which an outer edge 15 of the carrier substrate 2 has been removed, revealing a second sacrificial carrier 4 underneath. The width of the edge 15 can be chosen arbitrarily. Preferably, the edge 15 is located on all sides of the carrier substrate 2, regardless of the final shape of the carrier substrate 2. The width of the edge can be, for example, less than 1 mm, less than 700 µm, or less than 500 µm.

[0027] Fig. 1G shows the layer structure 1, in which the exposed second sacrificial carrier 4, the exposed carrier substrate 2, the exposed adhesion layer 5, the exposed contact layer 6, and the outer solder resist layer 12 are coated with a further adhesion layer 16. The further adhesion layer 16 is preferably selected from one of the materials from which the adhesion layer 5 is made. Therefore, the further adhesion layer 16 has the same hatching as the adhesion layer 5. Materials for the further adhesion layer 16 can be, for example, titanium, titanium tungsten, or chromium.

[0028] Fig. 1H shows the layer structure 1, in which the further adhesion layer 16 is coated with a further contact layer 17. The further contact layer 17 is preferably made of the same material from which the contact layer 6 is already made. The further contact layer 17 is therefore preferably made of gold. The thickness of the further adhesion layer 16 is in a range from 10 nm to 50 nm. The thickness of the further contact layer 17 is in a range from 500 nm to 3 µm, for example. This range is adjustable. In the drawings, the transitions between these further layers are shown as abrupt. In reality, the transitions are soft, rounded transitions.

[0029] Fig. Figure 1I shows the layer structure 1, in which the further adhesive layer 16 and the further contact layer 17 are structured in such a way that the further adhesive layer 16 and the further contact layer 17 remain only at the locations where the fastening elements 20 are to be formed on the outer region of the carrier substrate 2 and on the second sacrificial carrier 4, and at the locations where the border 21 is to be formed, which connects all fastening elements 20 via webs 22. Therefore, the further adhesive layer 16 and the further contact layer 17 also remain at the locations that later form the webs 22. A corresponding structure is shown in Fig. 3A and will be explained later. It is also possible for only the further contact layer 17 to be removed in a first step, while the further adhesion layer 16 is removed in a subsequent step. The removal of the further contact layer 17 and the further adhesion layer 16 is achieved by means of photolithography and wet-chemical etching steps.

[0030] Fig. Figure 1J shows the layer structure 1, in which a first sacrificial carrier 3 has been removed. The first sacrificial carrier 3, which preferably consists of silicon, can be removed by undercutting, e.g., using potassium hydroxide at a temperature of, e.g., 80°C.

[0031] Fig. Figure 1K shows layer structure 1, in which a second sacrificial support 4 has been removed. Thus, all sacrificial supports 3 and 4 have been removed.

[0032] Fig. 1L shows the layer structure 1 in which at least a part of the adhesive layer 16 arranged on the removed second sacrificial carrier 4 has been removed. A plan view of the layer structure 1 as shown in Fig. 1 is shown, Fig. 3A, which will be explained in detail.

[0033] Fig. Figure 2A shows the layer structure 1, in which a capacitor is formed by the contact layer 6 and the further contact layer 17, between which the solder resist layer 12 and / or the further adhesive layer 16 are enclosed. For this purpose, preferably Fig. 1C, the contact layer 6 is left on the second part 52 of the adhesive layer 5 and it is ensured that the contact layer 6 above the second part 52 of the adhesive layer 5 is also electrically conductively connected to the part of the contact layer 6 that forms the conductor track 7. In the embodiment of Fig. 2A, there is therefore no interruption between the first part 51 of the adhesive layer 5 and the second part 52 of the adhesive layer 5. Following this, the solder resist layer 12, as in Fig. 1D and in Fig. 1E shown, applied accordingly. In the further course, the further adhesive layer 16 can be applied over the solder stop layer 12, wherein the further contact layer 17 is applied to the further adhesive layer 16, whereby a capacitance is formed. The capacitance is formed between the overlapping area of the contact layer 6 and the further contact layer 17. The level of the capacitance can be adjusted by the size of the overlapping area and / or by the thickness of the dielectric, which is formed by the solder stop layer 12 and / or the further adhesive layer 16 between the contact layer 6 and the further contact layer 17.

[0034] In this case, the further contact layer 17 is electrically connected to the fastening element 20. The contact layer 6 forms, as will be explained in detail later, the at least one conductor track 7 and / or the at least one antenna element 8.

[0035] Fig. Figure 2B shows a top view of the carrier substrate 2 with a conductor track 7 and a support surface 9 for an electrical component 10. It can be clearly seen that the support surface 9 is surrounded by a solder resist layer 12, which ensures that the solder (e.g., tin solder) does not flow in uncontrolled paths, thus allowing reproducible solder joints to be obtained. The conductor track 7 can have a structural width of, for example, less than 50 µm, preferably less than 20 µm. The support surface is therefore not to scale.

[0036] The adhesive layer's effect as a solder resist does not occur as a mechanical barrier, but rather by preventing wetting / alloying with the gold of the contact layer. The second part 52 of the adhesive layer 5 therefore functions as a solder barrier. The conductor track 7, which is formed by the contact layer 6, is electrically separated from a further ground plane 25. The further ground plane 25 can also already be part of the fastening element 20.

[0037] Fig. Figure 3A shows a top view of an embodiment of the carrier substrate 2 according to the invention with an applied circuit structure, which, in addition to four fastening elements 20, also shows a border 21 that connects the four fastening elements to one another (or more or less) via, for example, two webs 22. It can be clearly seen that the carrier substrate 2 has a rectangular shape. Two fastening elements 20 are located on each of the two sides of the carrier substrate 2. These are preferably formed parallel to the conductor track. Fig. 1A to 1L show a section through axis A. Each fastening element 20 is connected to an outer border 21 via two webs 22. The distance between the outer border 21 and the carrier substrate 20 can be chosen arbitrarily.

[0038] Two antenna elements 8 and the associated conductor structures are also clearly visible. Two filters 30 are also shown, which filter the high-frequency microwave signal accordingly. The carrier substrate 2 can have any desired shape. This shape is, as shown in Fig. 3A, enclosed by a border 21, wherein the border 21 is connected to the carrier substrate 2 solely via the fastening elements 20. The number of fastening elements 20 is not limited to four, but can be any number. Depending on the thickness of the carrier substrate 2, more or fewer fastening elements 20 are required. The shape and width of the carrier substrate 2 also result in a different number of fastening elements 20 being required. The fastening elements 20 impart excellent mechanical stability to the carrier substrate 2, which is preferably less than 20 µm thick. At the same time, the fastening elements 20 allow excess thermal energy to be dissipated via them to a corresponding heat sink, e.g., in the form of a housing. This fact is referred to in the Fig. 4A and Fig. 4B. The substrate-based circuit 31, which is shown in Fig. 3A is the final product of the Fig. Follow the steps described in 1A to 1L.

[0039] Fig. Figure 3B shows a plan view of an exemplary embodiment of the carrier substrate 2 according to the invention with an applied circuit structure, which has four fastening elements 20, the webs 22 of which were preferably separated by means of a laser. Clearly visible is the substrate-based circuit 31, which is formed by detaching the frame 21, i.e. the border 21, by cutting through the webs 22. Fig. 3A. The support surface 9 can be equipped with the electronic component 10 before the webs 22 are cut through by the laser. However, it is also possible for the electronic component 10 to be installed only after the webs 22 and the border 21 have already been removed.

[0040] The area of the conductor track 7, which is located at the edge of the substrate-based circuit 31, can be used to supply a bias voltage (BIAS) to the substrate-based circuit 31.

[0041] The substrate-based circuit 31 in Fig. 3B, the carrier substrate 2, wherein the carrier substrate 2 is coated with a solder resist layer 12. However, an adhesive layer 5 is formed on the carrier substrate 2 in front of this, wherein a contact layer 6 is formed on at least a first part 51 of the adhesive layer 5, which forms at least one conductor track 7 and / or at least one antenna element 8. The carrier substrate 2 has at least one fastening element 20, which is deposited on the outer region of the carrier substrate 2 and protrudes beyond the outer region of the carrier substrate 2. By deposited is meant here that this is a mechanically stable, non-detachable connection, as is shown in the Fig. 1A to 1L. The deposition can be carried out, for example, by a physical PVD or chemical CVD process. The fastening elements 20 can be further reinforced by a galvanic process. The outer region of the carrier substrate 2 can be freely selected. Preferably, the outer region is smaller than 300 µm, particularly preferably even smaller than 200 µm or even smaller than 100 µm.

[0042] The frequencies of the microwave signal, which is coupled to the substrate-based circuit 31 via at least one antenna element 1, are, for example, at least 100 GHz and extend, for example, up to 2 THz.

[0043] The at least one fastening element 20 is preferably made of the same material as the contact layer 6. This material is preferably gold. The area where the at least one fastening element 20 is connected to the carrier substrate 2 comprises a further adhesive layer 16, which is arranged between the carrier substrate 2 and the fastening element 20.

[0044] It is also clearly visible that at least a portion of the contact layer 6 is designed as a support surface 9 for receiving an electronic component 10. As already explained, a second portion 52 of the adhesive layer 5 is located at a defined, adjustable distance from the support surface 9, wherein the second portion 52 of the adhesive layer 5 is at least partially provided with a solder stop layer 12. The area between the second portion 52 of the adhesive layer 5 and the support surface 9 is also provided with a solder stop layer 12. The same also applies to at least a portion of the support surface 9.It is also possible for a contact layer 6, 17 to be formed on an area between the adhesive layer 5, preferably using the second part 52 or a further part of the adhesive layer 5, and the solder resist layer 12, and for a contact layer 6, 17 to be formed on a further area of the same size on the solder resist layer 12, wherein the two contact layers 6, 17 are not electrically conductively connected to one another and are connected to the at least one fastening element 20 or to the at least one conductor track 7, whereby a capacitor is formed. The level of capacitance can be adjusted by the thickness of the solder resist layer 12 and the area of the structured contact layers 6, 17.

[0045] Fig. 4A shows a spatial view of an embodiment of a waveguide 40 according to the invention, which consists of two segments 411, 412 into which the carrier substrate 2 according to the invention, i.e., the substrate-based circuit 31 with the applied circuit structure, is inserted. It can be clearly seen that the waveguide 40 is formed from two waveguide segments 411, 412 that can be firmly connected to one another. A first waveguide segment 411 can be firmly connected to a second waveguide segment 412 via a screw connection and / or welded connection (not shown). Preferably, each waveguide segment 411, 412 has a groove 421, 422, wherein the at least one fastening element 20 is pressed between the two segments 411, 412, so that the substrate-based circuit 31 is arranged centrally within the waveguide 40 formed from the two grooves 411, 412. The depth of the respective groove 421, 422 can depend on the respective operating frequency.The higher the operating frequencies, the less deep the grooves must be.

[0046] Also clearly visible is an electrical component 10, which is mounted on the support surface 9 and is electrically connected to the at least one electrical conductor track 7. The at least one electrical component 10 can be, for example, a mixer.

[0047] It is also clearly visible that the substrate-based circuit 31 has four fastening elements 20, one part of which protrudes beyond the edge of the carrier substrate 2 by means of the fastening element 20. This part of each fastening element 20, which protrudes beyond the edge of the carrier substrate 2, is clamped between the two segments 411, 412 after they are firmly connected to each other. Each groove 421, 422 is at least as wide as the carrier substrate 2.

[0048] It can also be clearly seen that at least one waveguide segment 411, 412 has at least one recess 431, 432, wherein the at least one recess 431, 432 is arranged perpendicularly (or horizontally, not shown) to the at least one antenna element 8, wherein a microwave signal can thereby be fed to the at least one antenna element 8 via the at least one recess 431, 432. The at least one recess 431, 432 itself forms a waveguide. The vertical orientation is shown, for example, by the dashed line. A microwave signal can be fed to an antenna element 8 via, for example, the first recess 431. The microwave signal couples onto the at least one conductor track 7 via the antenna element 8 and is further processed by the electronic component 10 and, for example, its frequency is increased.Via the further antenna element 8, which is also electrically connected to the electronic component 10, the microwave signal with its frequency increased can be led out of the waveguide 40 via the second recess 432.

[0049] Such a waveguide 40 can, for example, be used to generate radar signals for weather satellites that have a very high frequency.

[0050] Fig. 4B shows a further spatial view of an exemplary embodiment of the inventive waveguide 40, which consists of two segments 411, 412, into which the inventive carrier substrate 3 with the applied circuit structure is inserted. It can be clearly seen how at least a portion of the fastening elements 20 rests on a surface of the second segment 412 of the waveguide 40. After the two waveguide segments 411, 412 are connected, the substrate-based circuit is held firmly and, above all, stably in position centrally within the formed waveguide 40 via this portion of the fastening element 20. Because both segments 411, 412 are firmly connected to one another, electrical contact with the housing ground of the waveguide 40 can also be established via the fastening elements 20. The waveguide 40 can thus serve as a heat sink to absorb excess thermal energy.

[0051] It is also possible for the surface of the first waveguide segment 411 and the surface of the second waveguide segment 412, which partially touch each other and between which some of the fastening elements 20 are inserted, to have a contour or profile, wherein the contour or profile of the corresponding surface of the first waveguide segment 411 is inverse to the contour or profile of the corresponding surface of the second waveguide segment 412, so that the surface of the first waveguide segment 411 engages the surface of the second waveguide segment 412 and vice versa. This allows the fastening elements 20 to be pressed even more effectively onto the waveguide.

[0052] Fig. 5A shows an embodiment of a flowchart for the method according to the invention. In a first method step S1, at least one fastening element 20 is applied to an outer region of the carrier substrate 2 by a deposition process, wherein the at least one fastening element protrudes beyond the outer region of the carrier substrate 2. All known deposition methods, such as PVD (physical vapor deposition) and electroplating, are suitable for depositing the fastening element 20. The fastening elements 20 are also referred to as beam leads.

[0053] Fig. 5B shows a further embodiment of a flow chart for the method according to the invention, which explains the construction of the layer structure 1 in more detail. In a second method step S2, the carrier substrate 2 is applied to at least one sacrificial carrier 3, 4. Subsequently, in a method step S3, an adhesive layer 5 is applied to the carrier substrate 2. Subsequently, in method step S4, a contact layer 6 is formed on the adhesive layer 7 and / or the at least one antenna element 8. In a further method step S5, the at least one conductor track 7 and / or the at least one antenna element 8 is structured. The carrier substrate 2 preferably consists of Si3N4 or diamond in the desired thickness. The adhesive layer 5 preferably consists of titanium, titanium tungsten or chromium. The contact layer 6 is preferably formed of gold. The conductor tracks 7 preferably have a width of, for example,less than 50 µm, more preferably less than 20 µm. Process step S5 is described in the . Fig. 1B and Fig. 1C.

[0054] Fig. 5C shows a further embodiment of a flow chart for the method according to the invention, which explains the construction of the layer structure 1. Preferably, the method step of applying the carrier substrate S2 comprises the following sub-process steps. These include the method step S 2_1 , which involves applying a second sacrificial carrier 4 to a first sacrificial carrier 3. Instead of process step S 2_1 or in addition to process step S 2_1 the process step S 2_2 Within process step S 2_2The carrier substrate 2 is applied to the second sacrificial carrier 4. The first sacrificial carrier 3 is preferably silicon. The second sacrificial carrier 4 is preferably SiO2.

[0055] Fig. 5D shows a further embodiment of a flowchart for the method according to the invention, which explains the structuring of the circuit. The structuring method step S5 preferably comprises the method steps S 5_1 and S 5_1 Within process step S 5­_1 the contact layer 6 is removed, with the exception of the part that forms the at least one conductor track 7 and / or the at least one antenna element 8, or the part that is designed as a support surface 9 of at least one electrical component 10. This step is in Fig. 1D.

[0056] In process step S 5_2the adhesive layer 5 is removed, with the exception of a first part 51, which lies beneath the part of the contact layer 6 on which the at least one conductor track 7 and / or the at least one antenna element 8 is formed. Alternatively or in addition thereto, the adhesive layer 5 is removed, with the exception of at least a second part 52, which has a defined distance from the support surface 9 on the contact layer 6, which is designed to receive at least one electrical component 10. These steps are described in Fig. 1C shown.

[0057] Fig. 5E shows a further embodiment of a flow chart for the method according to the invention, which explains the passivation of the surface in the vicinity of a receiving surface 9. For this purpose, within the structuring method step S5, preferably after the method step S 5_2 the process steps S 5_3 and S 5_4 In process step S5_3 The carrier substrate 2 is coated together with the second part 52 of the adhesive layer 5 and the contact layer 6 with a solder resist layer 12. This fact is described in Fig. 1D.

[0058] Within process step S 5_4 the solder resist layer 12 is removed, with the exception of the areas that lie at least partially on the second part 52 of the adhesive layer 5 and / or the areas that lie in a region between the second part 52 of the adhesive layer 5 and the support surface 9 and / or the areas that lie at least partially on the support surface 9. This fact is in Fig. 1E shown.

[0059] Fig. 5F shows a further embodiment of a flowchart for the method according to the invention, which explains the removal of the sacrificial carriers 3, 4. For this purpose, after completion of method step S5, method steps S6 and S7 are performed. Within method step S6, all sacrificial carriers 3, 4 are removed. The removal of the sacrificial carriers 3, 4 can be achieved by undercutting.

[0060] Within the method step S7, the further adhesive layer 16 arranged on the at least one removed sacrificial carrier 3, 4 is removed. These facts are described in the Fig. 1 year, Fig. 1K and Fig. 1L shown.

[0061] Fig. 5G shows a further embodiment of a flow chart for the method according to the invention, which explains the production of the fastening elements 20. For this purpose, the method steps S 1_1 , S 1_2 , S 1_3 and S 1_4Within process step S 1_1 an edge 15 of the carrier substrate 2 is removed. This process step is described in Fig. 1F shown.

[0062] Subsequently, the process step S 1_2 Within process step S 1_2 the process step S 1_1 exposed at least one sacrificial carrier 3, 4 together with the carrier substrate 2, which contains the adhesive layer 5 and the contact layer 6, is coated with a further adhesive layer 16 and with a further contact layer 17. The coating with the further adhesive layer 16 and with the further contact layer 17 is also a deposition process. These facts are described in Fig. 1G and Fig. 1H is explained in more detail.

[0063] Subsequently, the process step S 1_3 Within process step S 1_3the further adhesive layer 16 and the further contact layer 17 are removed, with the exception of the area on the carrier substrate 2 where no fastening elements 20 are to be formed for stabilization. This fact is also in Fig. 1I is explained in more detail.

[0064] Finally, the process step S 1_4 Within process step S 1_4 the further adhesive layer 16 and the further contact layer 17 are removed from the areas on the at least one sacrificial carrier 3, 4 on which no fastening elements 20 are to be formed, with the exception of a border 21 and at least one web 22, which surrounds all fastening elements 20 with a defined distance and connects them by at least one web 22. This situation also applies in Fig. 1J, but is not shown there because Fig. 1J shows a simplified cross-section through the substrate-based circuit 1 along the axis A, as shown in Fig. 3A. Both the fastening elements 20 and the border 21 and the at least one web 22 are formed from the same material, namely, on the one hand, the further adhesive layer 16 and, on the other hand, the overlying further contact layer 17.

[0065] Fig. 5H shows a further embodiment of a flowchart for the method according to the invention, which explains the cutting out of the substrate-based circuit 31. For this purpose, method step S8 is preferably carried out after method step S7. Within method step S8, the border 21 is removed by means of a laser in which the at least one web 22 is severed at the transition to the corresponding fastening element 20. The substrate-based circuit 31 is thereby detached from the border 21 and the webs 22. The situation is well illustrated at the transition from Fig. 3A on Fig. 3B.

[0066] Fig. 5I shows a further embodiment of a flow chart for the method according to the invention, which explains the production of a capacitor on a substrate layer 1. For this purpose, the method steps S9 and S 10 which, for example, following process step S 5_2 and S5_4 can be carried out. Within method step S9, at least one region of the adhesive layer 5 is coated with a contact layer 6 before the contact layer 6 is coated with the solder resist layer 12 and / or the further adhesive layer 16 itself.

[0067] After the solder resist layer 12 and / or the further adhesive layer 16 has been applied, the process step S 10 Within process step S 10At least the parts of the solder resist layer 12 and / or the further adhesive layer 16 that are arranged above the area of the adhesive layer 5 are coated with the further contact layer 17, whereby a capacitance is formed, the height of which is adjusted via a thickness of the solder resist layer 12 and / or the further adhesive layer 16 and / or the size of the area of the area. The area of the area is defined by the overlapping parts of the first contact layer 6 and the further contact layer 17. The further contact layer 17 can, for example, be connected to the at least one fastening element 20, as shown in Fig. 2A. The contact layer 6 is preferably electrically connected to the conductor track 7 or the at least one antenna element 8.

[0068] Within the scope of the invention, all described and / or drawn features can be combined with one another as desired.

Claims

[1] Method for producing a substrate-based circuit (31) with a carrier substrate (2) and with at least one conductor track (7) and / or antenna element (8) arranged on the carrier substrate (2), characterized by , the following procedural step: - applying by deposition (S1) of at least one fastening element (20) to an outer region of the carrier substrate (2), wherein the at least one fastening element (20) projects beyond an edge of the carrier substrate (2), wherein the at least one fastening element (20) is designed such that the carrier substrate (2) can be clamped in a waveguide (40) via the parts of the fastening element (20) which protrude beyond the outer region of the carrier substrate (2), wherein the waveguide (40) is formed from two waveguide segments (411, 412) which are firmly connected to one another, wherein each waveguide segment (411, 412) has a groove (421, 422), and wherein the at least one fastening element (20) is clamped between both waveguide segments (411, 412) so that the substrate-based circuit (31) is arranged centrally within the waveguide (40) formed from both grooves (421, 422). [2] Method according to claim 1, characterized by , the following procedural steps: - applying the carrier substrate (S2) to at least one sacrificial carrier (3, 4); - applying (S3) an adhesive layer (5) on the carrier substrate (2); - applying (S4) a contact layer (6) on the adhesive layer (5), from which the at least one conductor track (7) and / or the at least one antenna element (8) is formed; - Structuring (S5) the at least one conductor track (7) and / or the at least one antenna element (8). [3] Method according to claim 2, characterized by that the process step of applying the carrier substrate (S2) includes the following process steps: - Application (S 2_1 ) of a second sacrificial carrier (4) onto a first sacrificial carrier (3); and / or - Application (S 2_2 ) of the carrier substrate (2) onto the second sacrificial carrier (4). [4] Method according to claim 2 or 3, characterized by that the structuring process step (S5) comprises the following process steps: - Remove (S 5_1 ) the contact layer (6) with the exception of the part which forms the at least one conductor track (7) and / or the at least one antenna element (8), or the part which is designed as a support surface (9) of at least one electrical component (10); - Remove (S 5_2) of the adhesive layer (5) with the exception of a first part (51) which lies under the part of the contact layer (6) on which the at least one conductor track (7) and / or the at least one antenna element (8) is formed and / or removing the adhesive layer (5) with the exception of at least a second part (52) which has a defined distance from the support surface (9) on the contact layer (6) which is designed to receive at least one electrical component (10). [5] Method according to claim 4, characterized by that the structuring process step (S5) comprises the following process steps: - Overcoat (S 5_3 ) the carrier substrate (2) together with the second part (52) of the adhesive layer (5) and the contact layer (6) with a solder stop layer (12); - Remove (S 5_4) of the solder resist layer (12) with the exception of the regions which lie at least partially on the second part (52) of the adhesive layer (5) and / or which lie in a region between the second part (52) of the adhesive layer (5) and the support surface (9) and / or which lie at least partially on the support surface (9). [6] Method according to one of claims 2 to 5, characterized by that the process step of applying by deposition (S1) comprises the following process steps: - Remove (S 1_1 ) an edge of the carrier substrate (2); - Overcoat (S 1_2 ) the exposed at least one sacrificial carrier (3, 4) and the carrier substrate (2) together with the adhesive layer (5) and the contact layer (6) with a further adhesive layer (16) and with a further contact layer (17); - Remove (S 1_3) the further adhesive layer (16) and the further contact layer (17) from the areas on the carrier substrate (2) where no fastening elements (20) for stabilization are to be formed; - Remove (S 1_4 ) of the further adhesive layer (16) and the further contact layer (17) from the areas on the at least one sacrificial carrier (3, 4) on which no fastening elements (20) are formed, with the exception of a border (21) which surrounds all fastening elements (20) at a defined distance and connects them by at least one web (22). [7] Method according to claim 6, characterized by that the following procedural steps are carried out: - Removal (S6) of all sacrificial bearers (3, 4); - removing (S7) the further adhesive layer (16) arranged on the at least one removed sacrificial carrier (3, 4). [8] Method according to claim 7, characterized by that the following process step is carried out: - removing (S8) the border (21) by cutting through the at least one web (22) of the at least one fastening element (20), in particular by means of a laser. [9] Method according to claim 5, characterized by that the following process step is carried out: - coating (S9) at least one region of the adhesive layer (5) with a contact layer (6) before it is coated with the solder stop layer (12) and / or further adhesive layer (16); - Overcoat (S 10 ) at least the parts of the solder stop layer (12) or the further adhesive layer (16) which are arranged above the at least one region of the adhesive layer (5) with the further contact layer (17), whereby a capacitor is formed, the capacitance of which is adjusted via a thickness of the solder stop layer (12) and / or the further adhesive layer (16) and / or a size of the region. [10] Method according to claim 3, characterized by , that the first sacrificial carrier (3) contains Si and / or that the second sacrificial carrier (4) contains SiO2 and / or that each adhesion layer (5, 16) contains Ti or TiW and / or Cr and / or that the carrier substrate (2) consists of Si3N4 and / or diamond and / or that each contact layer (6, 17) contains Au. [11] Waveguide comprising a substrate-based circuit, the substrate-based circuit (31) comprising a carrier substrate (2), wherein an adhesive layer (5) is formed on at least a part of the carrier substrate (2) and wherein a contact layer (6) is formed on at least a first part (51) of the adhesive layer (5), which contact layer forms at least one conductor track (7) and / or at least one antenna element (8), characterized by , that the carrier substrate (2) has at least one fastening element (20) which is deposited on the outer region of the carrier substrate (2) and projects beyond an edge of the carrier substrate (2), that the waveguide (40) is formed from two waveguide segments (411, 412) which are firmly connected to one another, each waveguide segment (411, 412) having a groove (421, 422) and that the at least one fastening element (20) is clamped between both waveguide segments (411, 412) so that the substrate-based circuit (31) is arranged centrally within the waveguide (40) formed from both grooves (421, 422). [12] Waveguide according to claim 11, characterized by , that the at least one fastening element (20) is formed from the same material as each contact layer (6, 17) and / or that in the region where the at least one fastening element (20) is connected to the carrier substrate (2), a further adhesive layer (16) is arranged between the at least one fastening element (20) and the carrier substrate (2). [13] Waveguide according to claim 11 or 12, characterized by , that at least a part of the contact layer (6) is designed as a support surface (9) for receiving an electronic component (10) and / or that a second part (52) of the adhesive layer (5) is formed at a defined distance from the support surface (9) and / or that at least the second part (52) of the adhesive layer (5) is partially provided and / or a region between the second part (52) of the adhesive layer (5) and the support surface (9) and / or at least a part of the support surface (9) is provided with a solder stop layer (12). [14] Waveguide according to one of claims 11 to 13, characterized bythat a contact layer (6) is formed on a surface between the adhesive layer (5) and the solder stop layer (12), and that a further contact layer (17) is formed on a further surface of the same size on the solder stop layer (12) or on the solder stop layer (12) and the further adhesive layer (16), wherein the further contact layer (17) is electrically conductively connected to the at least one fastening element (20), and wherein the contact layer (6) is electrically conductively connected to the at least one conductor track (7) or the at least one antenna element (8), whereby a capacitor is formed. [15] Waveguide according to claim 13 or 14, characterized by , that each adhesion layer (5, 16) contains Ti or TiW or Cr and / or that the carrier substrate (2) consists of Si3N4 and / or diamond and / or that the solder resist layer (12) consists of Si3N4 and / or that each contact layer (6, 17) contains Au. [16] Waveguide according to claim 11, characterized by in that at least one waveguide segment (411, 412) has at least one recess (431, 432), wherein the at least one recess (431, 432) is arranged perpendicular to the at least one antenna element (8), whereby a microwave signal can be supplied to the at least one antenna element (8).

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