Drive control device for a motor

Abstract

A motor drive control device comprising an inverter circuit (3) with n (equal to or greater than 3) phases, the output lines (Vu, Vv, Vw) of respective phases of which are connected to respective phases (U, V, W) of an n-phase motor (4), and which controls the drive of the motor (4) based on an output signal of the inverter circuit (3); the motor drive control device comprising: an amplifier circuit (10) connected to the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3) and amplifying output signals of the output lines; Semiconductor relays (5U, 5V, 5W) interposed in respective phases of the motor (4), which are connected to the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3), and which are adapted to receive the output signals amplified by the amplifier circuit (10) and distributed as relay motor drive signals at a time of driving the motor; characterized by a switching circuit (11) which stops an operation of the amplifier circuit (10) and switches off the semiconductor relays (5) to switch off the drive of the motor, wherein the amplifier circuit (10) comprises: at least (n-1) pieces of diodes (Duu, Dvu, Dwu) interposed in a power (VB) supply line for the amplifier circuit (10) at a position upstream of connection points with the output lines of at least (n-1) phases of the inverter circuit (3); and a capacitor (Cd) for storing an electric charge, one end of which is connected to the output end of the diodes (Duu, Dvu, Dwu), the other end of the capacitor (Cd) being connected to a neutral point to which the phases of the motor (4) are connected.

Description

Background of the invention 1. Field of the invention

[0001] The present invention relates to a drive control device for a motor provided with a switching circuit for stopping the operation of the motor. 2. Description of related technology

[0002] Japanese Patent Application Laid-Open No. 2006-21645 A discloses that in an electric power steering apparatus, a semiconductor relay having higher reliability than a mechanical relay is provided in an output line of each phase connecting an inverter circuit and a motor, and the semiconductor relay is turned off to stop the driving of the motor.

[0003] However, in an operating state in which a phase of the inverter circuit is controlled with a particularly high duty cycle compared with other phases, in an output line of the phase with a particularly high duty cycle, boosting of a booster circuit is not performed or boosting is insufficient during the driving of the motor, so that the solid-state relay may be turned off to stop the operation of the motor.

[0004] Further related prior art is known from DE 10 2012 208 632 A1, which discloses the preamble of claim 1. Overview of the invention

[0005] Under the circumstances, the present invention has an object to provide a drive control device for a motor, wherein a switching circuit using a semiconductor relay having high reliability is provided, and the drive control device stably drives a motor even in an operating state in which the drive duty cycle differs considerably between phases.

[0006] To achieve the above-mentioned object, in one aspect of the present invention, there is provided a motor drive control device that includes an inverter circuit having n (equal to or greater than 3) phases, the output lines of respective phases of which are connected to respective phases of an n-phase motor, and that controls the drive of the motor based on an output signal of the inverter circuit. The motor drive control device includes: an amplifier circuit connected to the output lines of at least (n-1) phases of the inverter circuit; semiconductor relays connected to respective phases of the motor, which are connected to the output lines of at least (n-1) phases of the inverter circuit, and configured to receive the output signals amplified by the amplifier circuit and distributed as relay motor drive signals at a time of driving the motor; andand a switching circuit that stops the operation of the amplifier circuit and turns off the semiconductor relays to stop the motor from driving. The amplifier circuit comprises: at least (n-1) pieces of diodes interposed in a power supply line for the amplifier circuit at a position upstream of connection points with the output lines of at least (n-1) phases of the inverter circuit; and a capacitor for storing an electric charge, one end of which is connected to the output end of the diodes, the other end of the capacitor being connected to a neutral point to which the phases of the motor are connected.

[0007] Further objects and features of aspects of the present invention will become apparent from the following description with reference to the accompanying drawings. Short description of the drawings Fig. 1 is a system layout diagram showing an electric power steering (EPS) device for a vehicle. Fig. 2 is a view schematically illustrating a drive control device for an engine according to an embodiment of the present invention, which is applied to the EPS, etc. Fig. 3 is a detailed circuit diagram of a first embodiment of the above-described drive control apparatus for a motor. Fig. Figure 4 is a timing chart showing potentials at different sections when U, V, and W phases of the inverter circuit are driven at a duty cycle of 50%. Fig. 5 is a timing chart showing potentials at different sections when a U phase of the inverter circuit is driven at a duty cycle of 100% and V and W phases of the inverter circuit are driven at a duty cycle of 50%. Fig. 6 is a timing chart showing potentials at different sections when U, V, and W phases of the inverter circuit are driven at different duty cycles. Fig. 7 is a detailed circuit diagram of a second embodiment of the above-described drive control apparatus for a motor. Description of preferred embodiments

[0008] Fig. 1 is a system layout diagram showing an electric power steering (EPS) device for a vehicle.

[0009] A steering device to which such an EPS is applied has an actuating mechanism, a transmission mechanism and a linkage mechanism.

[0010] The actuating mechanism has a steering wheel SW and a steering shaft (column shaft) SS. The steering shaft SS has a first steering shaft S1 and a second steering shaft S2 (center shaft).

[0011] The transmission mechanism is of a rack and pinion type having a rack R and a pinion P. The pinion P is provided on a front part of a pinion shaft PS, which is connected to the second shaft S2 and meshes with the rack R.

[0012] The connecting mechanism has a tie rod TR connected to the rack R and steered wheels FL and FR connected to the tie rod TR.

[0013] An EPS 101 is of an electric direct connection type having an electric motor 102 configured to directly drive a gear box to generate an assist force, and is of a pinion assist type attached to the pinion shaft PS and providing an assist force for rotation of the pinion shaft PS.

[0014] The EPS 101 includes a motor 102 driven by electric energy (electric current) supplied from a battery BATT as a power source; a reduction gear mechanism 103 that reduces rotation of the motor 102; a torque sensor TS that detects steering torque; a resolver (not shown) that detects rotation (rotation angle or rotation position) of the motor; and an electronic control unit ECU that receives signals from these sensors and controls the drive of the motor 102. These components are housed in a single housing HSG, and the EPS 101 is formed as a unit that includes integrally integrated mechanical components and electronic components.

[0015] The EPS 101 is an example of a pinion EPS, but there are other EPSs such as double pinion EPSs, rack and pinion EPSs, or column EPSs, and an embodiment of the present invention is applicable to any type of EPS.

[0016] Fig. Fig. 2 schematically shows a drive control device for a motor having a switching circuit and used in the EPS etc. described above.

[0017] A CPU 1 outputs a PWM signal for inverter driving to a driver circuit 2 (FET driver). The driver circuit 2 expands a voltage level of the PWM signal and outputs the expanded PWM signal to an inverter circuit 3.

[0018] The inverter circuit 3 performs switching control of semiconductor switching elements and outputs PWM signals of U, V and W phases via output lines of respective phases to respective phases of a three-phase motor 4 (motor 102 in the EPS in Fig. 1). This drives motor 4.

[0019] In an EPS provided with such a mechanism, a driving force generated by driving the motor 4 assists the steering force for a steering operation of a vehicle driver.

[0020] Furthermore, in such an EPS, it is necessary to disable the steering assist force when an abnormality occurs in the vehicle, and for this purpose, a cut-off circuit is provided to cut off the drive of the motor.

[0021] In Fig. 2 the switch-off circuit for a motor is constructed as follows.

[0022] The phases of the motor 4 (U, V and W phases of a stator coil) each have one end to which PWM signals are input from the inverter circuit 3, and the other ends connected to each other at a neutral point via respective semiconductor relays 5 (5U, 5V and 5W).

[0023] Furthermore, the output lines of the U, V, and W phases of the inverter circuit 3 are each branched and connected to an amplifier circuit 10. During the driving of the motor 4, a control signal (gate voltage) amplified by the amplifier circuit 10 is supplied to the semiconductor relay 5 to enable the driving of the motor 4. Further, when a command to stop the driving of the motor 4 is issued from a CPU 1, a switching circuit 11 that has received the command stops the operation of the amplifier circuit 11 to keep the semiconductor relays 5 in the OFF state to stop the motor 4.

[0024] Fig. 3 shows a detailed circuit diagram of a first embodiment of a drive control device for a motor with the schematic structure described above.

[0025] An inverter circuit 3 is formed of a three-phase FET bridge circuit, and output voltages Vu, Vv and Vw output to U, V and W phases are input to upstream capacitors Cu, Cv and Cw of the amplifier circuit 10.

[0026] Downstream diodes Dud, Dvd, and Dwd are connected to the output side of the capacitors Cu, Cv, and Cw, respectively. The output sides of these downstream diodes Dud, Dvd, and Dwd are connected together at an upstream junction point uc, and the voltage is extracted as a common output voltage (gate voltage) Vs.

[0027] The common gate voltage Vs propagates through a resistor r11, is branched into three phases U, V and W at a downstream branch point db, propagates through resistors r21, r22 and r23 and is supplied to the gate terminals of the solid-state relays 5U, 5V and 5W of the U, V and W phases, respectively.

[0028] Further, between the downstream side of the resistor r11 and the downstream branch point db, one end of a downstream capacitor Cd is connected, and the other end of the capacitor Cd is connected to a neutral point Vn of the motor 4.

[0029] A resistor r12 and a Zener diode Dz are connected in parallel with the capacitor Cd, so that the potential difference between the gate voltage Vs and the neutral point Vn is limited to a breakdown voltage Vz (e.g., approximately 15 V) of the Zener diode Dz or less. Accordingly, the service life of 5U, 5V, and 5W solid-state relays can be increased.

[0030] Downstream terminals of the U, V and W phases of the motor 4 are connected to drain electrodes of the solid-state relays 5U, 5V and 5W, and source electrodes of the solid-state relays 5U, 5V and 5W are connected to the neutral point Vn.

[0031] Further, an electric power supply circuit is provided that supplies a power supply voltage VB through a resistor r41 and upstream diodes Duu, Dvu, and Dwu of the branched U, V, and W phases to points between the capacitors Cu, Cv, and Cw and downstream diodes Dud, Dvd, and Dwd. In this first embodiment, a transistor Tr1 is provided between the power supply and a resistor r41 (or between the resistor r41 and the upstream diodes Duu, Dvu, and Dwu) as a switching circuit.

[0032] The transistor Tr1 has a base terminal configured to receive a switching signal output from the CPU 1, and normally the transistor Tr1 is kept at an L level to set the transistor Tr1 in an ON state to supply the power supply voltage to the amplifier circuit 10 to operate the amplifier circuit and drive the motor 4.

[0033] Below are specific operation examples with reference to the timing diagrams in Fig. 4 to 6.

[0034] Fig. Figure 4 shows potentials at different sections when U, V and W phases of the inverter circuit are driven at a duty cycle of 50%.

[0035] When the output voltages Vu, Vv and Vw of the three phases U, V and W of the inverter circuit 3 are at L level (0 V), the input side voltages of the capacitors Cu, Cv and Cw are also at L level (0 V), and the output side voltages Vuc, Vvc and Vwc of the capacitors Cu, Cv and Cw become as follows. Vuc=VB−VfVvc=VB−VfVwc=VB−Vf

[0036] Here Vf is a turn-on voltage (e.g., approximately 0.7 V) of the diodes Duu, Dvu, and Dwu (and Dud, Dvd, and Dwd).

[0037] The voltage (source voltage) Vn of the neutral point to be applied to the source electrodes of the semiconductor relays 5U, 5V and 5W is at L level (0 V), which is the same as the output voltage of the inverter circuit 3.

[0038] Furthermore, the voltage (gate voltage) Vs to be applied to the gate electrodes of the semiconductor relays 5U, 5V and 5W to the turn-on voltage Vf of the diodes Dud, Dvd and Dwd is lower than the output voltages Vuc, Vvc and Vwc of the capacitors Cu, Cv and Cw and is as follows. Vs=VB−2Vf

[0039] Accordingly, a potential difference ΔVsn between the gate voltage Vs and the source voltage Vn becomes VB - 2Vf, and when this potential difference ΔVsn = VB - 2Vf exceeds the breakdown voltage Vz of the Zener diode Dz, this potential difference ΔVsn is maintained at ΔVsn = Vz. Since the turn-on voltage of a diode is approximately 0.7 V when the power supply voltage VB is at least 20 V and the breakdown voltage Vz is approximately 15 V, the potential difference ΔVsn is maintained at ΔVsn = Vz.

[0040] Next, when the output voltages Vu, Vv and Vw of the three phases U, V and W of the inverter circuit 3 rise to H level (VB), the output voltages Vuc, Vvc and Vwc of the capacitors Cu, Cv and Cw are increased to the following by an output voltage rise VB of the inverter circuit 3 through charge pumping. Vuc=VB−Vf+VB=2VB−VfVvc=VB−Vf+VB=2VB−VfVwc=VB−Vf+VB=2VB−Vf

[0041] Furthermore, since the gate voltage Vs is lower than the output voltages Vuc, Vvc and Vwc, which are 2VB-Vf, respectively, by the turn-on voltage Vf of the downstream diodes Dud, Dvd and Dwd, the gate voltage becomes the following. Vs=VB−Vf+VB−Vf=2VB−Vf

[0042] At the same time, the source voltage Vn is also increased by the output voltage increase VB of the inverter circuit 3.

[0043] Accordingly, the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn is calculated as follows. ΔVsn=Vs−Vn=2VB−2Vf−VB=VB−2Vf

[0044] Here, when the calculated value VB - 2Vf of this potential difference ΔVsn exceeds the breakdown voltage Vz of the Zener diode Dz, the potential difference ΔVsn is maintained at the breakdown voltage Vz. As described above, when the power supply voltage VB is at least 20 V and the breakdown voltage Vz is approximately 15 V, since VB - 2Vf exceeds the value Vz, the potential difference ΔVsn is maintained at ΔVsn = Vz.

[0045] As described above, even when the output voltages Vu, Vv and Vw of the inverter circuit 3 are switched between H level and L level, the potential difference between the gate voltage Vs and the source voltage Vn of each of the semiconductor relays 5U, 5V and 5W becomes the breakdown voltage Vz (or VB - 2Vf) defined by the Zener diode Dz.

[0046] Since the solid-state relays 5U, 5V, and 5W enter the ON state when the potential difference ΔVsn becomes at least a relay drive voltage V0 (e.g., approximately 10 V), the potential difference ΔVsn (Vz or VB - 2Vf), which is greater than the relay drive voltage V0, is maintained. Accordingly, each of the solid-state relays 5U, 5V, and 5W remains in the ON state, and the drive of the motor 4 can continue.

[0047] Next, based on Fig. 5 is an explanation regarding a case where one phase, e.g., the U phase, is driven at a duty cycle of 100%, and the other phases are driven at duty cycles of less than 100%, e.g., 50%. In an example of a power steering device, such an operating state occurs, for example, when an output torque increases significantly in cases where a steering wheel is strongly steered in one rotational direction or the rotational direction is reversed.

[0048] The output voltage Vu of the inverter circuit 3 is kept at the H level (VB), as shown in Fig. 5, and the output voltages Vv and Vw oscillate between the H level (VB) and the L level (0 V) at a 50% duty cycle.

[0049] When the output voltages Vv and Vw are at the L level (0 V), the voltage (source voltage) Vn at the neutral point becomes an average voltage 1 / 3 VB because a voltage VB is applied from the U phase of the motor 4 and the V phase and the W phase are at the L level (0 V).

[0050] The gate voltage Vs is determined as follows. Similar to the case where each of the U, V, and W phases is driven at a 50% duty cycle, the gate voltage Vs is lower than the output voltages Vuc, Vvc, and Vwc (= VB - Vf) of the capacitors Cu, Cv, and Cw applied via the power line by the turn-on voltage Vf of the diodes Dud, Dvd, and Dwd. Accordingly, the gate voltage Vs becomes Vs = VB - Vf - Vf = VB - 2Vf.

[0051] Accordingly, the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn is calculated as follows. ΔVsn=VB−2Vf−1 / 3xVB−2Vf

[0052] If this calculated value 2 / 3xVB - 2Vf exceeds the breakdown voltage Vz of the Zener diode Dz, the potential difference ΔVsn is maintained at ΔVsn = Vz. In this case, the gate voltage Vs becomes Vs = Vn + ΔVsn = 1 / 3xVB + Vz. Fig. Figure 5 shows a case where ΔVsn = Vz and Vs = 1 / 3xVB + Vz.

[0053] This means that even though the potential difference ΔVsn becomes 2 / 3xVB - 2Vf or Vz, whichever is smaller, since both are at least the relay drive voltage V0, each of the solid state relays 5U, 5V and 5W goes into the ON state.

[0054] Furthermore, when the output voltages Vv and Vw are at H level (VB), the output voltage Vu also goes to H level (VB), and the voltage (source voltage) Vn at the neutral point rises to VB.

[0055] Furthermore, the output voltage Vuc of the capacitor Cu is maintained at Vuc = VB - Vf, but the output voltages Vvc and Vwc of the capacitors Cv and Cw are increased by VB by charge pumps to VB - Vf + VB = 2VB - Vf, respectively.

[0056] Then the potential at the junction point uc of the downstream diodes Dud, Dvd and Dwd, that is, the gate voltage Vs, becomes Vs = VB - Vf + VB - Vf = 2VB - 2Vf.

[0057] Accordingly, the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn becomes ΔVsn = 2VB - 2Vf - VB = VB - 2Vf, but if this potential difference exceeds the breakdown voltage Vz of the Zener diode Dz, the potential difference is maintained at this breakdown voltage Vz.

[0058] Thus, even when one phase is driven at a duty cycle of 100% and the other phases are driven at duty cycles of less than 100%, the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn is maintained at least at the relay drive voltage V0, and each of the semiconductor relays 5U, 5V, and 5W is maintained in the ON state, so that the drive of the motor 4 can be continued.

[0059] Here, in Japanese Patent Application Laid-Open No. 2006-21645, since independent amplifier circuits are provided for respective phases, it becomes difficult to drive the motor in such an operating state in which one phase, for example, the U phase, is driven at a duty cycle of 100% or close to 100% and the other phases V and W are driven at lower duty cycles.

[0060] That is, when the U-phase is driven at a duty cycle of 100%, there is no low-level duration in the U-phase, the potential difference between the upper and lower sides of the upstream capacitor is kept low, and no charge pumping occurs. Furthermore, when the U-phase is driven at a duty cycle close to 100% with a short low-level duration, the charge and discharge amount of the upstream capacitor is small, and charge pumping becomes insufficient.

[0061] Consequently, in the U-phase, it is not possible to sufficiently increase the gate voltage Vs from the source voltage Vn, and a problem may occur that a U-phase solid-state relay is not turned on and a motor stops.

[0062] On the other hand, in the above-described embodiment, for example, when the U phase is driven at a duty cycle of 100%, since the input voltage Vu of the upstream capacitor Cu is maintained at VB, the output voltage Vuc is also maintained at VB - Vf. However, in other phases, which are the V phase and the W phase, the output voltage Vvc or Vwc is amplified due to charge pumping, by which discharge occurs when the input voltage Vv or Vw is at the L level (0 V) and charge occurs when the input voltage is at the H level (VB). Then, these amplified output voltages are commonly supplied to the U, V, and W phases, the semiconductor relay 5U is also maintained in the ON state, and the driving of the motor 4 can continue.

[0063] Fig. 6 shows potentials of different sections when the utilization levels of the phases of the inverter circuit 3 are different.

[0064] Also in this case, the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn can be maintained at least at the relay drive voltage V0, and the semiconductor relays 5U, 5V and 5W are kept in the ON state, so that the drive of the motor 4 can be continued.

[0065] On the other hand, in such a case where a power steering device needs to be manually operated, the CPU 1 outputs an H-level switching signal corresponding to a motor-off command to turn off a transistor Tr1 to stop the supply of a power supply voltage VB to the amplifier circuit 10. Consequently, electric charges are discharged from the capacitors Cu, Cv, and Cw, so that the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn of each of the semiconductor relays 5U, 5V, and 5W decreases to turn off the semiconductor relays 5U, 5V, and 5W, thereby stopping the drive of the motor 4.

[0066] Here, since operations of a plurality of semiconductor relays 5U, 5V, and 5W are stopped by a turn-off operation of a single switching circuit, change of stop timings of the plurality of semiconductor relays is prohibited, so that it is possible to prevent unintentional operation of the motor within a period from the turn-off operation to the stop of all the semiconductor relays 5U, 5V, and 5W of the respective phase to prevent deterioration of the steering performance (operability).

[0067] Fig.7 is a detailed circuit diagram of a second embodiment of the above-described motor drive control device. The second embodiment provides a circuit similar to that of Embodiment 1. In the second embodiment, the circuit includes a transistor Tr2 as a switching circuit for stopping the boosting function of a boosting circuit for turning off a motor. A corrector terminal of the transistor Tr2 is connected to a point between a resistor r11 and a resistor r12, an emitter terminal thereof is grounded, and a base terminal thereof is configured to receive a switching signal from the CPU 1.

[0068] When the motor 4 is normally driven, the base terminal of the transistor Tr2 is kept at an L level to turn the transistor Tr2 off to drive the motor 4, while activating the amplifier circuit 10. The operation is similar to that during normal operation of the motor (when the transistor Tr1 is on) in the first embodiment.

[0069] Furthermore, when a switching signal with an H level corresponding to a motor turn-off command is output from the CPU 1, the transistor Tr2 is turned on, and an electric charge stored in the downstream capacitor Cd is discharged. Consequently, the potential difference ΔVsn between the gate voltage Vs and the source voltage Vn of each of the solid-state relays 5U, 5V, and 5W decreases to turn off the solid-state relays 5U, 5V, and 5W, thereby stopping the drive of the motor 4.

[0070] Furthermore, also in the second embodiment, when the apparatus is applied to a power steering apparatus, since operations of a plurality of semiconductor relays 5U, 5V, and 5W are stopped by a turn-off operation of a single switching circuit, a change in stop timings of the plurality of semiconductor relays is inhibited, so that it is possible to inhibit unintentional operation of the motor within a period from the turn-off operation to the stopping of all the semiconductor relays 5U, 5V, and 5W of the respective phases to inhibit deterioration of the steering performance (operability).

[0071] Further, in the second embodiment, since an off position of the switching circuit 11 is close to the semiconductor relays 5U, 5V, and 5W, it is possible to reduce a stop delay time of the semiconductor relays.

[0072] Furthermore, in the above-described embodiments, since the downstream capacitor Cd is connected to the neutral point of the motor 4 at which the voltage varies, an electric charge supplied from the inverter circuit 3 is suppressed, and it is possible to reduce a charging time for the capacitor Cd to suppress an activation start delay of the semiconductor relays 5.

[0073] Here, the structure can be such that the semiconductor relays 5U, 5V and 5W are connected between output terminals of the U, V and W phases of the inverter circuit 3 and input terminals of the U, V and W phases of the motor 4.

[0074] Furthermore, the circuit of the above-described embodiment has output lines of the three phases U, V and W connected to the amplifier circuit to control the solid-state relays for the three phases, and the circuit is configured to turn off the solid-state relays of the three phases when the motor turns off, and thus it is possible to turn off the motor with high responsiveness.

[0075] Here, the structure can be such that the output lines of two of the three phases U, V, and W are connected to the amplifier circuit, and the circuit is configured to control the solid-state relays for the corresponding two phases. In this case, it is possible to turn off the two phases to turn off the motor, thus simplifying the structure and reducing costs.

[0076] Furthermore, the present invention is applicable to an n-phase motor having at least three phases, and it is possible to turn off the motor by turning off the (n-1) phases.

Claims

[1] A motor drive control device comprising an inverter circuit (3) having n (equal to or greater than 3) phases, the output lines (Vu, Vv, Vw) of respective phases of which are connected to respective phases (U, V, W) of an n-phase motor (4), and which controls the drive of the motor (4) based on an output signal of the inverter circuit (3); the motor drive control device comprising: an amplifier circuit (10) connected to the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3) and amplifying output signals of the output lines; Semiconductor relays (5U, 5V, 5W) interposed in respective phases of the motor (4), which are connected to the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3), and which are adapted to receive the output signals amplified by the amplifier circuit (10) and distributed as relay motor drive signals at a time of driving the motor; characterized by a switching circuit (11) which stops an operation of the amplifier circuit (10) and switches off the semiconductor relays (5) to switch off the drive of the motor, wherein the amplifier circuit (10) comprises: at least (n-1) pieces of diodes (Duu, Dvu, Dwu) interposed in a power (VB) supply line for the amplifier circuit (10) at a position upstream of connection points with the output lines of at least (n-1) phases of the inverter circuit (3); and a capacitor (Cd) for storing an electric charge, one end of which is connected to the output end of the diodes (Duu, Dvu, Dwu), the other end of the capacitor (Cd) being connected to a neutral point to which the phases of the motor (4) are connected. [2] Motor drive control device according to claim 1, characterized by that the switching circuit (11) is interposed in the energy (VB) supply line for the amplifier circuit (10). [3] Motor drive control device according to claim 1, characterized bythat the switching circuit (11) is interposed in a line for discharging the electrical charge stored in the capacitor. [4] Motor drive control device according to one of claims 1 to 3, characterized by that the amplifier circuit (10) comprises: a Zener diode (Dz) connected in parallel with the capacitor and limiting a voltage between the terminals of the capacitor to a maximum of a predetermined voltage. [5] Motor drive control device according to one of claims 1 to 4, characterized by that the amplifier circuit (10) further comprises: at least (n-1) upstream capacitors (Cu, Cv, Cw) for storing an electric charge, which are interposed in the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3) on the upstream side of the connection points with the diodes; and downstream diodes (Dud, Dvd, Dwd) of at least (n-1) phases connected to the downstream side of the capacitors (Cu, Cv, Cw), wherein the output terminals of the downstream diodes (Dud, Dvd, Dwd) are connected to each other at a connection point and the output signal at the connection point is distributed to the semiconductor relays (5U, 5V, 5W). [6] Motor drive control device according to one of claims 1 to 5, characterized bythat the semiconductor relays (5U, 5V, 5W) are interposed between the output sides of the respective phases of the motor (4), which are connected to the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3), and a neutral point to which the phases of the motor (4) are connected. [7] Motor drive control device according to one of claims 1 to 5, characterized by that the semiconductor relays (5U, 5V, 5W) are interposed between the output lines (Vu, Vv, Vw) of at least (n-1) phases of the inverter circuit (3) and the at least (n-1) phases of the motor (4). [8] Motor drive control device according to one of claims 1 to 7, characterized by that the output lines (Vu, Vv, Vw) of all three phases U, V and W of the inverter are connected to the amplifier circuit (10). [9] Motor drive control device according to one of claims 1 to 8, characterized bythat the output lines (Vu, Vv, Vw) of two of the three phases U, V and W of the inverter are connected to the amplifier circuit (10). [10] Motor drive control device according to one of claims 1 to 9, characterized by that the motor (4) is a motor for driving an electric power steering device of a vehicle.

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