Digital circuit for generating a pulse-width modulated signal, especially for controlling an analog quantity

Abstract

A digital circuit arrangement for generating a pulse-width modulated signal, in particular for controlling an analog electrical quantity by means of pulse-width modulation, wherein an actual value of the analog quantity present at the input of an A / D converter (105) is converted into a digital output quantity, wherein the digital output quantity of the A / D converter (105) is supplied to a comparator unit (115, 125) which compares the output quantity with an upper threshold value (120) and with a lower threshold value (130), and wherein a signal is present at the output (135, 140) of the comparator unit (115, 125) which indicates whether the output quantity of the A / D converter (105) is above the upper threshold value (120) or below the lower threshold value (130), characterized in that the output of the A / D converter (105) is connected to a digital timer (215) by means of which the The pulse width ratio of a generated pulse-width modulated signal is adjustable.

Description

[0001] The invention relates to a digital circuit arrangement for generating a pulse-width modulated signal, in particular for controlling an analog quantity, according to the preambles of the independent claims. State of the art

[0002] The generation of an analog electrical quantity, such as voltage or current, by integrating a digitally switched, pulse-width modulated (PWM) signal is a well-known principle in DC / DC converters or switching regulators. This involves the use of a switch, a memory element, and a specific control circuit, with such control circuits available in various designs, mostly as integrated circuits. The aforementioned memory element is, for example, an electrical inductor or capacitor.

[0003] From EP 1 943 567 B1 a transmission element with at least one input (E) and at least one output (A) is known, wherein • the transfer element provides a functional relationship (t = F(R)) between the input quantity (R) applied to the input and the output quantity (t) that can be tapped at the output, • the functional relationship (t = F(R)) is stored in a characteristic map (7), • the characteristic map (7) consists of several areas (bi) each with a lower limit (N(bi)), an upper limit (N(bi+1)), a starting value (K(bi)), an ending value (E(bi)) and a slope value (P(bi)), where the lower limit (N(bi)) is assigned a function value (t(i)=F(N(bi))) and the upper limit (N(bi+1)) is assigned a function value (t(i+1)=F(N(bi+1))), • the transmission element comprises a delta-sigma converter (1) with a quantizer (3) and an integrator (4), wherein the digitized input quantity (R) is present at the output (6) of the integrator (4), • using the digitized input variable (R) from the characteristic map (7) a range (bi) is selected and the respective start value (K(bi)), end value (E(bi)) and slope (P(bi)) are used to calculate the manipulated variable in such a way that the output variable (t) is interpolated between the lower limit and the upper limit of the selected range (bi). Disclosure of the invention

[0004] The present invention is based on the idea of ​​controlling a specified analog electrical quantity (voltage, current, etc.) by means of pulse width modulation, and in particular by linking an analog-to-digital converter (ADC) with a digital timer. The so-called "embedded" microcontrollers available today, which are used, for example, to control electric motors in electric vehicles, already include the aforementioned ADCs and timers, so that the inventive linking of an ADC with a digital timer, and in particular the construction of a direct control loop controlled and realized exclusively by electronic components, is simple and therefore cost-effective to implement.

[0005] With a digital circuit arrangement according to the invention, an analog quantity can be controlled or regulated using only a few external components. Since the actual control process does not require continuous instruction execution by the microcontroller, the dead time of the circuit is significantly reduced. Furthermore, only very low jitter (fluctuation) of the dead time is to be expected. If the control loop is closed by instruction execution by a microcontroller, the time required for executing the instructions leads to a significantly larger dead time. If the microcontroller also has other tasks, which is usually the case in practice, this results in considerable jitter of the dead time, which is very disruptive in a control loop. Compared to the prior art of today's microcontrollers, where signal processing is carried out by software, which, due to the necessary data processing, is subject to runtime or...The discrete design of the circuit arrangement according to the invention, which uses a microcontroller instead of a microcontroller, avoids the aforementioned disadvantages caused by dead-time effects and jitter.

[0006] Furthermore, the microcontroller is thus relieved of some of its workload and is therefore available for other tasks. The microcontroller's programmability can also be used to adjust the control parameters or adapt them to current requirements.

[0007] Thanks to the invention, the control system described here can be implemented using integrated logic structures already present in a (e.g., embedded) microcontroller. This is particularly relevant for systems where microcontrollers are used to minimize the number of externally required components.

[0008] The invention can be used in particular in electric drives and / or battery supplies of electric vehicles or in electric inverters with the advantages described herein.

[0009] Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings. It is understood that the features mentioned above and those to be explained below can be used not only in the respective combinations specified, but also in other combinations or individually, without departing from the scope of the present invention. Brief description of the drawings Fig. Figure 1 shows a circuit arrangement of a digital comparator for threshold monitoring according to the state of the art. Fig. Figure 2 shows a first embodiment of a digital circuit arrangement according to the invention for adjusting the pulse width ratio of a pulse width modulated (PWM) signal. Fig. Figure 3 shows a second embodiment of a circuit arrangement according to the invention for adjusting the pulse width ratio of a PWM signal. Fig. Figure 4 shows a further embodiment of a circuit arrangement according to the invention for adjusting the pulse width ratio of a PWM signal. Description of exemplary implementations

[0010] The one in Fig. The first part of the entire circuit arrangement shown in Figure 1 is known in the prior art. The entire circuit arrangement is obtained by combining the first circuit part with a second circuit part according to the diagram. Fig. 2 or Fig. 3.

[0011] The in Fig. The first circuit section shown in Figure 1 comprises an analog-to-digital (A / D) converter 105, which converts an analog input signal applied to its analog input 100—in this case, an actual value of a controlled variable represented as an electrical voltage or current value—into a digital output signal. As is also known per se, a sampling rate for digitizing the analog signal 100 is supplied to the A / D converter via a separate input 110. The numerical value of the digital output signal of the A / D converter is directly proportional to the analog input signal.

[0012] The digital output of the A / D converter 105 is fed to a first digital comparator 115, which compares the value of the output with an upper threshold 120 and, preferably essentially simultaneously, via a second digital comparator 125 with a lower threshold 130. As a result of these two comparison operations, one of the following three pieces of information or a corresponding digital signal is present at the output 135, 140 of the respective comparator 115, 125: The value of the output variable of the A / D converter 105 is a. above the upper threshold of 120; b. below the lower threshold of 130; c. between the lower threshold of 130 and the upper threshold of 120.

[0013] The aforementioned possible information a. - c. each serves as input data or input variables 135, 140 of the in the Fig. 2 and Fig. 3 shown circuit arrangements according to the invention, which connect the said A / D converter 105 and the comparator or comparators 115, 125 with each a timer unit 215, 320, which can generate said PWM signals, in such a way that the pulse width ratio of the PWM signal present at the output 225, 330 of the respective circuit is adjustable.

[0014] At the in Fig. In the first embodiment of the circuit arrangement according to the invention shown in Figure 2, the input variables 135, 140 are first fed to a state-controlled, bistable flip-flop 200. In this embodiment, the flip-flop 200 is a known flip-flop of the type "RS-FF" (i.e., reset / set or reset-set). Depending on the value of the variable applied to the flip-flop 200, which signals either exceeding the upper threshold (case a. above) or falling below the lower threshold, the flip-flop 200 or its output selects a PWM signal with a first pulse width ratio of x% 205 in the first case, whereas in the second case (case b. above), a PWM signal with a second pulse width ratio of y% 210 is selected.

[0015] The selected pulse width ratio, as described, is supplied to a timer 215 together with a clock signal 220. In the present embodiment, the timer 215 is configured as a "capture / compare unit", i.e., it has the following operating modes: 1. 'Timer mode': Counting up using various sources as clocks. An interrupt can be triggered if the counter overflows. 2. 'Capture Mode': When an external signal occurs, the contents of the assigned (running) timer are saved. An interrupt can also be triggered here. 3. 'Compare Mode': The counter value of the assigned timer is compared with that of a register. If they match, an interrupt can be triggered.

[0016] To generate a PWM signal, the compare mode is used: When the value exceeds the compare value (in 205 or 210), the counter outputs a logic 1 as its output signal (225), for example, when the compare value is exceeded and a logic 0 when it falls below the compare value. The ratio of the duration of the logic 1 to the duration of a complete counter cycle is thus proportional to the compare value. In the method according to the invention, the timer signal is therefore influenced depending on the applied analog quantity. The results of the aforementioned comparison thus already provide a sufficiently good pulse width ratio, so that the switching, which only takes place between two states, and the corresponding timer signal enable a coarser control loop compared to the prior art. A corresponding pulse-width modulated signal is therefore present at the digital output 225 of the present circuit arrangement.

[0017] If the counter is not used in compare mode, then, for example, an output signal (225) can be generated that provides the information ">" or "<" immediately or after a variable delay time as digital information.

[0018] At the in Fig. In the second embodiment of the circuit arrangement according to the invention shown in Figure 3, the input variables 135 and 140 are first fed to an adder / subtractor 300. The signal 135 supplied by the upper comparator 115 is fed to the subtraction input (-) of the adder 300, and the signal 140 supplied by the lower comparator 125 is fed to the addition input (+) of the adder 300. Additionally, the adder 300 is supplied with a sampling rate 305 (typically identical to 110) required for digitizing the analog signal 100, as well as a predetermined step size 310 for changing the pulse width ratio.

[0019] If the upper threshold of 120 is exceeded (case a. above), the pulse width ratio 315 is reduced by the amount of the specified step size 310, whereas if the lower threshold of 130 is not reached (case b. above), the pulse width ratio is increased by the step size 310. It should be noted that the step size 310 is freely configurable in both cases (cases a. and b. above).

[0020] The modified pulse width ratio 315 is then fed, together with a clock signal 325, to a timer 320, which in this embodiment is also designed as a "capture / compare unit" and therefore possesses the functionality described above. A correspondingly pulse-width modulated signal is present at the digital output 330 of the circuit arrangement. One advantage of the second embodiment over the first embodiment ( Fig. 2) The advantage lies in the fact that the pulse width ratio can be tracked across the entire possible range of 0% to 100% of the manipulated variable (analog signal) without intervention from the microcontroller, whereas in the first embodiment, only two pulse width ratios are used for switching. Changing these two pulse width ratios, however, requires the microcontroller to execute a command. Using the timer, the pulse width ratio can be decreased or increased in very small steps, depending on whether the analog signal is larger or smaller.

[0021] According to a third embodiment of the circuit arrangement according to the invention (not illustrated in the figures), the result of the A / D converter is transferred to a timer unit and compared there with a predetermined value. This embodiment is particularly advantageous if the microcontroller used does not already have threshold monitoring (as assumed in the preceding embodiments). In this case, compare units present in the timer module can be used instead of comparing a counter value against the transmitted analog value, as is usually the case. The further design is essentially identical to the first two embodiments, except that the comparators 115, 125 and comparison thresholds 120, 130 of the A / D converter shown there are implemented in the timer module.

[0022] According to a Fig. In the fourth embodiment of the circuit arrangement according to the invention, shown in Figure 4, the pulse width ratio is changed by direct derivation from the deviation of the result of a (in the upper half of Fig. The analog-to-digital converter (ADC) 400 (as shown in Figure 4) is used to measure the actual value of an analog control variable 410 from a predetermined setpoint 405. The inputs to the ADC 400 are an actual value 410 of an analog control variable applied to an analog input and a previously mentioned sampling rate (“sample clock”) 415. The (digital) output 425 of the ADC 400 then displays either a positive or negative difference value. This deviation is determined by a subtractor 420. On the digital side of the ADC 400, the signal exchange and processing between the ADC, the subtractor 420, and the setpoint generator 405 takes place digitally using binary signals (referred to here as “n bits”).

[0023] In this embodiment, therefore, there is no two-point control, but rather a direct control around a mean value.

[0024] In the lower half of Fig. At position 4, there is a timer module, which is formed by a capture-compare timer 430. This timer is operated as described above by means of a clock signal (“timer clock”) 435 and a pulse width modulation (PWM) 440. Additionally, an adder 445 is arranged, which is operated by means of a supplied sampling rate 450 and a step size encoder 455 that provides a step size. The input signal for the adder 445 is the bit signal (“n bits”) supplied by the subtractor 420. The signal exchange and processing between the timer 430, the pulse width encoder 440, the adder 445, and the step size encoder 455 is digital and uses binary signals (here referred to as “m bits”). Finally, a pulse-width modulated signal is present at the (digital) output 460 of the timer 430 and thus of the entire circuit arrangement.

[0025] The additional logic required for the aforementioned setpoint comparison, which is not standard in microcontrollers, includes some of the logic in Fig. 4 logic components shown, namely the setpoint generator 405, the subtractor 420, the step size generator 455 and the adder 445.

[0026] The fourth embodiment can (in Fig. (4 not shown) can be made even more flexible by adding half (a quarter, an eighth, etc.) or double (four times, eight times, etc.) the difference to the current value of the pulse width ratio by appropriately (selectably) shifting the determined difference from the current A / D value by 1 or more bit(s) to the right or to the left.

[0027] As a result, the described A / D conversion, due to the discrete functional elements, delivers a numerical value that is not only compared with a threshold value – as in the prior art – but is transmitted in its entirety to a timer and compared with a value. That is, according to the invention, the A / D converter already implemented in conventional microcontrollers is replaced by the aforementioned timer.

Claims

[1] Digital circuit arrangement for generating a pulse-width modulated signal, in particular for controlling an analog electrical quantity by means of pulse-width modulation, wherein an actual value of the analog quantity present at the input of an A / D converter (105) is converted into a digital output quantity, wherein the digital output quantity of the A / D converter (105) is supplied to a comparator unit (115, 125) which compares the output quantity with an upper threshold value (120) and with a lower threshold value (130), and wherein a signal is present at the output (135, 140) of the comparator unit (115, 125) which indicates whether the output quantity of the A / D converter (105) is above the upper threshold value (120) or below the lower threshold value (130), characterized by , that the output of the A / D converter (105) is connected to a digital timer (215) by means of which the pulse width ratio of a generated pulse width modulated signal can be adjusted. [2] Circuit arrangement according to claim 1, characterized by , that the timer (215) is formed by a Generic Timer Module (GTM) or a Capture / Compare unit. [3] Circuit arrangement according to claim 1 or 2, characterized by , that the comparator unit (115, 125) is formed by a first digital comparator (115) and at least one second digital comparator (125). [4] Circuit arrangement according to one of the preceding claims, characterized by , that the first digital comparator (115) and the at least second digital comparator (125) operate essentially simultaneously. [5] Circuit arrangement according to claim 3 or 4, characterized by, that the signals present at the output (135, 140) of the comparator unit (115, 125) are fed to a bistable flip-flop (200), which, depending on the value of the signal applied to the flip-flop (200), selects a pulse-width modulated signal with a first pulse width ratio (205) or a pulse-width modulated signal with a second pulse width ratio (210). [6] Circuit arrangement according to claim 3 or 4, characterized by , that the signals present at the output (135, 140) of the comparator unit (115, 125) are fed to an adder / subtractor (300), which, depending on the value of the signal present at the adder / subtractor (300), reduces or increases the pulse width ratio (315) by a predetermined step size (310). [7] Circuit arrangement according to claim 6, wherein the comparator unit (115, 125) is formed by a first digital comparator (115) and at least one second digital comparator (125), characterized by, that a signal (135) supplied by the first comparator (115) is fed to the subtraction input of the adder / subtractor (300), that a signal (140) supplied by the at least second comparator (125) is fed to the addition input of the adder / subtractor (300), that a sampling rate (305) is supplied to the adder / subtractor (300), and that a predetermined step size (310) is supplied to the adder / subtractor (300) to change the pulse width ratio. [8] Circuit arrangement according to one of the preceding claims, characterized by, that the signal present at the output of the A / D converter (105) is compared with a predetermined value using the digital timer (215) and, depending on the result of the comparison, either a first pulse-width modulated signal with a first frequency and a first pulse width is output or a second pulse-width modulated signal with a second frequency and a second pulse width. [9] Circuit arrangement according to one of the preceding claims, characterized by , that the pulse width ratio is set based on the duty cycle (pulse duration to pulse period) and depends on a predefined threshold. [10] Circuit arrangement according to one of the preceding claims, characterized by, that a change in the pulse width ratio is achieved by means of a deviation of the result of an A / D converter (400) from a predetermined setpoint (405), wherein the deviation of the result (425) is supplied to a timer (430) which is operated by means of a correspondingly changed pulse width ratio (440).

Images