Method for removing vacancy agglomerates from a crystalline silicon body

Abstract

Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) by forming a polysilicon layer (1020) on at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101), wherein a surface roughness of the polysilicon layer (1020) is greater than a surface roughness of at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101); Forming an oxide layer by oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and Removal of the polysilicon layer (1020).

Description

BACKGROUND

[0001] Semiconductor devices, particularly field-effect controlled switching devices such as junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated-gate bipolar transistors (IGBTs), are typically used in various applications, including but not limited to switches in power supplies and converters, electric vehicles, and air conditioning systems. Such semiconductor devices are typically fabricated at the wafer level. As wafer size increases, the manufacturing cost per chip typically decreases. Larger silicon wafers, i.e., silicon wafers with a diameter of at least 12 inches (30.5 cm), are currently only available as magnetic Czochralski-grown silicon wafers. Silicon wafers with a diameter of 8 inches (20.3 cm) are also available as float-zone (FZ)-grown silicon wafers, but are comparatively expensive.These devices are complex and can exhibit a comparatively large variation in resistance due to grooves. Exemplary semiconductor devices and manufacturing processes are known from publications US 4 874 484 B2, US 5 902 135 B2, US 2004 / 0 002 200 A1, DE 10 2006 002 903 A1 and US 2003 / 0 051 660 A1.

[0002] During single-crystal growth using the Czochralski (CZ) method, crystal defects such as vacancy agglomerates (COPs; crystal-originated particles) or dislocation rings are formed. Agglomerated vacancy-correlated defects are commonly known as D-defects or COPs. Such defects can facilitate the formation of origination centers in the wafer, resulting in increased leakage current, and weaken subsequently formed gate dielectrics.

[0003] Accordingly, there is a need to remove vacancy agglomerates from a crystalline silicon body.

[0004] It is therefore an object of the present invention to provide a method that satisfies the above requirements.

[0005] This problem is solved according to the invention by a method with the features of claim 1. Advantageous embodiments of the invention are set forth in the dependent claims. SUMMARY

[0006] One embodiment relates to a method for removing vacancy agglomerates from a crystalline silicon body having opposing first and second surfaces. The method comprises increasing the surface area of ​​at least one surface from the first and second surfaces. The method further comprises oxidizing the increased surface area at a temperature of at least 1000°C for a duration of at least 20 minutes.

[0007] The expert will recognize additional features and advantages after reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are enclosed to provide a further understanding of the invention and are incorporated into the disclosure of the invention and form part thereof. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the invention. Other exemplary embodiments and intended advantages are immediately acknowledged, as they are better understood with reference to the following detailed description. Fig. Figure 1 is a schematic process diagram illustrating a method for removing vacancy agglomerates from a crystalline silicon body. Fig. 2A and Fig. Figure 2B are schematic cross-sectional views illustrating a method for enlarging a surface area of ​​a crystalline silicon body by forming a polysilicon layer on a surface of the crystalline silicon body. Fig. Figure 3 is a schematic cross-sectional view illustrating a method for enlarging a surface area of ​​a crystalline silicon body by forming a porous layer on a surface of the crystalline silicon body. Fig. Figure 4 is a schematic cross-sectional view illustrating a method for enlarging a surface area of ​​a crystalline silicon body by irradiating a surface of the crystalline silicon body with a laser irradiation. Fig. Figure 5 is a schematic cross-sectional view illustrating a method for enlarging a surface area of ​​a crystalline silicon body by a machining process. Fig. Figure 6 is a schematic sectional view illustrating a method for enlarging a surface area of ​​a crystalline silicon body by a masked etching process. Fig. Figures 7A to 7D are schematic cross-sectional views illustrating methods for enlarging a surface area of ​​a crystalline silicon body by forming trenches. Fig. Figures 8A to 8D are schematic top views of a crystalline silicon body incorporating various trench configurations. Fig. 9A and Fig. Figure 9B shows schematic cross-sectional views of a crystalline silicon body after filling trenches with a doped material and diffusion of dopants into the crystalline silicon body. Fig. Figures 10A to 10H illustrate front-end-of-line (FEOL) and back-end-of-line (BEOL) processing after processing the crystalline silicon body, as described in Fig. 1 shown. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings, which form part of the disclosure and show specific embodiments for illustrative purposes in which the invention can be carried out. It is understood that other embodiments can be used and structural or logical modifications can be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment can be used in or in conjunction with other embodiments to arrive at yet another embodiment. It is intended that the present invention encompasses such modifications and changes. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements are marked with corresponding reference symbols in the various drawings, unless otherwise stated.

[0010] The terms "have," "contain," "comprise," "exhibit," and similar terms are open-ended, indicating the presence of the identified structures, elements, or features, but not the presence of additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise.

[0011] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal transmission may be present between the electrically coupled elements, for example, elements that temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0012] The figures illustrate relative doping concentrations by specifying “ - " or " + “Next to the doping type “n” or “p”. For example, “n” means -“a doping concentration that is lower than the doping concentration of an “n” doping range, while an “n + A doping area has a higher doping concentration than an "n" doping area. Doping areas with the same relative doping concentration do not necessarily have the same absolute doping concentrations. For example, two different "n" doping areas can have the same or different absolute doping concentrations.

[0013] The term "horizontal," as used in this description, is intended to describe an orientation essentially parallel to a first or main surface of a semiconductor substrate or body. This could be, for example, the surface of a wafer, a die, or a chip.

[0014] The term “vertical”, as used in the present description, is intended to describe an orientation that is essentially perpendicular to the first surface, i.e. parallel to the normal direction of the first surface of the semiconductor substrate or body.

[0015] In this description, a second surface of a semiconductor substrate or semiconductor body is considered to be formed by the lower or backside surface, while the first surface is considered to be formed by the upper front or main surface of the semiconductor substrate. The terms "above" and "below," as used in this description, therefore describe a relative localization of one structural feature to another with respect to this orientation.

[0016] The term "vacancy agglomerate" (COPs), as used in this description, refers to a void within the semiconductor material, typically formed by an agglomeration of vacancies during crystal growth, and may include an outer silicon oxide shell. The risk of slip line formation in the semiconductor substrate typically increases with the concentration and size of the COPs. Furthermore, COPs decorated with diffusing heavy metals, such as Fe, Cu, and Ni, can act as generation centers, increasing leakage current from the devices. The diameter of the COPs is typically below approximately 100 nm, and even more typically below 80 nm.

[0017] In this description, n-doped refers to a first conductivity type, while p-doped refers to a second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type n-doped. Furthermore, some figures illustrate relative doping concentrations by specifying “ - " or " + “next to the doping type. For example, “n” means - “a doping concentration that is lower than the doping concentration of an “n” doping range, while an “n +The “-doping range has a higher doping concentration than the “n” doping range. However, specifying the relative doping concentration does not mean that doping ranges with the same relative doping concentration must have the same absolute doping concentration unless otherwise stated. For example, two different “n” + Doping ranges have different absolute doping concentrations. The same applies, for example, to an n + -doping- and a p + -Doping range.

[0018] Specific embodiments described in this description relate, but are not limited to, semiconductor devices, in particular field-effect semiconductor transistors, and manufacturing processes for them. In this description, the terms "semiconductor device" and "semiconductor component" are used synonymously. The semiconductor device typically comprises a field-effect structure. The field-effect structure can be a MOSFET or an IGBT structure, which has a pn junction forming a body diode between a drift region of the first conductivity type and a body region of the second conductivity type.The semiconductor device is typically a vertical semiconductor device with two load metallizations, for example, a source metallization and a drain metallization for a MOSFET, which are oriented opposite to each other and in low-resistance contact with their respective contact areas. The field-effect structure can also be formed by a JFET structure.

[0019] For example, the semiconductor device is a power semiconductor device that has an active region with, for example, a plurality of IGBT cells or MOSFET cells to conduct and / or control a load current between the two load metallizations. Furthermore, the power semiconductor device typically has a peripheral or edge region with at least one edge termination structure that at least partially surrounds the active region when viewed from above.

[0020] The term "power semiconductor device," as used in this description, is intended to describe a semiconductor device on a single chip with high-voltage and / or high-current switching capabilities. In other words, the power semiconductor devices are designed for high currents, typically in the range of 10 amperes to several kA. Within this description, the terms "power semiconductor device" and "power semiconductor component" are used synonymously.

[0021] The term "field effect," as used in this description, refers to the formation of a conducting "channel" of a first conductivity type mediated by the electric field, and / or the control of the conductivity, and / or the shaping of the channel between two regions of the first conductivity type. The conducting channel can be formed and / or controlled in a semiconductor region of the second conductivity type, in particular a body region of the second conductivity type located between the two regions of the first conductivity type. Due to the field effect, a unipolar current path is formed through the channel region and / or controlled between a source region or an emitter region of the first conductivity type and a drift region of the first conductivity type, respectively, in a MOSFET structure and an IGBT structure.The drift region can be in contact with either a more heavily doped drain region of the first conductivity type or a more heavily doped collector region of the second conductivity type. The drain region or collector region is in low-resistance electrical contact with a drain or collector electrode, respectively. The source region or emitter region is in low-resistance electrical contact with a source or emitter electrode, respectively. In a JFET structure, the channel region is typically formed by a portion of the first conductivity-type drift region, located between a gate region and a second conductivity-type body region, and can be controlled by changing the width of a depletion layer formed between the gate region and the channel region.

[0022] In the context of this description, the term "MOS" (metal-oxide semiconductor) should be understood to include the more general term "MIS" (metal-insulator semiconductor). For example, the term MOSFET (metal-oxide semiconductor field-effect transistor) should be understood to include FETs that have a gate insulator that is not an oxide; that is, the term MOSFET is used in the more general sense of both IGFET (isolated-gate field-effect transistor) and MISFET (metal-insulator semiconductor field-effect transistor), respectively.

[0023] In the context of this description, the term "gate electrode" is intended to describe an electrode located closest to a channel region and configured to form and / or control it. The term "gate electrode" is intended to encompass an electrode or conductive region located closest to the body region and insulated from it by an insulating region, forming a gate dielectric region and configured to form and / or control a channel region through the body region by charging it with a suitable voltage.

[0024] For example, the gate electrode can be designed as a trench gate electrode, i.e., a gate electrode arranged in a trench extending from the main surface into the semiconductor substrate or semiconductor body. The gate electrode can also be designed as a planar gate electrode.

[0025] A unit cell of an active region of a power field-effect transistor device can, in a horizontal section, comprise a trench-gate electrode and a surrounding part of a mesa if the trench-gate electrodes form a two-dimensional grid, for example in the shape of a chessboard when viewed from above.

[0026] Alternatively, the unit cell of the active region of a power field-effect semiconductor device, viewed from above in a horizontal section, can comprise a trench-gate electrode and a respective portion of two adjacent mesas. In these embodiments, trench-gate electrodes, mesas, and unit cells can each form one-dimensional grids.

[0027] In the context of the present description, the term “mesa” or “mesa region” is intended to describe a semiconductor region that is located in a vertical section close to and typically between two adjacent trenches extending into the semiconductor substrate or semiconductor body.

[0028] The conductive regions forming the gate electrode and field electrode, respectively, can be made of a material with sufficiently high electrical conductivity to create an equipotential region during device operation. For example, the conductive region can be made of a material with metallic or near-metallic electrical conductivity, such as a metal (e.g., tungsten), highly doped polysilicon, a silicide, or the like. Typically, the conductive region is in resistive electrical contact with the gate metallization of the semiconductor device. The insulating region can be made of any suitable dielectric material, such as silicon dioxide (e.g., thermal silicon dioxide), silicon nitride, silicon oxynitride, or the like.

[0029] In the context of this description, the term "metallization" shall be understood to describe any region or layer with metallic or near-metallic electrical conductivity. A metallization may be in contact with a semiconductor region to form an electrode, pad, and / or terminal of the semiconductor device. The metallization may be made of and / or comprise a metal such as Al, Ti, W, Cu, and Co, and may also be made of a material with metallic or near-metallic electrical conductivity, such as highly doped n-type or p-type poly-Si, TiN, or an electrically conductive silicide such as TaSi₂, TiSi₂, PtSi, CoSi₂, WSi₂, or the like. The metallization may also comprise various electrically conductive materials, for example, a stack of such materials.

[0030] Fig. Figure 1 is a schematic process diagram illustrating a method for removing COPs from a crystalline silicon body.

[0031] A process feature S100 includes increasing or enlarging a surface area of ​​at least one surface from first and second surfaces of a crystalline silicon body.

[0032] A process feature S200 comprises oxidizing the enlarged surface area at a temperature of at least 1000°C, or even at least 1050°C, or even at least 1100°C, for a duration of at least 20 minutes, or even at least one hour. According to one embodiment, the oxidation is carried out in a wet environment.

[0033] According to one embodiment, the crystalline silicon body is a silicon wafer. The silicon wafer can be a Czochralski (CZ) wafer, for example, grown by the standard CZ process, the magnetic CZ (MCZ) process, or the continuous CZ (CCZ) process. The CZ wafer can serve as a base material for fabricating a variety of semiconductor devices and integrated circuits, such as power semiconductor devices and solar cells.

[0034] During the oxidation of silicon, interstitial silicon atoms are generated at the oxidizing surface and diffuse into the crystalline silicon body. These interstitial silicon atoms, migrating into a body or volume of the crystalline silicon, occupy vacancies in the crystal lattice, thereby dissolving COPs by filling accumulations of vacancies or voids within the COPs. The process can also lead to the rupture or dissolution of an oxide layer lining the inner surface of the COPs.

[0035] By increasing the surface area of ​​at least one surface from the first and second surfaces of the crystalline silicon body, the number of interstitial silicon atoms produced during oxidation can be increased, leading to a more effective resolution of the COPs due to an increased concentration of interstitial silicon atoms; i.e., the required oxidation temperature can be reduced, for example, from 1100°C to 1000°C or 1050°C and / or the duration of the oxidation can be reduced to, for example, half the time.

[0036] According to one embodiment, the process of oxidizing the enlarged surface area involves a moist / wet oxidation process. For example, the crystalline semiconductor body can be oxidized in moist air. According to another example, the crystalline semiconductor body can be oxidized in an oxygen-containing gaseous doping compound. Phosphorus oxytrichloride (POCl3) is an example of such an oxygen-containing compound.

[0037] According to one embodiment, the duration of the oxidation process of the enlarged surface area is between 1 hour and 5 hours or between 2 and 4 hours.

[0038] According to one embodiment, the process of oxidizing the enlarged surface area is carried out in a temperature range between 1000°C and 1300°C. For example, the oxidation can be carried out at a temperature between 1080°C and 1180°C, e.g., around 1150°C for POCl3 diffusion. According to another embodiment, after oxidation with phosphorus oxytrichloride, phosphorus-doped zones created by diffusion with POCl3 can be removed, for example, by an etching process.

[0039] Referring to the schematic sectional view of a in Fig. Figure 2A illustrates an embodiment of a process for increasing the surface area of ​​the crystalline silicon body 101 by forming a first polysilicon layer 1020 on a first side 1030 of a crystalline silicon substrate 104, for example, a CZ silicon wafer. Since the surface roughness of the first polysilicon layer 1020 on a first surface 1050 of the crystalline silicon body 101 is greater than the surface roughness on the first side 1030 of the crystalline silicon substrate 104, the surface area of ​​the crystalline silicon body 101 is increased. For example, the first polysilicon layer 1020 can be formed by a chemical vapor deposition (CVD) process, e.g. by atmospheric pressure chemical vapor deposition (APCVD) and / or by low pressure chemical vapor deposition (LPCVD).The enlarged surface area of ​​the first surface 1050 of the crystalline silicon body 101 compared with the surface roughness at the first side 1030 of the crystalline silicon substrate 104 is based on a composition of a number of randomly assigned crystallites of silicon in the first polysilicon layer 1020, which determines the surface area at the first surface 1050 of the crystalline silicon body 101.

[0040] According to one embodiment, the thickness t1 of the first polysilicon layer 1020 is between 500 nm and 2 µm.

[0041] The surface area of ​​the crystalline silicon body 101 can also be enlarged with respect to opposite sides, as shown in the schematic sectional view of Fig. 2B is illustrated. In the illustrated embodiment of Fig. 2B the first polysilicon layer 1020 is formed on the first side 1030 of the crystalline silicon substrate 104, resulting in the enlarged surface area on the first surface 1050 similar to that in Fig. This leads to the embodiment shown in Figure 2A. Additionally, a second polysilicon layer 1021 is formed on a second side 1031 of the crystalline silicon substrate 104, resulting in an enlarged surface area on the second surface 1051 of the crystalline silicon body 101. The thicknesses t1, t2 of the first and second polysilicon layers 1020, 1021 can be the same if, for example, the first and second polysilicon layers 1020, 1021 are formed by a common process. According to another embodiment, the thicknesses t1, t2 of the first and second polysilicon layers 1020, 1021 can also differ from each other if, for example, the first and second polysilicon layers 1020, 1021 are formed sequentially by different processes.

[0042] After increasing the surface area of ​​the first and / or second surfaces 1050, 1051 of the crystalline silicon body 101 and after oxidizing the increased surface area to remove COPs from the crystalline silicon body 101 by interstitial diffusion, the polysilicon layer(s) 1020, 1021 can be removed, followed by processes, for example, to fabricate a semiconductor device in the crystalline silicon body 101. According to another embodiment, the polysilicon layer 1020 and / or the polysilicon layer 1021 can remain as a gettering layer during further processing of the crystalline silicon body 101. The oxide layer on the polysilicon layer can remain during subsequent processes or can be removed. An oxide layer on a side of the silicon body 101 that does not have a polysilicon layer can be partially or even completely removed.An additional curing step, for example carried out in a hydrogen-containing atmosphere at a temperature between 800°C and 1200°C or between 900°C and 1100°C, can then be performed to smooth out COP-induced surface imperfections on the side of the silicon body 101 that does not have a polysilicon layer.

[0043] According to one embodiment, the formation of the first and / or second polysilicon layer 120, 121 comprises doping the first and / or second polysilicon layer 1020, 1021 with at least 10 17 cm -3 on phosphorus or even at least 10 19 cm -3Phosphorus doping in the first and / or second polysilicon layer 1020, 1021 allows for increased injection of interstitial silicon into the crystalline silicon body 101 due to an increase in the oxidation rate caused by the presence of the phosphorus doping. Additionally, the effectiveness of a getter in the first and / or second polysilicon layer 1020, 1021 can be increased, leading to a reduction or suppression of heavy metal incorporation by diffusion from outside the crystalline silicon body 101.

[0044] Another embodiment of enlarging the surface area of ​​the crystalline silicon body 101 is shown in the schematic sectional view of Fig. Figure 3 illustrates the process of increasing the surface area of ​​the crystalline silicon body 101 by forming a porous layer 1041 on the first surface 1050. For example, electrochemical anodizing of the crystalline silicon body 101 in dilute aqueous or hydrofluoric acid (HF) can be used to form the porous layer 1041. Ethanol can be added to remove H2 bubbles that escape during the etching process. Other examples of producing the porous silicon layer 1041 include stain etching or chemical etching (without current). Pore widths and sizes can range from less than 2 nm (micropores), between 2 and 50 nm (mesopores), to widths and sizes greater than 50 nm (macropores), for example.

[0045] Another embodiment of enlarging the surface area of ​​the crystalline silicon body 101 is shown in the schematic sectional view of Fig. Figure 4 illustrates this. In the illustrated embodiment of Fig. Figure 4 shows the surface area of ​​the first surface 1050 of the crystalline silicon body 101 enlarged by irradiating the first surface 1050 with a laser beam designed to locally melt the crystalline silicon body 101 at the first surface 1050. Recrystallization of the crystalline silicon body 101 leads to an increased surface roughness at the first surface 1050.

[0046] Another embodiment of enlarging a surface area of ​​the crystalline silicon body 101 is shown in the schematic sectional view of Fig. Figure 5 illustrates this. In the illustrated embodiment of Fig. 5. The process of increasing the surface area of ​​the crystalline silicon body 101 includes a machining process. A machining tool 107 acts on the first surface 1050 to increase the surface area. Examples of the machining process include metal cutting, abrasive processes such as grinding and / or lapping, and shearing. The machining process may be followed by a surface cleaning process. Examples of the surface cleaning process include any operation or combination of wet chemical cleaning, such as combined RCA cleaning; ultra-high vacuum (UHV) cleaning, such as thermal desorption; cleaning processes using oxygen and / or ozone, such as carbon burning; and processes using hydrogen, such as heating in an H2 environment.

[0047] Another embodiment of enlarging the surface area of ​​the crystalline silicon body 101 is shown in the schematic sectional view of Fig. Figure 6 illustrates this. In the illustrated embodiment of Fig. 6 an etch mask layer 108 is formed on the first surface 1050 of the crystalline silicon body 101 and patterned or structured, for example by a lithographic process for patterning or structuring a hard mask layer or a resist layer.

[0048] An etching process is then applied to the first surface 1050. By applying an isotropic etching process to the first surface 1050 of the crystalline silicon body 101, for example by isotropic wet etching, an enlarged surface area on the first surface 1050 can be obtained, similar to the cross-sectional view of the crystalline silicon body 101, indicated by an arrow A in Fig. 6, result.

[0049] When an anisotropic etching process is applied to the first surface 1050 of the crystalline silicon body 101, for example by an anisotropic dry etching process such as reactive ion etching, or an anisotropic wet etching with hydroxides such as potassium hydroxide (KOH), an enlarged surface area on the first surface 1050 can be seen, similar to the schematic cross-sectional view of the crystalline silicon body 101, indicated by an arrow B in Fig. 6, result.

[0050] Anisotropic etching can also result in a multitude of trenches 109 on the first surface 1050 of the crystalline silicon body 101, as shown in the schematic sectional view of Fig. 7A is illustrated.

[0051] According to one embodiment, the process of enlarging the surface area of ​​at least one surface from the first and second surfaces 1050, 1051 yields an increase in the surface area by at least 30%, or even by at least 50%, or even by more than a factor of two. Any one or any combination of the Fig. The processes described in sections 2A to 7A can be used. The process of enlarging the surface area can also be applied to a portion or all of the first and / or second surfaces 1050, 1051. According to one embodiment, the trenches 109, or a portion thereof, formed in the first surface 1050 of the crystalline silicon body 101 can be used as device-specific elements of trench-based semiconductor devices, such as gate trenches with a gate electrode, a gate dielectric, and an optional field electrode. Additionally, or alternatively, the trenches 109, or a portion thereof, formed in the first surface 1050 of the crystalline silicon body 101 can be used to realize compensation structures in the drift zone.Thus, the trenches 109 can first serve to provide an increased surface area in the process of removing COPs from the crystalline silicon body 101 and can then be integrated as device-specific elements into the process of fabricating a semiconductor device in the crystalline silicon body 101. A depth t3 of the trenches 109, which in the embodiment of . Fig. 7A illustrates that it can also change, for example down to a depth t4, as shown in the schematic cross-sectional view of the crystalline silicon body 101 of Fig. 7B illustrates this.

[0052] According to one embodiment, trenches 109 of varying depths can be formed on the first surface 1050 and / or the second surface 1051. According to another embodiment, the ratio between the depth of the plurality of trenches 109 and the thickness of the crystalline silicon body 101 is between 0.5% and 100% or between 1% and 50%.

[0053] As shown in the schematic cross-sectional view of the crystalline silicon body 101 of Fig. As illustrated in Figure 7C, the trenches 109 are formed on the first and second surfaces 1050 and 1051. Further details can be seen in the cross-sectional view of the crystalline silicon body 101. Fig. As shown in Figure 7D, the trenches 109 can extend through the crystalline silicon body 101. In this case, but also in other cases, the extension of the trenches 109 into a third dimension perpendicular to the plane of the drawing can be limited to a range between 1 µm and 100 µm or to a range between 3 µm and 50 µm.

[0054] According to one embodiment and after forming the Trenches 109, as in any or any combination of the Fig. As illustrated in Figures 7A to 7D, at least one oxygen concentration and one nitrogen concentration in the crystalline silicon body 101 are reduced by diffusion of oxygen and / or nitrogen from the crystalline silicon body 101. The increased surface area at the first and / or second surfaces 1050, 1051, caused by the presence of the trenches 109, allows for increased diffusion of oxygen and / or nitrogen.

[0055] According to one embodiment, the nitrogen concentration in the crystalline silicon body 101 is reduced by at least a factor of 2 or by at least a factor of 5 in a mesa region 110 between opposing trenches 109. The process of nitrogen diffusing from the crystalline silicon body 101 can be carried out at a temperature in a range between, for example, 900°C and 1050°C. According to one embodiment, the nitrogen concentration after partial diffusion of nitrogen from the crystalline silicon body 101 can be less than 2 × 10⁻⁶. 14 cm -3 .

[0056] According to another embodiment, the oxygen concentration in the crystalline silicon body 101 decreases by at least 10% or at least 50% or even by at least a factor of 2, starting from a depth of 10 µm from the first and / or second surface 1050, 1051 to the first and / or second surface 1050, 1051.

[0057] According to one embodiment, the depth of the trenches 109 is between 3 µm and 250 µm. According to another embodiment, the width of the trenches 109 is between 1 µm and 30 µm. A distance d between adjacent two trenches of the trenches 109, i.e., a width of the mesa area 110, can be between 1 µm and 30 µm, for example. In this case, but also in other cases, the extension of the trenches 109 into a third dimension perpendicular to the plane of the drawing can be limited to a range between 1 µm and 100 µm or to a range between 3 µm and 50 µm.

[0058] According to one embodiment, the depth of the trenches 109 and the extent of a space charge region within the depth of the crystalline semiconductor body 101 deviate by less than 50%, less than 30%, or even less than 10% at the maximum blocking voltage for which the device to be formed in the crystalline silicon body 101 is designed. The depth of the trenches 109 can, for example, be set to the maximum blocking voltage for which the device to be formed in the crystalline semiconductor body 101 is designed.

[0059] Diffusion of foreign substances, such as nitrogen and / or oxygen and / or any dopants, from the crystalline silicon body 101 allows for a reduction or suppression of unwanted background doping by oxygen and / or nitrogen in the base material used to fabricate a semiconductor device. Diffusion of, for example, boron or phosphorus allows for the realization of a base material or a starting material with high resistivity in the region of the epitaxially filled trenches.

[0060] The formation of trenches 109 on opposite sides of the crystalline silicon body 101, as in Fig. 7C illustrates, or a formation of the trenches 109 extending through the crystalline silicon body 101, as in Fig. As illustrated in Figure 7D, this is advantageous for the effective removal of COPs from the crystalline silicon body 101 by interstitial diffusion and is further advantageous for the effective diffusion of oxygen and / or nitrogen and / or unwanted dopants from the crystalline silicon body 101 in order to reduce or suppress unwanted background doping by oxygen and / or nitrogen and / or phosphorus and / or boron and / or other dopants.

[0061] The Fig. Figures 8A to 8D illustrate schematic top views of a crystalline silicon body 101 with various designs or layouts of trenches formed in the crystalline silicon body 101 to enlarge a surface area.

[0062] Referring to the schematic top view of the crystalline silicon body 101 of Fig. 8A the Trenches 109 extend as strips parallel to each other.

[0063] Referring to the schematic top view of the crystalline silicon body 101 of Fig. In 8B, the trenches are arranged in a circular and regular pattern.

[0064] Referring to the schematic top view of the crystalline silicon body 101 of Fig. 8C the Trenches 109 are rectangular or square and arranged regularly.

[0065] The Trenches 109 or a part of the Trenches 109 may also be arranged in the shape of an ellipse, a polygon, for example a hexagon, a closed loop, for example a ring, or any combination of different shapes.

[0066] The schematic top view of the crystalline silicon body 10l of Fig. Figure 8D illustrates a combination of different trench designs, including a circle, a square or rectangle, a strip, and a closed loop. The various trench designs can be arranged regularly or irregularly. According to one embodiment, the arrangement and dimensions of the trenches are selected with due consideration for optimizing the removal of COPs from the crystalline silicon body 101 by the [unclear text]. Fig. 1 illustrated process as well as a reduction or suppression of an unwanted background doping by oxygen and / or nitrogen in the crystalline silicon body 101 by diffusion.

[0067] Following the in Fig. 1 illustrated process and / or a reduction or suppression of an undesired background doping by oxygen and / or nitrogen and / or boron and / or phosphorus and / or other dopants in the crystalline silicon body 101 by diffusion are carried out according to a Fig. In the embodiment shown in Figure 9A, the trenches 109 are filled by lateral epitaxial growth in areas 111. Forming the trenches 109 with a taper can facilitate the avoidance of voids in the areas 111.

[0068] According to one embodiment, lateral epitaxial growth includes in-situ doping.

[0069] With reference to the schematic cross-sectional representation of the crystalline silicon body 101 of. Fig. 9B, dopants introduced into regions 111 are partially diffused from regions 111 and into surrounding parts of the crystalline silicon body 101, for example, by applying a suitable thermal budget through heating. Depending on the thermal budget and subsequent thermal budgets during the fabrication of the semiconductor device in the crystalline silicon body 101, lateral undulation or waviness of a doping profile can be established. The above method allows the crystalline silicon body 101 to be subdivided into regions with different doping concentrations, with the regions being laterally adjacent to one another. For example, the above method allows a target doping concentration to be established in an inner region 112 of the crystalline silicon body 101, while maintaining a background doping concentration in a region 113, for example, a peripheral region surrounding the inner region 112.

[0070] Filling of Trenches 109 by lateral epitaxial growth was illustrated by an arrangement of Trenches 109 as shown in Fig. 7D is shown. Lateral epitaxial growth can be performed independently of the trench arrangement, i.e., also with respect to trench arrangements such as those shown, for example, in the Fig. Figures 7A to 7C show that after filling the trenches 109 by lateral epitaxial growth, one or more semiconductor layers, for example epitaxial semiconductor layers, can be formed on one side or on opposite sides of the crystalline silicon body 101. The formation of one or more semiconductor layers, for example one or more epitaxial semiconductor layers, on one or opposite sides of the crystalline silicon semiconductor body 101 is not limited to the processes shown in the figures. Fig. The embodiments shown in 7A to 7D are not limited, but can also be applied to any other embodiment according to, for example, the one in Fig. The illustrated process feature S200 will be executed.

[0071] According to another embodiment, dopants can be diffused through a side wall and / or the bottom of the trenches 109 before the trenches are filled. This allows the creation of buried field stop zones, and subsequent high-temperature processes can be suitably selected such that the dopants introduced, for example, through the bottom of the trenches 109 diffuse along a lateral direction to such an extent that an overlap of a diffusion area with adjacent trenches 109 occurs. If no overlap occurs, structured field stop layers can be created, resulting, for example, in improved softness or smoothness of the shutdown behavior of power semiconductor devices and reduced overvoltage peaks.

[0072] According to another embodiment, the regions 111 are intrinsically or lightly doped, and doping of the crystalline semiconductor body 101 is carried out by proton irradiation from one or opposite sides of the crystalline semiconductor body 101, followed by thermal annealing, for example by an annealing process in a temperature range between 300°C and 520°C, in order to generate hydrogen-correlated donors in the crystalline silicon body 101. In addition to proton irradiation, electron irradiation can be carried out to improve the homogeneity of the doping between opposite sides of the crystalline silicon body 101 as a result of vacancies in the crystalline semiconductor body 101 created by electron irradiation.

[0073] Referring to the section view of Fig. In the embodiment shown in Figure 10A, a first part 1140 of the trenches 109 is lined with a first dielectric material 115, for example an oxide such as SiO2. A second part 1141 of the trenches 109 remains uncovered.

[0074] By forming the first dielectric material 115 only in the first part 1140 of the trenches 109, the second part 1141 of the trenches 109 can be filled and doped in situ by lateral epitaxial growth, as shown in the schematic section view of Fig. 10B is shown, compare area 1111.

[0075] Similar to the one in the Fig. 9A and Fig. In the embodiment shown in Figure 9B, dopants introduced into the second part 1141 can partially diffuse into surrounding parts of the crystalline silicon body 101, as shown in the sectional view of Fig. As shown in 10C, this can be achieved, for example, by applying a suitable thermal budget through heating. This allows the inner region 112 of the crystalline silicon body 101 to be doped.

[0076] Referring to the schematic cross-sectional representation of the crystalline silicon body of Fig. In 10D, the trenches 109 in the first part 1140 are filled with a second dielectric material 116 or a combination of materials. The first dielectric material 115 can optionally be removed before the formation of the second dielectric material 116.

[0077] Further processes for fabricating a semiconductor device in the crystalline silicon body 101 follow. For example, and representative of a wide variety of processes, is the formation of a gate structure 120 with a gate electrode 121 and a gate dielectric 122 in Fig. 10E shown. The processes for manufacturing the semiconductor device in the crystalline semiconductor body 101 can include front-end-of-line (FEOL) processing with processes such as formation of a semiconductor well or zone by diffusion or implantation of dopants, formation of conductive and insulating layers, and planarization as examples.

[0078] Referring to the schematic cross-sectional view of the crystalline silicon body 101 of Fig. 10F, the second dielectric material 116 is removed from the first part 1140 of the trenches 109, for example, by an etching process.

[0079] Referring to the schematic cross-sectional view of the crystalline silicon body 101 of Fig. 10G, a contact layer 127 can be formed on a bottom side and side walls of the trenches 109, for example by introducing dopants through side walls and a bottom side of the trenches 109 into a surrounding part of the crystalline semiconductor body 101. The dopants can be introduced by one or a combination of methods, for example, diffusion from the gas phase, diffusion from the solid phase, and ion implantation.

[0080] Referring to the schematic cross-sectional view of the crystalline silicon body 101 of Fig. 10H can be followed by back-end-of-line (BEOL) processing, including, among other things, the formation of a passivation layer 129, for example an imide on the crystalline silicon body 101, and / or wafer thinning. In some embodiments, the wafer thinning process removes the layer with the increased surface roughness.

[0081] The FEOL and BEOL processing of the crystalline silicon body 101, which is in Fig. The process shown in 1 can result in any desired semiconductor device, such as a semiconductor diode, an insulated gate bipolar transistor (IGBT), a bipolar transistor, a field-effect transistor (FET), a solar cell, or an integrated circuit.

[0082] The semiconductor regions described as p-doped or n-doped in the illustrated embodiments can also be reverse-doped, i.e., semiconductor regions described as p-doped can be n-doped, and semiconductor regions described as n-doped can be p-doped. This application is intended to cover any adaptations or modifications of the specific embodiments discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

Claims

[1] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) by forming a polysilicon layer (1020) on at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101), wherein a surface roughness of the polysilicon layer (1020) is greater than a surface roughness of at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101); Forming an oxide layer by oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and Removal of the polysilicon layer (1020). [2] Method according to claim 1, wherein the oxidizing of the enlarged surface area (1050) comprises a wet oxidation process. [3] Method according to claim 1 or 2, wherein the duration of oxidizing the enlarged surface area (1050) is between one hour and five hours. [4] Method according to any one of claims 1 to 3, wherein the oxidation of the enlarged surface area (1050) is carried out in a temperature range between 1000°C and 1300°C. [5] Method according to claim 1, further comprising curing the crystalline silicon body (101) in a hydrogen-containing atmosphere at temperatures greater than 800°C. [6] Method according to claim 1, wherein the thickness of the polysilicon layer (1020) is between 500 nm and 2 µm. [7] Method according to claim 1 or 6, further comprising doping at least a part of the polysilicon layer (1020) with at least 10 17cm -3 on phosphorus. [8] Method according to any one of claims 1 to 5, wherein the enlargement of the surface area of ​​at least one surface from the first and second surfaces (1030, 1031) comprises local etching of the at least one surface from the first and second surfaces (1030, 1031). [9] Method according to any one of claims 1 to 5, further comprising etching a plurality of trenches (109) into the crystalline silicon body (101). [10] Method according to claim 9, wherein the depth of the plurality of trenches (109) is between 3 µm and 250 µm and the width of the plurality of trenches (109) is between 1 µm and 30 µm. [11] Method according to claim 9 or 10, wherein the distance between adjacent trenches of the plurality of trenches (109) is between 1 µm and 30 µm. [12] Method according to any one of claims 9 to 11, further comprising filling the plurality of trenches (109) by lateral epitaxial growth. [13] Method according to claim 12, wherein the lateral epitaxial growth comprises in-situ doping. [14] Method according to claim 12, wherein doping the crystalline silicon body (101) comprises proton irradiation through at least one surface from the first and second surfaces (1030, 1031) and a subsequent annealing process in a temperature range between 300°C and 520°C. [15] Method according to any one of claims 12 to 14, wherein doping the crystalline silicon body (101) further comprises generating vacancies in the crystalline silicon body (101) by electron irradiation. [16] Method according to any one of claims 12 to 15, further comprising, after filling the trenches (109), forming a semiconductor layer on the crystalline silicon body (101) on a side which comprises at least a part of the plurality of trenches (109) filled by lateral epitaxial growth. [17] Method according to any one of claims 9 to 16, further comprising forming the plurality of trenches (109) on the first and second surfaces (1030, 1031). [18] Method according to any one of claims 9 to 17, wherein the ratio between the depth of the plurality of trenches (109) and the thickness of the crystalline silicon body (101) is between 0.5% and 100%. [19] Method according to any one of claims 9 to 18, further comprising reducing the concentration of foreign substances in the crystalline silicon body (101) by a thermal process for diffusing at least a part of the foreign substances out of the crystalline silicon body (101). [20] Method according to any one of claims 9 to 19, further comprising introducing dopants through at least one wall or side of the side walls and bottom side of the plurality of trenches (109). [21] Method according to any one of claims 1 to 5, wherein the enlargement of the surface area of ​​the at least one surface from the first and second surfaces (1030, 1031) comprises forming a porous layer (1041) on at least one surface from the first and second surfaces (1030, 1031). [22] Method according to any one of claims 1 to 5, wherein the enlargement of a surface area of ​​the at least one surface from the first and second surfaces (1030, 1031) comprises irradiating the surface area with laser irradiation designed to melt an irradiated part of the crystalline silicon body (101). [23] Method according to any one of claims 1 to 5, wherein the enlargement of the surface area of ​​the at least one surface from the first and second surfaces (1030, 1031) comprises a machining process and a subsequent surface cleaning process. [24] Method according to any one of claims 1 to 23, wherein the enlargement of the surface area of ​​at least one surface from the first and second surfaces (1030, 1031) provides for an enlargement of the surface area by at least 30%. [25] Method according to any one of claims 1 to 24, wherein the oxidation of the enlarged surface area is carried out at a temperature of at least 1100°C. [26] Method according to any one of claims 1 to 25, further comprising forming a semiconductor layer on the crystalline semiconductor body (101). [27] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) and Oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and further comprising a healing of the crystalline silicon body (101) in a hydrogen-containing atmosphere at temperatures greater than 800°C. [28] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) and Oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and further comprising an etching of a multitude of trenches (109) into the crystalline silicon body (101), and a filling of the multitude of trenches (109) by lateral epitaxial growth. [29] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) by forming a polysilicon layer (1020) on at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101), wherein a surface roughness of the polysilicon layer (1020) is greater than a surface roughness of at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101); and Oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and further comprising an etching of a plurality of trenches (109) into the crystalline silicon body (101), wherein a ratio between a depth of the plurality of trenches (109) and a thickness of the crystalline silicon body (101) is between 0.5% and 100%. [30] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), wherein the method comprises: . Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) by forming a polysilicon layer (1020) on at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101), wherein a surface roughness of the polysilicon layer (1020) is greater than a surface roughness of at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101); and Oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and further comprising an etching of a plurality of trenches (109) into the crystalline silicon body (101), and an introduction of dopants through at least one wall or side from the side walls and a bottom side of the plurality of trenches (109). [31] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) by forming a polysilicon layer (1020) on at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101), wherein a surface roughness of the polysilicon layer (1020) is greater than a surface roughness of at least one surface of the first and second surfaces (1030, 1031) of the crystalline silicon body (101); and Oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and wherein the enlargement of the surface area of ​​the at least one surface from the first and second surfaces (1030, 1031) comprises forming a porous layer (1041) on at least one surface from the first and second surfaces (1030, 1031). [32] Method for removing vacancy agglomerates from a crystalline silicon body (101) having opposite first and second surfaces (1030, 1031), the method comprising: Enlarging a surface area of ​​at least one surface from the first and second surfaces (1030, 1031) and Oxidizing the enlarged surface area (1050) at a temperature of at least 1000°C and for a duration of at least 20 minutes; and wherein enlarging a surface area of ​​the at least one surface from the first and second surfaces (1030, 1031) comprises irradiating the surface area with laser irradiation designed to melt an irradiated part of the crystalline silicon body (101).

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