METHOD FOR STRUCTURING INTEGRATED CIRCUITS

Abstract

Method for structuring a substrate (202), wherein the method comprises: Structuring a resist layer (210) formed over the substrate (202), resulting in a resist structure (210); Treating the resist structure (210) with an ion beam (212), resulting in a treated resist structure (210), wherein the ion beam (212) is generated with a first gas and is directed at the resist structure (210) at an angle of inclination of at least 10 degrees; and Etching of the substrate (202) with the treated resist structure (210) as an etching mask, wherein the ion beam (212) is directed towards the resist structure (210) as a fan-shaped beam which has a unimodal distribution with rotation angles of about -50 degrees to about 50 degrees.

Description

STATE OF THE ART

[0001] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC development, functional density (i.e., the number of interconnected devices per unit area) has generally increased, while geometric size (i.e., the smallest component or trace that can be produced using a manufacturing process) has decreased. This miniaturization process generally provides benefits by increasing manufacturing efficiency and reducing associated costs. However, such miniaturization has also increased the complexity of IC processing and manufacturing, and similar advancements in IC processing and manufacturing are needed to realize these benefits.

[0002] For example, lithography is a process commonly used in IC manufacturing to transfer IC designs onto a semiconductor substrate. A typical lithography process involves applying a resist (protective coating or photoresist) to a substrate, exposing the resist to radiation, such as deep ultraviolet (DUV) rays, and developing and partially stripping the resist to leave a structured resist on the substrate. This structured resist is then used in subsequent etching processes to build the ICs. During such etching processes, some characteristics of the structured resist, such as critical dimension (CD), linewidth roughness (LWR), and line edge roughness (LER), can be transferred to the final IC features, such as transistor gates.With the reduction of IC device dimensions, CD, LWR, and / or LER of transistor gates (as well as other IC features) are recognized as important issues. Accordingly, progress in the lithography process is generally desirable to meet the demand for continued semiconductor miniaturization.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2012 / 0 083 136 A1, US 2013 / 0 062 309 A1 and US 2009 / 0 203 839 A1.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for the sake of clarity of discussion. Fig. Figure 1 is a flowchart of a method for forming a target structure or device on a substrate for implementing one or more embodiments of the present invention. The Fig. Figures 2-4, 7, 9 and 11 illustrate three-dimensional views of the shaping of a target structure according to the method of Fig. 1 according to one embodiment ( Fig. 2-4 and 9) and some examples ( Fig. 7 and Fig. 11). The Fig. 5 and Fig. Figure 6 illustrates edge roughness, width roughness and critical dimension of a structured resist layer. Fig. Figure 8 illustrates the inclination angle and rotation angle of an ion beam incident on a substrate, according to the method of Fig. 1, according to one embodiment. The Fig. 10 and Fig. Figure 12 illustrates exemplary twist angle distributions of an ion beam according to the method of Fig. 1 according to one embodiment ( Fig. 10) and an example ( Fig. 12). The Fig. Figures 13-17 are images and data from laboratory experiments, which were carried out according to the procedure of Fig. 1 were implemented, according to one embodiment. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for realizing various functions of the intended subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and should not be understood as a limitation. For example, the formation of a first feature over or on top of a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not dictate a relationship between the different embodiments and / or configurations discussed.

[0007] Furthermore, spatial relative terms, such as "below," "above," "lower," "above," and "upper," and the like, can be used here for easier description of the relationship of one element or feature to another element or features, as illustrated in the figures. The spatial relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or otherwise), and the spatial relative descriptors can be interpreted accordingly.

[0008] The present disclosure relates generally to the formation of a structure or device for an integrated circuit (IC) using a photolithography process and more specifically to the treatment of a structured resist layer in order to reduce its LWR, LER and / or CD before the structured resist layer is used in subsequent etching processes.

[0009] Fig. Figure 1 shows a flowchart of a method 100 for forming a target structure or device according to various embodiments of the present invention. Additional operations may be provided before, during, and after the method 100, and some of the operations described may be replaced, eliminated, or deferred for additional embodiments of the method. The method 100 is an example and is not intended to limit the present disclosure beyond what is explicitly stated in the claims. The method 100 is described below in conjunction with the Fig. 2-17 described.

[0010] In Operation 102, the procedure represents 100 ( Fig. 1) a substrate 202 ready, as in Fig. 2 shown. With reference to Fig. 2 The substrate 202 comprises one or more material layers in various embodiments and is an intermediate step in a manufacturing process for forming a device 200. The device 200 can be an integrated circuit (IC) or a part thereof, which may include a random access static memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors and inductors, and active components such as p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells and combinations thereof.The device 200 can include three-dimensional devices and multi-gate devices, such as double-gate FETs, FinFETs, tri-gate FETs, omega FETs, gate-all-around (GAA) devices, and vertical GAA devices. In one embodiment, the substrate 202 is a semiconductor substrate (e.g., a wafer). In another embodiment, the substrate 202 is silicon in a crystalline structure. In alternative embodiments, the substrate 202 can include other elemental semiconductors, such as germanium, or a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate 202 may comprise a silicon-on-insulator (SOI) substrate, be stressed to improve performance, include epitaxial regions, include doped regions, include one or more semiconductor devices or parts thereof, include conductive and / or insulating layers, and / or include other suitable features and layers.

[0011] In operation 104, procedure 100 forms ( Fig. 1) a resist layer 210 on the substrate 202. With reference to Fig. 3. In the present embodiment, prior to the formation of the resist layer 210, one or more material layers are formed on the substrate 202 as etched layers, such as a hard mask layer 204, a lower material layer 206, and a layer 208 for reflection reduction. In various embodiments, some of the material layers 204 / 206 / 208 can be omitted and / or replaced, or alternatively, other material layers can be added between the resist layer 210 and the substrate 202. In one embodiment, the resist layer 210 is formed by a rotary coating process followed by a soft baking process.

[0012] In various embodiments, the hard mask layer 204 can use amorphous silicon (a-Si), silicon oxide, silicon nitride (SiN), titanium nitride (TiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or other suitable material or composition; the lower material layer 206 can contain silicon, oxygen, and / or carbon, such as silicon dioxide (SOC) or spin-deposited silicon dioxide (SOG); the arc layer 208 can be a polymer material layer or a silicon-containing material layer, such as silicon oxide, silicon oxygen carbide, and plasma-enhanced vapor-deposited silicon oxide. The various material layers 204, 206, and 208 can be formed by a variety of processes.For example, they can be formed by chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition method. For example, the hard mask layer 204 can be formed by CVD using chemicals including hexachlorosilane (HCD or Si₂Cl₆), dichlorosilane (DCS or SiH₂Cl₂), and bis(tert-butylamino)silane (BTBAS or C₈H). 22 N2Si) and Disilan (DS or Si2H6).

[0013] The resist layer 210 can be a positive or a negative resist. A positive resist is normally insoluble in a resist developer but is made soluble by exposure to radiation, such as deep ultraviolet (DUV) radiation, extreme ultraviolet (EUV) radiation, an electron beam (e-beam), an X-ray beam, or other suitable radiation. An example of a positive resist material is chemically strengthened resist (CAR), which contains main strand polymer protected by acid-labile groups (ALGs). A negative resist exhibits the opposite behavior—normally soluble in a resist developer, it is made insoluble by exposure to radiation, such as a DUV beam, an EUV beam, an e-beam, an X-ray beam, or other suitable radiation.An example of a negative resist is a polymer that forms intramolecular and / or intermolecular cross-links when irradiated, such as the polymerization of ethyl(alphahydroxy)acrylate (EHMA) and methacrylic acid (MAA).

[0014] In operation 106, the procedure 100 is structured ( Fig. 1) the resist layer 210, thereby forming a resist structure. In one embodiment, the structuring process transfers a structure from a mask (or a photomask or a grid) to the resist layer 210. Alternatively, the structuring process can utilize a maskless structuring method, such as direct electron beam writing (EBDW). In one embodiment, structuring the resist layer 210 comprises exposing the resist layer 210 to radiation, annealing after exposure, developing the resist layer 210 in a resist developer, and curing annealing, thereby removing the exposed portion (or non-exposed portion in the case of a negative resist) of the resist layer 210 and leaving non-exposed portions of it on the ARC layer 208 as a resist structure. The radiation can be a DUV beam, an EUV beam, an e-beam, an X-ray beam, an ion beam, or other suitable radiation.In embodiments where a mask is used to structure the resist layer 210, the mask can be of different types, such as a transparent mask or a reflective mask, and can be formed using various technologies, such as a binary mask or phase-shift mask (PSM). In one example, a binary mask comprises a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) applied as a layer in the opaque areas of the mask. In another example, a PSM comprises various features designed to have a suitable phase difference to improve resolution and image quality. In the current example, the resist layer 210 is structured to form a line pattern 210 ( Fig. 4) forms. For simplification, the line pattern 210 is longitudinally oriented in the “y” direction, laterally in the “x” direction, and vertically in the “z” direction. In the present example, the single line pattern 210 is used for simplification and easier understanding and does not necessarily restrict the embodiment to a number of line patterns and / or an arrangement of the line pattern, such as slot patterns, hole patterns, patterns with arcs, etc.

[0015] In a typical lithography process, an etching process follows, which etches the ARC layer 208 using the line pattern 210 as an etch mask, thereby transferring the pattern to the ARC layer 208 and subsequently to the substrate 202 through further etching processes. Problems arise when transferring the pattern from the resist structure 210 to the ARC layer 208. For example, the line pattern 210 may not have an ideal critical dimension (CD). For instance, its dimension in the "x" direction (or its width) may be larger than an IC design target. In another example, the line pattern 210 may have undesirable surface roughness, such as line edge roughness (LER) and / or width roughness (LWR). Fig. Figure 5 illustrates a cross-sectional view of the line pattern 210, showing the roughness of its side walls. Fig. Figure 6 illustrates the surface roughness along the line pattern 210 in the “y” direction (or its longitudinal direction). In the present embodiment, LER is defined as the 3σ deviation of an edge from a line adjacent to that edge, or mathematically LER=3∑i=0n(xi−x¯)2 / n, and LWR is defined as the 3σ deviation of the line width along the line, or mathematically: LWR=3∑j=0n(CDj−CD¯)2 / n Such non-ideal CD and unwanted LER / LWR can be transferred from line pattern 210 to the ARC layer 208 and ultimately to the substrate 202, causing problems in IC fabrication. For example, line pattern 210 can be used to pattern transistor gate electrodes whose gate length corresponds to the width of line pattern 210. Gate length is a critical characteristic of a transistor because it can affect the transistor's power consumption and / or switching speed. Unwanted CD and LER / LWR can cause the gate length to fall outside the design specification. Furthermore, during etching processes, such as dry etching, which is frequently used for gate structuring, line pattern 210 undergoes severe degradation due to a lack of etch selectivity, leading to resist film loss and increased LER / LWR.The present disclosure addresses the above problems by treating a structured resist layer, such as the line pattern 210, with ion beams before it is used in subsequent etching processes. Laboratory experiments have shown that embodiments of the present disclosure can reduce CD, LER, and / or LWR of the resist structures. This is highly desirable for advanced process nodes, such as 10 nanometers (nm) and above.

[0016] In operation 108, the procedure treats 100 ( Fig. 1) the line pattern 210 with an ion beam 212. In embodiments, the ion beam 212 is generated by an ion implanter. With reference to Fig. 7, for example, the ion beam 212 is a focused ion beam. To further develop the example, the ion beam 212 is directed onto the line pattern 210 (or onto the upper surface of the ARC layer 208, or actually onto the substrate 202) at an angle inclined to a normal to the upper surface of the ARC layer 208 (i.e., the "z" axis in the present example). This angle of incidence is called the "angle of inclination" in the present disclosure and is described in Fig. 8 illustrated. Fig. Figure 8 also shows a "rotation angle" of the ion beam 212, which is the angle between the plane containing the ion beam 212 and the "z" axis, and the plane containing the "x" and "z" axes. The tilt angle and rotation angle together define the direction of incidence of the ion beam 212. Referring again to Fig. 7. The ion beam 212 is directed at the line pattern 210 at an angle of inclination greater than or equal to 10 degrees. In some cases, the angle of inclination is set to more than 30 degrees to reduce resist film loss. For example, the ion beam 212 is directed at the line pattern 210 at a uniform angle of rotation, which is, for example, approximately zero (0) degrees. In another example, the ion beam 212 is directed at the line pattern 210 at a uniform angle of rotation of approximately 90 degrees (i.e., parallel to the line pattern 210).

[0017] In various embodiments, the ion beam 212 is generated by an ion implanter using a gas as the ion source. In one embodiment, the gas is argon (Ar), and the ion beam 212 is generated with an ion energy of approximately 1.0 kV to approximately 3.5 kV and an ion dose of approximately 1 × 10⁻⁶ ions / cm². 2 up to about 10 E16 ions / cm² 2In one embodiment, the gas is helium (He) and the ion beam 212 is provided with an ion energy of about 1 kV to about 5 kV and an ion dose of about 1 E16 ions / cm². 2 up to about 10 E16 ions / cm² 2 In one embodiment, the gas is silane (SiH4) and the ion beam 212 is provided with an ion energy of about 2 kV to about 5 kV and an ion dose of about 0.5 E16 ions / cm². 2 up to about 3 E16 ions / cm² 2 In one embodiment, the gas is methane (CH4), and the ion beam is supplied with an ion energy of approximately 1 kV to approximately 5 kV and an ion dose of approximately 1 E16 ions / cm². 2 up to about 6 E16 ions / cm² 2The gas can be one of the following in various embodiments: CH4, SiH4, Ar, He, O2, N2, CO2, other suitable gases, and a combination thereof. In one example, the ion beam 212 is generated with Ar, has an inclination angle of about 19 degrees to about 30 degrees and a twist angle of about 0 degrees, and is provided with an ion energy of about 1 kV to about 1.5 kV and an ion dose of about 0.5 E16 ions / cm². 2 up to about 3 E16 ions / cm² 2 The device 200 is provided with various embodiments. In these embodiments, the device 200 moves relative to the ion beams 212, so that the line pattern 210 is scanned uniformly in its longitudinal direction by the ion beams 212.

[0018] In some embodiments, the ion beam 212 not only trims the line pattern 210 to reduce its width and smooth its surfaces, including the sidewalls, but also causes a chemical reaction in the resist material to certain depths in the line pattern 210, depending on how far the ions migrate within the resist material. The chemical reaction alters the characteristics of the resist material. For example, it can cause the etch rate of the line pattern 210 to decrease. Fig. Figures 13-17 show various images and data obtained from laboratory experiments according to different embodiments of the present disclosure, demonstrating the effectiveness of the ion beam treatment. Fig. Figure 13 shows an image of the resist line structure after resist development and before ion beam treatment. As shown, the resist line structures are formed on a silicon-containing ARC layer and exhibit a certain surface roughness. Fig. Figure 14 is an image of the resistance line structures after the execution of the ion beam treatment according to an embodiment of the present disclosure. As can be seen, the resistance line structures ( Fig. 14) smoother surfaces and a smaller width compared to the resistance line structures before treatment. Fig. Figure 15 shows that a crust is formed on the surface of a resist structure after it has been subjected to ion beam treatment according to an embodiment of the present disclosure. The crust is hardened resist material as a result of the chemical reaction between the resist material and the ions. Fig. Figure 16 shows that a resist structure CD shrinkage of 26.8% to 49.8% was achieved in various embodiments of the present disclosure using Ar, He, SiH4, and CH4 as the respective ion source. Furthermore, a general LWR reduction of 16% (with Ar ion beam treatment), 46% (with C ion beam treatment), and 38% (with Si ion beam treatment) is reported. A general LER reduction similar to the LWR reduction, with a difference of a few percentage points, has also been reported. Fig. Figure 17 shows a diagram of the resistance rate before and after the ion beam treatment(s). As in Fig. As shown in Figure 17, the resist etch rate decreases from 135.2 nm / min (1352 Å / min) before treatment to less than 40 nm / min (400 Å / min) after treatment, which generally represents a 3- to 6-fold reduction in the etch rate. Such a reduction in the etch rate is highly desirable for subsequent etching of the ARC layer 208, as it strengthens the resist structure against etchants to be used, thereby reducing resist film loss and LER / LWR degradation during the etching process. At the same time, the treated resist structure retains a desirable ashing rate for a subsequent resist ashing or peeling process. It has been reported that in some cases the resist structure has an ashing rate of about 400 nm / min (4,000 Å / min), compared to about 700 nm / min (7,000 Å / min) before ion beam treatment.

[0019] In one embodiment according to the invention, the ion beam 212 has more than one rotation angle, which means that different parts of the ion beam 212 are directed at the line pattern 210 simultaneously at different rotation angles. This is shown in Fig. Figure 9 illustrates this. In fact, the ion beam 212 is not supplied as a focused beam, but as a fan-shaped beam. In one embodiment according to the invention, the ion beam 212 has rotation angles with a unimodal distribution 214, as shown in Figure 9. Fig. Figure 10 shows that the unimodal distribution 214 has an ion energy peak at zero (0) degrees of twist angle and has an ion energy that is essentially limited within the range of -θ1 to +θ2 degrees. In one embodiment of the invention, both θ1 and θ2 are approximately 50 degrees. In various examples, the unimodal distribution 214 can be asymmetric with respect to the zero-degree twist angle or can have an ion energy peak at a non-zero twist angle. In some cases, the use of an ion beam with a twist angle and unimodal distribution is more effective than an ion beam with a uniform twist angle, since the former cuts the surface of the line pattern 210 from different angles simultaneously.

[0020] In one example, the ion beam has 212 rotation angles with a bimodal distribution 216, as in the Fig. 11 and Fig. Figure 12 illustrates this. As a result, the ion beam 212 has two fan-shaped parts that are simultaneously directed towards the line pattern 210. As shown in Fig. As shown in Figure 12, the bimodal distribution 216 has two unimodal distribution components, 216A and 216B, each corresponding to one of the two parts of the ion beam 212. The unimodal distribution 216A has an ion energy peak at a twist angle α0 and has an ion energy that is essentially within a range of twist angles from α1 to α2. In an example, α0 is about 12.5 degrees, α1 about 7.5 degrees, and α2 about 17.5 degrees. The unimodal distribution 216B has an ion energy peak at a twist angle β0 and has an ion energy that is essentially within a range of twist angles from -β1 to -β2. In an example, β0 is about 12.5 degrees, β1 about -7.5 degrees, and β2 about -17.5 degrees. In some examples, the unimodal distribution 216A (or 216B) can be asymmetric with respect to its mean twist angle. For example, its energy peak can be closer to the twist angle α2 (or β2).In one example, α0 is approximately 40 degrees, α1 approximately 20 degrees, and α2 approximately 40 degrees. In some examples, the unimodal distributions 216A and 216B may partially overlap. In some cases, using an ion beam with a bimodal twist angle distribution is more effective than using an ion beam with a uniform twist angle or a unimodal twist angle distribution because the former not only trims the surface of the line pattern 210 from different angles simultaneously but also uses more ion energy to process the surface roughness from the sides.

[0021] In one embodiment, the ion beam 212 ( Fig. 7, Fig. 9 and Fig. 11) a gas cluster ion beam (GCIB), such as an O2 cluster, an Ar cluster, or a CO2 cluster. For example, ion beam 212 may be an Ar-GCIB with an average cluster size of about 10,000 to about 20,000 atoms, average cluster charge +3, average cluster energy 65 keV, average cluster velocity 6.5 km / s, and a total electric current of 200 µA or more.

[0022] In operation 110, the procedure transmits 100 ( Fig. 1) The treated resist structure 210 is deposited onto the ARC layer 208 and subsequently onto the substrate 202 by a process that includes etching. The etching processes may include dry (plasma) etching, wet etching, and / or other etching methods. For example, a dry etching process may introduce an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. The etching processes etch the ARC layer 208 using the treated resist structure 210 as an etching mask. Due to the ion beam treatment of the resist structure 210, the transferred structure in the ARC layer 208 (as well as in the substrate 202) exhibits superior CD and LER / LWR compared to those in a typical lithography process.After the ARC layer 208 has been etched, in one embodiment the line pattern 210 is removed, for example by a wet etching process using a photoresist stripper, an aqueous alkaline solution, an amine solvent mixture or an organic solvent.

[0023] In operation 112, the procedure runs at 100 ( Fig.1) to form a final structure or device. In one embodiment, the resist structure 210 is part of a feature definition of a flat slot insulation. To further develop this embodiment, the method 100 transfers the treated resist structure 210 onto the hard mask layer 204 as an opening; etches the substrate 202 through the opening to form a slot in it; removes the hard mask layer 204; fills the slot with a dielectric material; and performs a chemical-mechanical planarization (CMP) process on the dielectric material. In another embodiment, the resist structure 210 is part of a feature definition of gate electrodes, and the substrate 202 comprises a layer of polysilicon on a layer of dielectric material, such as silicon dioxide (SiO2) or silicon oxynitride (SiON).To further develop this embodiment, method 100 transfers the treated resist structure 210 onto the hard mask layer 204 as a line; etches the polysilicon layer and the dielectric material with the structured hard mask layer 204 as an etch mask, thereby forming a gate stack; removes the structured hard mask layer 204, and forms a spacer around the gate stack. In a further embodiment, the resist structure 210 is part of a contact feature definition, such as a source, drain, or gate contact.To further develop this embodiment, the method 100 transfers the treated resist structure 210 onto the hard mask layer 204 as an opening; etches the substrate 202 through the opening to form a contact hole, whereby an upper surface of a terminal (source, drain or gate) deposits a barrier layer in the contact hole; fills the remaining space of the contact hole with a conductive material, such as aluminum (Al), tungsten (W), copper (Cu) or cobalt (Co), and performs a CMP process to planarize an upper surface of the conductive material.

[0024] In one embodiment, the ion beam 212 is used to treat a material layer that is not a resist layer. For example, the line pattern 210 is first transferred to the arc layer 208, and then the structured arc layer 208 is treated with the ion beam 212. Experiments show that such treatment is also effective in reducing CD, LER, and LWR of the structured arc layer 208, which is a polymeric or silicon-containing material. Analogously, the ion beam 212 can be used to treat the lower material layer 206 after it has been structured.

[0025] For example, the present disclosure treats a structured resist layer with an ion beam to reduce CD, LER, and LWR of the structured resist layer before it is used as an etching mask. This improves the CD uniformity of the final IC devices. The ion beam can be generated with various gases, such as Ar, He, CH4, and SiH4, and with selectable ion energies and doses, making the examples in the present disclosure adaptable to different applications and currents. In several examples, the ion beam is directed onto the structured resist layer at an inclination angle and a rotation angle, which contributes to smoothing the sidewalls of the resist structure without significant film loss.Furthermore, the presence of a unimodal or bimodal twist angle distribution in conjunction with an inclination angle helps to overcome the shadowing effect when dense resist structures are treated with the ion beam. Moreover, various examples of the present disclosure can be introduced into all types of IC fabrication processes where lithography is used, such as nanowire structuring in vertical gate all-around (VGAA) devices, STI structuring, gate electrode structuring, contact structuring, and so on.

[0026] The preceding overviews present several embodiments so that those skilled in the field can better understand the manifestations of the present disclosure. Those skilled in the field will recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to pursue the same purposes and / or achieve the same advantages of the embodiments described herein.

Claims

[1] Method for structuring a substrate (202) wherein the method comprises: Structuring a resist layer (210) formed over the substrate (202), resulting in a resist structure (210); Treating the resist structure (210) with an ion beam (212), resulting in a treated resist structure (210), wherein the ion beam (212) is generated with a first gas and is directed at the resist structure (210) at an angle of inclination of at least 10 degrees; and Etching of the substrate (202) with the treated resist structure (210) as an etching mask, wherein the ion beam (212) is directed towards the resist structure (210) as a fan-shaped beam which has a unimodal distribution with rotation angles of about -50 degrees to about 50 degrees. [2] Method according to claim 1, wherein the first gas is Ar and the ion beam (212) is provided with an ion energy of about 1.0 kV to about 3.5 kV and the ion dose is about 1E16 ions / cm² 2 up to about 10E16 ions / cm² 2 amounts. [3] Method according to claim 1, wherein the first gas is He and the ion beam (212) is provided with an ion energy of about 1 kV to about 5 kV and the ion dose is about 1E16 ions / cm² 2 up to about 10E16 ions / cm² 2 amounts. [4] Method according to claim 1, wherein the first gas is SiH4 and the ion beam (212) has an ion energy of about 2 kV to about 5 kV and an ion dose of about 0.5E16 ions / cm 2 up to approximately 3E16 ions / m 2 is provided. [5] Method according to claim 1, wherein the first gas is CH4 and the ion beam (212) has an ion energy of about 1 kV to about 5 kV and an ion dose of about 1E16 ions / cm² 2 up to about 6E16 ions / cm²2 is provided. [6] The method of claim 1, wherein the first gas is one of the following group: CH4, SiH4, Ar, He, O2, N2, CO2 and a combination thereof. [7] Method for forming an etch layer over a substrate (202), the method comprising: Forming a resist layer (210) over the etched layer; Structuring the resist layer (210), resulting in a structured resist layer (210); Performing an ion implantation in the structured resist layer (210), resulting in a treated structured resist layer (210), wherein performing the ion implantation includes: Providing a treatment gas containing CH4, SiH4, Ar or He; Generating an ion beam (212) from the treatment gas; and Directing the ion beam (212) which is incident on the substrate (202) at an angle of inclination; and etching the etch layer with the treated structured resist layer (210) as an etch mask, wherein the ion beam (212) is directed onto the structured resist layer (210) as a fan-shaped beam which has a unimodal distribution with rotation angles of about -50 degrees to about 50 degrees. [8] Method according to claim 7, wherein the ion beam (212) has an ion dose of at least 0.5E16 ions / cm² 2 has. [9] Method according to claim 7 or 8, wherein the angle of inclination is at least 10 degrees. [10] Method for forming an integrated circuit, the method comprising: Structuring a layer of material (210, 208) over a substrate (202), resulting in a structured layer of material (210); Treating the structured material layer (210) with an ion beam (212) generated with an element from the following: CH4, SiH4, Ar and He, and directed towards the substrate (202) at an angle of inclination greater than 10 degrees, resulting in a treated structured material layer (210); and Etching of the substrate (202) with the treated structured material layer (210), wherein the ion beam (212) is directed onto the structured material layer (210) as a fan-shaped beam having a unimodal distribution with rotation angles of about -50 degrees to about 50 degrees. [11] Method according to claim 10, wherein the material layer (210, 208) is a resist layer (210). [12] Method according to claim 10, wherein the material layer (210, 208) is a silicon-containing layer (208) for antireflective coating, ARC. [13] Method according to any one of claims 10 to 12, wherein the material layer (210, 208) contains silicon, carbon and oxygen.

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