High-bandwidth memory and noise-free differential XOR

Abstract

Differential XOR circuit (600A), wherein the circuit has: a selection logic circuit (610) configured to receive an unbalanced input signal (602) and a clock signal (604), and to provide a complementary output signal corresponding to the unbalanced input signal; a pre-charge circuit (630) configured to pre-charge output nodes (632, 634) during a pre-charge phase; and a multiplexer (620) configured to receive a differential input signal and the complementary output signal and to provide a differential output signal to the output node during an evaluation phase.

Description

[0001] The present description refers generally to memory circuits and in particular, but not exclusively, to a high-bandwidth multi-read memory device and a noise-free differential exclusive OR (XOR).

[0002] Network processors requiring high memory bandwidth can use multiport memory bit cells, which are quite large and complex to implement. For example, register file memories based on multiport memory bit cells can use 4-port memory bit cells, each employing four sets of pass gates, or 4-read-port memory bit cells, which use four sets of series transistors (e.g., NFETs) for the read ports and pass gates for the write ports. However, these bit cells are essentially area-intensive and are most commonly used in small-capacity register file applications. Existing bit cells and their associated memory architectures are not suitable for use in the large-capacity memories required by network processors.

[0003] US 2011 / 0022791A1 describes a hierarchical storage system with several distinct algorithmic memory blocks. Each algorithmic memory block comprises a memory controller that implements a specific memory algorithm and a set of lower-level memory components.

[0004] US 2006 / 0 018 417 A1 describes a phase detection circuit for adjusting the data rate of an input data signal and selectively activating reference signals and error signals.

[0005] US 2006 / 0 034 394 A1 describes a differential control circuit for the sampling edge position for use in a clock and data recovery circuit that receives a high-speed data signal. BRIEF OVERVIEW OF THE INVENTION

[0006] In accordance with the present invention, a differential XOR circuit with the features of claim 1 and a multiple read storage device with the features of claim 5 are provided.

[0007] Advantageous further training opportunities arise from the dependent sub-requirements.

[0008] Advantageously, at least some of the numerous output data buses are configured to be connected by one or more XOR gates to at least two memory subblocks that differ from the single memory subblock.

[0009] Advantageously, a first output data bus of the plurality of output data buses is configured to output data during the multiple read operation according to a first address of the plurality of addresses corresponding to a first address input bus of the plurality of address input buses, wherein each of the auxiliary memory subblocks that is not part of the auxiliary memory block is configured to contain primary auxiliary data, and wherein at least one XOR gate is configured to supply the primary auxiliary data, and is configured to receive input data from at least two of the plurality of memory subblocks of a respective of the plurality of memory blocks during a write operation, wherein the at least two of the plurality of memory subblocks comprise the respective of the auxiliary memory subblocks.

[0010] Advantageously, each auxiliary memory subblock that is part of the auxiliary memory block is configured to contain secondary auxiliary data, wherein at least one XOR gate is configured to supply the secondary auxiliary data, and is configured to receive input data from at least two of the plurality of memory subblocks of at least two of the plurality of memory blocks during a write operation.

[0011] Advantageously, a final auxiliary memory subblock of the auxiliary memory block is configured to contain ternary auxiliary data, wherein at least one XOR gate is configured to supply the ternary auxiliary data and is configured to receive input data from at least two memory subblocks of the auxiliary memory block during a write operation.

[0012] Advantageously, a second output data bus is configured to output data during the multiple read operation according to a second address of the plurality of addresses corresponding to a second address input bus, and wherein the second output data bus is connected to a first read XOR gate which is configured to receive data from a memory subblock of a first memory block of the plurality of memory blocks and a respective auxiliary memory subblock of the first memory block of the plurality of memory blocks.

[0013] Advantageously, a third output data bus of the plurality of output data buses is configured to output data during the multiple read operation according to a third address of the plurality of addresses corresponding to a third address input bus of the plurality of address input buses, and wherein the third output data bus is connected to a second read XOR gate configured to receive data from a memory subblock of a second memory block of the plurality of memory blocks and a respective auxiliary memory subblock of the second memory block.

[0014] Advantageously, the device further comprises a data output path corresponding to each memory subblock of the plurality of memory subblocks, wherein the data output path includes a multiplexer connected to an output XOR gate, wherein output XOR gates are connected to form a series XOR tree, and wherein a read amplifier of a memory subblock is configured to forward data to one of the XOR gates of the series XOR tree.

[0015] Advantageously, the differential output signal is configured to depend on the asymmetrical input signal, and the differential output signal has one of the differential input signal or a complement of the differential input signal.

[0016] Advantageously, the pre-charging phase and the evaluation phase are based on different states of the clock signal, and the circuit is implemented in multiple XOR stages.

[0017] Advantageously, the selection logic circuit comprises two inverters and one or more logic gates including NAND or NOR gates, wherein the multiplexer has two cross-coupled MOS pass gates, and wherein the pre-load circuit has at least two MOS transistors that receive the clock signal at a common gate node of the at least two MOS transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Certain features of the technology in question are set forth in the attached claims. However, for illustrative purposes, several embodiments of the technology in question are shown in the following figures. Fig. Figure 1 shows an example of a high-bandwidth multi-read storage device according to one or more implementations. Fig. Figure 2 shows an example of a write circuit for the high-bandwidth multi-read storage device. Fig. 1 according to one or more implementations. Fig. Figures 3A-3B show examples of a read circuit and a data output path of the high-bandwidth multi-read storage device. Fig. 1 according to one or more implementations. Fig. Figure 4 is a flowchart showing an example algorithm for performing a multiple read operation according to one or more implementations. Fig. Figure 5 shows an example of a method for providing a high-bandwidth, multi-read storage device according to one or more implementations. Fig. Figures 6A-6B show examples of a differential exclusive OR (XOR) circuit and a corresponding truth table, according to one or more implementations. Fig. Figure 7 shows an example of a multi-stage differential XOR circuit according to one or more implementations. Fig. Figure 8 shows an example of a communication device that uses features of the technology in question, according to one or more implementations. DETAILED DESCRIPTION

[0019] The following detailed description is intended to describe various configurations of the technique in question and is not meant to represent the only configurations in which the technique can be practiced. The accompanying drawings are included herein and form part of the detailed description. The detailed description contains specific details to enable a thorough understanding of the technique in question. However, it is clear and obvious to those skilled in the art that the technique in question is not limited to the specific details presented here and can be practiced using one or more implementations. In one or more cases, known structures and components are shown in the form of a block diagram to avoid obscuring the concepts of the technique in question.

[0020] In one or more aspects of the technology described, methods and configurations for providing high-bandwidth memory are presented. Furthermore, a dynamic, noise-free differential XOR tree is disclosed, which can be effectively employed in implementing the high-bandwidth memory of the technology. The technology can be used in any semiconductor device requiring high-bandwidth memory (e.g., 1-2 GHz) or multi-port memory. The disclosed high-bandwidth memory has many advantageous features at the circuit, system, and product levels. At the circuit level, for example, the technology can lead to a substantial (e.g., ~50%) improvement in density (read ports per mm²). 2This leads to advantages over an existing two-port algorithmic XOR memory. System benefits include additional read bandwidth per unit area or a smaller area for the same read bandwidth. At the product level, cost savings due to reduced chip area and performance improvements due to additional read bandwidth are among the advantageous features. The differential XOR tree of this technique not only eliminates additional transitions (e.g., noise pulses) but can also significantly reduce the dynamic performance in the peripheral XOR logic (e.g., by ~80%) and the peripheral XOR area (e.g., by ~20%), resulting in a predictable worst-case delay path.

[0021] Fig. Figure 1 shows an example of a high-bandwidth, multi-read storage device 100 according to one or more implementations of the technology in question. The storage device 100 is divided into several (e.g., 3 or more) storage blocks (hereinafter referred to as "blocks") 110, including an auxiliary storage block (hereinafter referred to as "auxiliary block") 120. Each of the storage blocks 110 and 120 has several storage subblocks (hereinafter referred to as "subblocks") 112 (e.g., A1, A0, B1, and B0), including an auxiliary storage subblock (hereinafter referred to as "auxiliary subblock") 114 (e.g., AX and BX). The numbering of the subblocks (X1, X0, and XX) of the auxiliary block 120 is the same as the numbering of the subblocks of other blocks (e.g., 110). The storage device 100 can be any type of storage device, for example an SRAM storage device formed by, for example, 6-transistor (6-T) memory cells or other memory cells.

[0022] The storage device 100 has several address input buses 130, including, for example, four address input buses corresponding to four input addresses addrA, addrB, addrC, and addrD. The storage device 100 also has a number of output data buses 140, for example, doutA, doutB, doutC, and doutD, to output data corresponding to several addresses corresponding to the address input buses 130 during a multiple read operation. The addresses on the address input buses 130 can correspond to a single memory subblock (e.g., A1, A0, B1, or B0) of one of the blocks 110, into which input data (e.g., Din) is to be written in a write operation, as described herein. The high-bandwidth, high-capacity storage device of the present technology can be implemented in a multiple-read, single-write implementation. For the sake of simplicity, a quadruple-read, single-write implementation is described herein.Naturally, the multiple read operation can lead to an address collision if the multiple addresses to be read belong to (e.g., multiple rows) a single subblock (e.g., A1, A0, B1, or B0). The presented technique solves the problem of address collisions as described in detail below.

[0023] The concept behind the implementation of the multiple read (e.g., quadruple read) operation is based on the following Boolean equations: If A⊕B⊕C⊕D = n and B⊕C⊕D = m, then, considering the known equation A⊕A = 0, it follows that: n⊕m = (A → (B⊕iB)⊕ (C⊕C) ⊕(D⊕D)) = A⊕0⊕0⊕0 = A, where the symbol ⊕ denotes the XOR operation. In other words, if you have "n", you can reconstruct A if you have "m". This concept is used here to implement the multiple read (e.g., quadruple read) operation of memory device 100 without address collisions. To implement the multiple read operation, the technique in question uses the auxiliary subblocks AX and BX to resolve first and second address collisions, and the subblocks (e.g. X1, X0 and XX) of auxiliary block 120 to resolve third and fourth address collisions.The auxiliary subblocks AX, BX, X1, X0, and XX are not designated by actual addresses and contain auxiliary data that can be used to resolve multiple-read address collisions. Naturally, the present solution can be extended to handle more than four-address collisions by partitioning the storage device differently, for example, into blocks with more than four subblocks. In the four-address collision implementation described here, the data content of the auxiliary subblocks is defined by the following Boolean equations: AX=A0⊕A1 BX=B0⊕B1 X1=A1⊕B1 X0=A0⊕B0 XX=X1⊕X0

[0024] In other words, each auxiliary memory subblock (e.g., AX or BX) that is not part of auxiliary memory block 120 contains primary auxiliary data. The primary auxiliary data is provided by at least one XOR gate, which, during a write operation, receives input data from at least two memory subblocks (e.g., A0⊕A1 or B0⊕B1) of a given memory block, including that auxiliary memory subblock. Each auxiliary memory subblock (e.g., X1, X0, or XX) corresponding to auxiliary memory block 120 contains secondary auxiliary data. The secondary auxiliary data is provided by at least one XOR gate, which, during a write operation, receives input data from at least two memory subblocks (e.g., A1⊕B1, A0⊕B0, or A1⊕B1⊕A0⊕B0) of at least two memory blocks (e.g., 110 or 120). The XOR operations of the equations above are implemented using two-way XOR gates as explained below.

[0025] Fig. Figure 2 shows an example of a write circuit 200 of the high-bandwidth multi-read storage device 100 of Fig. 1 according to one or more implementations of the technique in question. In order to perform the multiple read (e.g., quadruple read) operation without address collision, the technique in question uses a hierarchical XOR architecture, as in Fig. 2 is shown. The one in Fig. The hierarchical XOR architecture shown in Figure 2 uses two-way XOR gates for simplicity. In some implementations, the number of inputs to the XOR gates depends on the number of subblocks within block 110. For example, if the number of subblocks within each block 110 was four, three-input XOR gates were used.

[0026] At the in Fig. In the write circuit 200 shown in Figure 2, writing to an address corresponding to row 10 of subblock A1 is described. The first pipeline stage (e.g., Stage 1) performs the actual write (e.g., W10) of the data (e.g., Din) to row 10 in subblock A1. Simultaneously, a read operation is performed on row 10 of subblocks A0, B1, and X0. The second pipeline stage (e.g., Stage 2) performs write operations to AX, X1, and XX. The XOR gate 210 is used to perform the Boolean operation in Eq. 1, providing XOR of A1 and A0. The XOR gate 220 performs the Boolean operation in Eq. 3 and provides XOR of A1 and B1, which is written to subblock X1 of auxiliary block 120. Finally, XOR 230 performs the Boolean operation in Eq. 5 through, which provides XOR of X1 and X0.It is noted that XOR 230 uses the output of XOR 220 as one of its inputs, which is written to subblock X1 and is identical to the contents of subblock X1. The contents of the auxiliary subblocks AX, X1, and XX, written according to the write operations explained above, can be used to read the data from four different addresses of subblock A, as explained here.

[0027] Fig. Figures 3A-3B show examples of a read circuit 300A and a data output path 300B of the multi-read high-bandwidth storage device 100. Fig. 1 according to one or more implementations of the technology in question. The read operation of the technology in question is performed by an exemplary 300A read circuit. The in Fig. The read operation shown in Figure 3A describes a solution to the four-way address collision, where address ports A, B, C, and D (e.g., AddrA, AddrB, AddrC, and AddrD) each access rows 10, 11, 12, and 13 of the same subblock (e.g., A1 of block 110). In other words, address A accesses data from an address corresponding to row 10 in subblock A1, address B accesses data from an address corresponding to row 11 in subblock A1, address C accesses data from an address corresponding to row 12 in subblock A1, and address D accesses data from an address corresponding to row 13 in subblock A1. It is noted that addresses A, B, C, and D do not access the same row of subblock A, but this is still an address collision because all addresses A, B, C, and D correspond to rows in the same physical subblock A1.It is noted that the case where all of the addresses access the same address is handled in the same way.

[0028] The read operation is performed as follows. Address port A accesses row 10 in subblock A1 and outputs the data to DOUTA. Address port B cannot simultaneously use subblock A1, so a read of row 11 (e.g., R11) is performed from subblocks A0 and AX, and the data is output as DOUTB. It should be noted that the data for port B has just been regenerated using the previously described procedure, by performing A0 ⊕ AX = A0 ⊕ (A1 ⊕ A0) = A1, using XOR gate 310. Address port C cannot simultaneously use subblock A1, A0, or AX, so a read of row 12 is performed from subblocks B1 and X1, and an XOR operation is performed on the data using XOR gate 312. The data is then forwarded as DOUTC to the respective output port.Address port D cannot simultaneously use subblocks that are already being accessed. Therefore, reading row 13 in subblocks B0, BX, X0, and XX is performed by XOR gates 314 and 316. XOR gate 318 then performs a combined XOR operation on the data from XOR gates 314 and 316, and the resulting data is forwarded as DOUTD to the respective output port. For simplicity, the XOR operation for the data to be sent as DOUTD is shown here in two parallel stages. In some embodiments, the XOR operations can be performed sequentially to achieve the same logical result.

[0029] Fig. Figure 3B shows a circuit diagram of some of the key data output path circuits. The diagram shows SRAM core cells represented by an SRAM block 320, a read amplifier 330, and a separate data output path for each data port. Each data path has a two-input multiplexer (e.g., 340A, 340B, 340C, or 340D) followed by a corresponding XOR gate (e.g., 350A, 350B, 350C, or 350D). This circuit diagram of Fig. 3B represents the column layouts for each subblock of storage device 100 of Fig. 1. The inputs RDA_IN, RDB_IN, RDC_IN and RDD_IN, which come into the circuit above, come from the outputs of a similar data output path circuit in a sub-block which is coupled (e.g. directly above) to data output path 300B.

[0030] When a read operation is performed, the data passed to each output port is either a buffered version of the data coming from the read amplifier or it is newly generated by performing an XOR operation on data coming from the read amplifiers of different subblocks. The XOR gates 350A, 350B, 350C, and 350D are connected in series, and the data 332 from a read amplifier (e.g., 330) of a subblock can be passed to one of the series-connected XOR trees formed by a multiplexer (e.g., 340A) and a corresponding XOR gate (e.g., 350A). The port selection signals PSA, PSB, PSC, and PSD control whether the data from the read amplifier 330 is passed to an XOR tree (e.g., for a given port) or whether a 0 is passed to that XOR tree.Passing a 0 into the XOR tree indicates that the data from the current subblock will not be used to generate the data going to the given port.

[0031] In some implementations, the operation of data output path 300B is as follows. When a WL is triggered in a memory module, the port selection input in that module is also triggered. The port selection signals PSA, PSB, PSC, and PSD are "one-hot" signals, separate for each module. Passing data 332 from the read amplifier 332 implies that data 332 is part of the data set for which an XOR operation is to be performed to yield the data for that port (e.g., RDA). Passing a 0 indicates that data 332 does not correspond to that port. Setting all PS signals except one (e.g., PSA) to 0 for a given port means that there was no address collision, and data 332 from that module is only buffered at the XOR gate (e.g., 350A) and passed to the output.Since the XOR gates 350A, 350B, 350C and 350D of each subblock are connected in series, the correct data for each port appears at the end of the series connection.

[0032] Fig. Figure 4 is a flowchart showing an example algorithm 400 for performing a multi-read operation, according to one or more implementations of the technique in question. The multi-read operation described here applies, for example, to the read circuit of Fig. 3A to. The algorithm starts at a control operation block 410, where it is checked whether a read operation is being performed on a primary port (e.g., a port of A1 of Fig. 3A). If the response is negative, control is passed to control operation block 430. Otherwise, if the response is positive, control is passed to operation block 420, where a read operation is performed on the primary port and the contents of the respective address are output to the primary output port (e.g., as DOUTA), and control is then passed to control operation block 430. At control operation block 430, it is checked whether a read operation is requested on the next port. If the response is negative, no read operation is performed. However, if the response is positive, control is passed to control operation block 440, where it is checked whether there is a collision with a previous port (e.g., the addresses belong to a single memory subblock).If no collision has occurred, a simple read operation without XOR is performed at operation block 450, the output is forwarded to a corresponding port, and control is passed to operation block 430. If the response is positive, equivalent series (e.g., R11 of ) are read at operation block 460. Fig. 3A) in the subblock of the lowest level (e.g. A0 of Fig. 3A) is read without collision and XORed with the respective auxiliary sub-block (e.g. AX), the result is output to a corresponding output port, and the control is passed on to the control operation block 430.

[0033] In some implementations, Algorithm 400 is executed by a local processor, such as a processor or controller of a network switch or router, or by a remote processor, such as a cloud processor. In one or more implementations, Algorithm 400 is implemented in firmware or hardware, for example, a field-programmable gate array (FPGA).

[0034] Fig. Figure 5 shows an example of a method 500 for providing a high-bandwidth, multi-read storage device according to one or more implementations of the technology. For illustrative purposes, the blocks of the example method 500 are described here as occurring sequentially or linearly. However, several blocks of the example method 500 can occur in parallel. Furthermore, the blocks of the example method 500 need not be executed in the sequence shown, and / or one or more of the blocks of the example method 500 need not be executed.

[0035] According to procedure 500, a storage device (e.g. 100 of Fig. 1) into multiple memory blocks (e.g. 110 of Fig. 1) including an auxiliary memory block (e.g. 120 of Fig. 1) divided, with each memory block having several memory sub-blocks (e.g. A1, A0, B1, B0 of Fig. 1) including an auxiliary memory subblock (e.g. Ax or BX of Fig. 1) has (510). Several output data buses (e.g. 140 of Fig. 1) During a multiple read operation, data is output to the storage device according to addresses (e.g., AddrA, AddrB, AddrC, or AddrD). Fig. 1) according to address entry buses (e.g. 130 of Fig. 1) from (520).

[0036] Fig. Figures 6A-6B show examples of a differential exclusive OR (XOR) circuit 600A and a corresponding truth table 600B according to one or more implementations of the technique described. In one or more implementations, a differential XOR circuit 600A includes a selection logic circuit 610, a multiplexer 620, and a preload circuit 630. The selection logic circuit 610 receives an unbalanced input signal 602 and a clock signal 604 and provides complementary output signals 606 and 608 corresponding to the unbalanced input signal 602. In some implementations, the selection logic circuit 610 includes inverters 612 and 614 and NAND gates 616 and 618. NAND gate 616 receives as inputs an output signal from inverter 614, similar to signal 602, and the clock signal 604, and provides the output signal 606. NAND gate 618 receives as inputs an output signal from inverter 612 (e.g.,the inverted version of signal 602) and the clock signal 604, and provides the output signal 608. For one or more aspects, the selection logic circuit 610 can be implemented using NOR gates.

[0037] The multiplexer 620 receives a differential input signal BT and BF and the complementary output signals 606 and 608, and during an evaluation phase (e.g., when the clock signal 604 is high), it provides a differential output signal (e.g., OUTT and OUTF) to the output nodes 632 and 634. In one or more implementations, the multiplexer 620 can be implemented by cross-coupling two MOS pass gates, formed, for example, by the PMOS transistor pairs T1-T2 and T3-T4. During the evaluation phase, the input signal 602 (e.g., A) must remain stable until the next pre-charge phase, which begins when the clock signal 604 passes low. In some implementations, the multiplexer 602 can be implemented differently, for example, by NMOS pass gates or other configurations.

[0038] During the pre-charge phase, the pre-charge circuit 630 pre-charges the output nodes 632 and 634 to a high level (logic 1). The pre-charge circuit 630 is implemented by transistors T5 and T6 and an optional transistor T7. Transistors T5-T7 are PMOS transistors, but can also be implemented by NMOS transistors. The clock signal 604 controls the common gate of transistors T5-T7, and when it is low, it allows transistors T5 and T6 to pre-charge the output nodes 632 and 634 to the supply voltage level VDD. As shown in truth table 600b, the differential output signals OUTT and OUTF depend on the unbalanced input signal 602 (e.g., A) and can be identical to the differential input signal (BT and BF) or a complement of the differential input signal. For example, if A is logically 0, then OUTT and OUTF are identical to BT and BF.However, if A is logic 1, then OUTT and OUTF are complements of BT and BF. Truth table 600b corresponds to a differential XOR truth table for the input signals BT and BF, confirming the operation of circuit 600A as a differential XOR in the evaluation phase. The noise-free nature of XOR circuit 600A can be seen in truth table 600b, which shows that in the evaluation phase only one of BT or BF can be low, and consequently, only one of the outputs (OUTT or OUTF) can be low. However, with previously known XOR circuits, multiple transitions at the output can be observed depending on the arrival times of the inputs.

[0039] In some implementations, the noise-free, low dynamic power 600A XOR circuit can be used to control the XOR gates of Fig. 2, Fig. 3A and Fig. 3B is to be implemented to eliminate additional transitions, reduce the dynamic performance in the peripheral XOR logic (e.g. by ~80%) and the peripheral XOR area (e.g. by ~20%), and achieve a predictable delay path for the worst case.

[0040] In some implementations, the XOR circuit 600A can be implemented in multiple XOR stages, as explained below.

[0041] Fig. Figure 7 shows an example of a multi-stage differential XOR circuit 700 according to one or more implementations of the technique described. The multi-stage differential XOR circuit 700 shows how four of the XOR circuits described above (e.g., 710-1 to 710-4) can be connected to obtain a 5-input XOR function capable of performing the XOR function A0 ⊕A1 ⊕A2 ⊕A3 ⊕B on inputs A0, A1, A2, A3, and B. Input B is an unbalanced input, which is converted to differential by inverter 704. In some applications, the physical distance between the XOR functions may be large because they must cross long lines, as in Fig. Figure 7 shows the circuit, where resistors 720-1 to 720-4 are used to denote the long lines traversed by the XOR circuits 710-1 to 710-4. A read amplifier 740 is used to sense the small differential signal of the differential output of the XOR tree in order to output a final unbalanced output signal (OUT) at an output node 742 of the read amplifier 740. The structure of each XOR circuit 710 is similar to the XOR circuit 600A, and the BT and BF inputs of each stage (e.g., 710-3) are the OUTT and OUTF of a preceding stage (e.g., 710-2) that has traversed the long lines (e.g., denoted by resistors 720-2). The 4-stage differential XOR circuit 700 is just one example, and more stages can be connected in a similar way to form larger XOR trees.

[0042] Fig. Figure 8 shows an example of a Communication Device 800 that uses features of the technology described, according to one or more implementations of the technology described. Examples of the Communication Device 800 include an Ethernet switch of an Ethernet network, such as a private network, a data center network, an enterprise network, or other private networks. The Communication Device 800 has a number of inbound (input) ports IP1-IPn and several outbound (output) ports EP1-EPm. In one or more implementations, one or more of the inbound ports IP1-IPn can receive a data packet from another switch or endpoint device on the network.The communication device 800 further comprises a hardware component, such as an application-specific integrated circuit (ASIC) 810 (which in some embodiments may be implemented as a field-programmable gate array (FPGA)), a buffer 820, a processor 830, a memory 840 and a software module 850.

[0043] In some implementations, the ASIC 810 may include suitable logic, circuitry, interfaces, and / or code that can be operated to perform functionalities of a PHY circuit. The buffer 820 includes suitable logic, circuitry, code, and / or interfaces that can be operated to receive, store, and / or delay a block of data for communication through one or more of the output ports EP1-EPm. The processor 830 includes suitable logic, circuitry, and / or code that can enable the processing of data and / or the control of operations of the communication device 800. In this respect, the processor 830 may be capable of supplying control signals to various other sections of the communication device 800. The processor 830 also controls data transmissions between different sections of the communication device 800.Furthermore, the 830 processor can enable the implementation of an operating system or otherwise execute code to manage operations of the 800 communication device. The 830 processor can also execute the 400 algorithm. Fig. Execute command 4 to perform a multiple read operation on memory 840.

[0044] The Memory 840 comprises suitable logic, circuitry, and / or code capable of storing various types of information, such as received data, generated data, code, and / or configuration information. The Memory 840 may, for example, include RAM, ROM, Flash, and / or magnetic storage. In various embodiments of the technology, the Memory 840 may include RAM, DRAM, SRAM, T-RAM, Z-RAM, TT-RAM, or any other storage medium. The Memory 840 may include Software Modules 850 which, when executed by a processor (e.g., the Processor 830), can perform some or all of the functionalities of the ASIC 810. In some implementations, the Software Modules 850 include code which, when executed by a processor, can perform functionalities such as configuring the Communication Device 800.

[0045] In some implementations, the 840 memory is a broadband multiport memory, such as the 100 memory device from Fig. 1, and exhibits a disturbance-free XOR tree of the technique in question (e.g. 600A of Fig. 6A). This can lead to a significant (e.g., ~50%) improvement in density compared to existing two-port algorithmic XOR memories, cost savings due to reduced chip area, and performance improvements due to the added capability of concurrent read operations. The use of the differential XOR tree of this technique can substantially reduce the dynamic performance in the peripheral XOR logic (e.g., by ~80%) and the peripheral XOR area (e.g., by ~20%) and can result in a predictable worst-case delay path.

Claims

[1] Differential XOR circuit (600A), the circuit comprising: a selection logic circuit (610) configured to receive an unbalanced input signal (602) and a clock signal (604) and to provide a complementary output signal corresponding to the unbalanced input signal; a precharge circuit (630) configured to precharge output nodes (632, 634) during a precharge phase; and a multiplexer (620) configured to receive a differential input signal and the complementary output signal and to provide a differential output signal to the output node during an evaluation phase. [2] The differential XOR circuit of claim 1, wherein the differential output signal is configured to depend on the single-ended input signal, and wherein the differential output signal comprises one of the differential input signal or a complement of the differential input signal. [3] Differential XOR circuit according to claim 1, wherein the precharge phase and the evaluation phase are based on different states of the clock signal, and wherein the circuit is implemented in multiple XOR stages. [4] Differential XOR circuit according to claim 1, wherein the selection logic circuit comprises two inverters (612, 614) and one or more logic gates (616, 618) including NAND or NOR gates, wherein the multiplexer comprises two cross-coupled MOS pass gates, and wherein the precharge circuit comprises at least two MOS transistors that receive the clock signal at a common gate node of the at least two MOS transistors. [5] A high bandwidth multi-read memory device (100), the device comprising: a plurality of memory blocks (110) including an auxiliary memory block (120), each of the plurality of memory blocks comprising a plurality of memory sub-blocks (112), the plurality of memory sub-blocks comprising an auxiliary memory sub-block (114); a plurality of address input buses (130); and a plurality of output data buses (140) configured to output data corresponding to a plurality of addresses during a multiple read operation, the plurality of addresses corresponding to the plurality of address input buses, wherein the plurality of addresses correspond to a single memory sub-block of the plurality of memory sub-blocks of a memory block of the plurality of memory blocks; wherein at least some of the plurality of output data buses are configured to be connected to at least two memory sub-blocks different from the single memory sub-block through one or more XOR gates according to the differential XOR circuit of claim 1. [6] The apparatus of claim 5, wherein a first output data bus of the plurality of output data buses is configured to output data corresponding to a first address of the plurality of addresses corresponding to a first address input bus of the plurality of address input buses during the multiple read operation, wherein each of the auxiliary memory sub-blocks that is not part of the auxiliary memory block is configured to contain primary auxiliary data, and wherein at least one XOR gate according to the differential XOR circuit of claim 1 is configured to provide the primary auxiliary data and is configured to receive input data from at least two of the plurality of memory sub-blocks of a respective one of the plurality of memory blocks during a write operation, wherein the at least two of the plurality of memory sub-blocks comprise the respective one of the auxiliary memory sub-blocks. [7] The apparatus of claim 5, wherein each auxiliary memory sub-block that is part of the auxiliary memory block is configured to contain secondary auxiliary data, wherein at least one XOR gate according to the differential XOR circuit of claim 1 is configured to provide the secondary auxiliary data and is configured to receive input data from at least two of the plurality of memory sub-blocks of at least two of the plurality of memory blocks during a write operation. [8] The apparatus of claim 5, wherein a last auxiliary memory sub-block of the auxiliary memory block is configured to contain ternary auxiliary data, wherein at least one XOR gate according to the differential XOR circuit of claim 1 is configured to provide the ternary auxiliary data and is configured to receive input data from at least two memory sub-blocks of the auxiliary memory block during a write operation. [9] The apparatus of claim 5, wherein a second output data bus is configured to output data corresponding to a second address of the plurality of addresses corresponding to a second address input bus during the multiple read operation, and wherein the second output data bus is connected to a first read XOR gate according to the differential XOR circuit of claim 1, configured to receive data from a memory sub-block of a first memory block of the plurality of memory blocks and a respective auxiliary memory sub-block of the first memory block of the plurality of memory blocks. [10] The apparatus of claim 5, wherein a third output data bus of the plurality of output data buses is configured to output data corresponding to a third address of the plurality of addresses corresponding to a third address input bus of the plurality of address input buses during the multiple read operation, and wherein the third output data bus is connected to a second read XOR gate according to the differential XOR circuit of claim 1, configured to receive data from a memory sub-block of a second memory block of the plurality of memory blocks and a respective auxiliary memory sub-block of the second memory block.

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