Method for manufacturing a plurality of components

Abstract

Method for manufacturing a plurality of components (100) comprising the following steps: - Providing a carrier assembly (10) with a connected base body (13); - Providing a wafer assembly (200) with a connected semiconductor body assembly (20) on a substrate (9); - Connecting the wafer network with the carrier network to form a joint network; - Forming a plurality of separation trenches (60) at least through the base body (13) to form a grid structure (6) which determines the dimensions of the building elements (100) to be produced; - Forming a passivation layer (61) covering the side surfaces of the separation trenches (60); and - Separation of the common assembly, wherein the substrate (9) is detached from the semiconductor body assembly (20) and the common assembly is separated along the separation grooves (60) into a plurality of components (100), wherein - the semiconductor body assembly (20) is formed in one piece and free of mesa trenches before the wafer assembly (200) is joined to the substrate assembly (10), which determine the dimensions of the semiconductor bodies (2) to be formed and thus of the components (100) to be manufactured, and the dimensions of the components (100) to be manufactured are only determined during the generation of the grid structure (6) with the separation trenches (60) extending through the base body (13), and - the semiconductor body assembly (20) is unstructured before the separation trenches (60) are formed through the base body (13) to form the raster structure (6) and is only self-adjusted to form the raster structure (6) into a plurality of semiconductor bodies (2) after the separation trenches (60) have been created.

Description

[0001] A method for manufacturing a plurality of components is described.

[0002] In the fabrication of multiple electronic components, a semiconductor aggregate is typically first grown epitaxially on a growth substrate. In a subsequent process step, the semiconductor aggregate is separated into multiple semiconductor bodies. Trenches between the semiconductor bodies are usually defined using photolithography, with each trench requiring an adjustment tolerance distance to its corresponding subsequent separation trench. This necessitates sufficiently wide trenches between the semiconductor bodies, resulting in a significant loss of the semiconductor aggregate.

[0003] Publications US 2009 / 0179207A1, US 2007 / 0096130A1, US 2013 / 0095581A1, and US 2012 / 0322240A1 describe semiconductor devices and methods for manufacturing semiconductor devices. For example, a coating layer containing phosphorus particles is applied to a plurality of semiconductor bodies. A mask can be used to create trenches in a substrate of semiconductor material by laser irradiation. A growth substrate can be detached from the semiconductor bodies.

[0004] One task is to specify a reliable and efficient method for manufacturing a plurality of components.

[0005] This problem is solved, among other things, by a method for manufacturing a plurality of components according to the independent claim. Further embodiments and developments of the method are the subject of the dependent claims.

[0006] In at least one embodiment of a method for manufacturing a plurality of components, a carrier assembly with a continuous base body and a wafer assembly with a continuous semiconductor body assembly and a substrate are provided. To form a common assembly, the wafer assembly and the carrier assembly are joined together. In a next step, a plurality of separation grooves are formed, at least through the base body, to create a grid structure. The grid structure, in particular, defines the dimensions of the components to be manufactured. A passivation layer is formed, covering approximately the side surfaces of the separation grooves. The passivation layer can be formed partially or completely before or after the formation of the separation grooves, or at least partially during the formation of the separation grooves. Subsequently, the common assembly is singulated, whereby the substrate is separated from the semiconductor body assembly.In particular, the common bond is broken down into a plurality of building elements by the detachment of the substrate along the separation trenches.

[0007] According to at least one embodiment of the method, the continuous base body is formed from an electrically insulating or a semiconducting material. At least 80%, approximately at least 90%, or at least 95% of the volume and / or weight of the carrier assembly can be attributed to the base body. The base body preferably comprises or consists of a semiconductor material such as silicon.

[0008] According to at least one embodiment of the method, the composite structure has an exposed, preferably planar, connecting surface. In particular, the connecting surface bounds the composite structure in a vertical direction. The connecting surface is formed, in particular, by a continuous surface of the composite structure that extends, approximately in lateral directions, over the entire principal plane of the composite structure. The exposed connecting surface can be a surface of the base body or of a layer arranged on the base body, in particular an electrically insulating layer.

[0009] A planar surface is understood to be a surface that is particularly microscopically flat. Preferably, such a planar surface exhibits local vertical roughness, which is particularly less than 5 nm, less than 3 nm, preferably less than 1 nm, or less than 0.5 nm. A vertical direction is understood to be a direction that is particularly perpendicular to a principal extensional surface of the composite structure. A lateral direction is understood to be a direction that runs approximately parallel to the principal extensional surface of the composite structure. In particular, the vertical direction and the lateral direction are perpendicular to each other.

[0010] According to at least one embodiment of the method, the interconnected semiconductor wafer assembly comprises a plurality of semiconductor layers arranged one above the other. The substrate is, in particular, a growth substrate on which the semiconductor wafer assembly is arranged. Specifically, the semiconductor wafer assembly is deposited layer by layer onto the growth substrate, for example, epitaxially. The wafer assembly can have a contact structure designed for electrical contacting the semiconductor wafer assembly. For example, the semiconductor wafer assembly is arranged vertically between the contact structure and the substrate.

[0011] According to at least one embodiment of the method, the wafer composite has an exposed, preferably planar, contact surface. In particular, the contact surface is an exposed surface of the wafer composite facing away from the substrate. The wafer composite can have an insulating layer that also has an exposed surface serving as the contact surface of the wafer composite. The insulating layer can be an electrically insulating oxide layer. In particular, the insulating layer is part of the contact structure.

[0012] According to at least one embodiment of the method, the composite structure consisting of the carrier structure and the wafer structure is formed by means of a direct bonding process, in which the contact surface, which is particularly planar, and the bonding surface, which is particularly planar, are joined to form a common interface. The common interface can be an overlapping surface created during the joining process between the bonding surface and the contact surface, thus separating the wafer structure from the carrier structure and vice versa. In a direct bonding process, the common interface is particularly free of a bonding agent, such as an adhesion promoter. Alternatively, it is also possible for the carrier structure and the wafer structure to be mechanically bonded to one another by means of an alternative method, such as with a bonding layer.

[0013] In a direct bonding process, hydrophilic and hydrophobic surfaces are brought into physical contact. The basis of the mechanical bond is primarily or exclusively hydrogen bonding and / or van der Waals interactions in the immediate vicinity of the common interface. In a direct bonding process, the planar bonding surface and the planar contact surface can be brought together to form the joint in such a way that the common interface is formed by directly adjacent regions of the bonding surface and the contact surface, remaining free of any bonding material.

[0014] According to at least one embodiment of the method, internal mechanical stresses, such as shear stresses, are reduced in the composite of the support structure and the wafer structure. This can reduce the potential defect area at the common interface. The internal mechanical stresses in the composite can be reduced by selectively removing material from the composite. For example, the support structure can be thinned, such as by grinding, after being bonded to the wafer structure. In this process, material from the support structure, particularly the base structure, can be selectively removed such that the support structure, especially the base structure, has a reduced vertical layer thickness. The overall thickness of the support structure can thus be reduced by selectively removing material.Alternatively or additionally, to reduce internal stresses, it is possible to form recesses in the composite, for example in the support composite and / or in the wafer composite.

[0015] Particularly in direct bonding processes, even small defects on the bonding or contact surface can lead to the formation of large defect areas and thus to widespread failures of semiconductor devices. The radius of such a defect area depends, among other things, on the layer thicknesses of the wafer composite and the substrate composite. Reducing the layer thickness of the substrate composite can reduce the size of the defect area. Similarly, material removal, for example by creating recesses in the composite, leads to the spatial separation of the defect and thus also to a reduction in the defect area.

[0016] According to at least one embodiment, the reduction of mechanical stresses within the composite is carried out incrementally. This minimizes component losses, as components directly affected by foreign particles, for example, cannot be bonded. By reducing the layer thickness only after the substrate composite has been bonded to the wafer composite, the substrate composite can be designed to be particularly mechanically stable, for example, when applied to the wafer composite. This embodiment also allows for components with particularly low profiles due to the subsequent reduction of the overall layer thickness of the composite.

[0017] According to at least one embodiment of the process, the composite undergoes thermal treatment after the reduction of internal stresses. Such thermal treatment can lead to the generation of covalent bonds between atoms or molecules on the physically contacting interface and thus to increased bond strength between the wafer composite and the substrate composite. If the thermal treatment is performed after localized material removal, potential defect areas can be minimized before the mechanical bond between the wafer composite and the substrate composite is further strengthened by the thermal treatment. However, the thermal treatment can be optional.

[0018] According to at least one embodiment of the method, the contact surface of the substrate composite is formed partially or exclusively by the surface of an oxide layer, such as a silicon oxide layer, in particular a SiO2 layer. Preferably, the substrate is made of silicon or consists of silicon. A silicon oxide layer can be formed particularly easily on a silicon substrate, for example by depositing silicon oxide such as SiO2 onto the substrate or by oxidizing the substrate. The contact surface of the wafer composite can be formed partially or exclusively by the surface of an oxide layer, such as a silicon oxide layer, in particular a SiO2 layer. A component with a silicon substrate exhibits, for example, a particularly low thermal resistance and higher mechanical tensile strength compared to a molded substrate.

[0019] According to at least one embodiment of the method, the step of generating the separation grooves through the base body and the step of generating the separation grooves through the semiconductor assembly are at least partially carried out by two separate process steps. This means, in particular, that the separation grooves are not generated through both the base body and the semiconductor assembly in a single process step.

[0020] In a first process step, the separation grooves are formed such that they are created through the substrate, and that after this first step, the separation grooves do not extend, or at most only partially extend, into the semiconductor matrix. This means that during the first process step, the separation grooves are created through the substrate and / or the contact structure of the wafer matrix into the semiconductor matrix, and that after this first process step, the separation grooves do not extend through the semiconductor matrix. In a second process step, distinct from the first, the separation grooves are created through the semiconductor matrix approximately to the substrate, so that the semiconductor matrix is ​​separated into a plurality of individual, adjacent semiconductor bodies.In this case, the semiconductor bodies are arranged on the common substrate and are spatially separated from each other in later directions, approximately by the separation trenches. The substrate may be partially exposed in the areas of the separation trenches.

[0021] According to at least one embodiment of the method, the grid structure is formed by the separation trenches extending through the base body, wherein the grid structure serves as an etching mask in the second process step and the semiconductor body composite is etched through by supplying an etching agent into the grid structure.

[0022] The semiconductor matrix exists in an unstructured state before the separation grooves are formed. The separation grooves, or the areas within the semiconductor matrix intended for their formation, are therefore not defined before or during wafer bonding—that is, before or during the joining of the wafer matrix to the substrate—and are not lithographically defined. The dimensions of the components to be manufactured are determined primarily during the creation of the grid structure with its separation grooves extending through the substrate or the substrate. During wafer bonding, the semiconductor matrix is ​​thus formed in a single piece and is free of mesa grooves that define the dimensions of the semiconductor bodies to be formed and, consequently, the manufactured components.

[0023] The semiconductor matrix is ​​structured into multiple semiconductor bodies only after the separation channels have been created through the substrate. The wafer matrix or semiconductor matrix can thus be self-aligned to the grid structure following the structuring of the substrate or substrate, particularly without a separate lithography step. An etching process, such as plasma etching, deep reactive ion etching (DRIE), or reactive ion etching (Cl-RIE) with chlorine as the etchant, can be used. The formation of a mask, for example, using a photostructurable material on the wafer matrix prior to wafer bonding, can be omitted.

[0024] Since the semiconductor substrate is unstructured during wafer bonding, and the separation channels within the semiconductor substrate are fully self-aligned following the formation of the separation channels in the substrate—that is, specifically following the formation of the grid structure—maximum surface utilization of the semiconductor substrate can be achieved. This is because maintaining an alignment tolerance between the separation channels in the semiconductor substrate and those in the substrate is no longer necessary. Overall, this increases the efficiency of the process. Compared to conventional methods, at least one lithography step is also eliminated. Furthermore, using an etching process to separate the components significantly reduces the risk of delamination.

[0025] According to at least one embodiment of the process, the semiconductor matrix is ​​structured, either completely or partially, before wafer bonding, for example, before the separation channels are formed through the substrate. This means that the semiconductor matrix already has multiple openings at the locations of the separation channels to be formed, particularly during wafer bonding. These openings in the semiconductor matrix thus essentially determine the dimensions of the semiconductor bodies to be formed, and therefore of the devices to be manufactured, even before wafer bonding. The openings can be filled, or even completely filled, with an electrically insulating material. After wafer bonding, the openings are completely covered in a top view by the substrate, especially by the substrate. In a subsequent process step, the separation channels are created through the substrate, for example, directly above the openings located beneath them.

[0026] According to at least one embodiment of the method, the semiconductor assembly comprises a first semiconductor layer facing the substrate, a second semiconductor layer facing away from the substrate, and an active layer arranged between the first and second semiconductor layers. The openings in the semiconductor assembly can be configured to extend through the second semiconductor layer and the active layer. The openings can each form a blind hole in the semiconductor assembly, meaning that the openings extend only into the first semiconductor layer. Alternatively, the openings can be created before wafer bonding, for example, from a main surface of the semiconductor assembly facing away from the substrate, extending through the semiconductor assembly, particularly to the substrate, and then filled with an electrically insulating material in a further process step.

[0027] According to at least one embodiment of the process, the portions of the separation channels located within the semiconductor matrix are created, at least in certain areas, by partially removing the electrically insulating material present in the openings. The resulting side surfaces of the separation channels are covered, in particular, by the remaining electrically insulating material. This remaining electrically insulating material thus forms the passivation layer, at least in certain areas, and the passivation layer may partially or completely cover the side surfaces of the separation channels. For example, it is possible that the separation channels are not covered by the passivation layer in the area of ​​the substrate, i.e., they are free of the passivation layer in this area. In particular, the side surfaces of the separation channels are also the side surfaces of the components to be manufactured.

[0028] According to at least one embodiment of the method, the formation of the separation grooves in the area of ​​the semiconductor body assembly is achieved exclusively by partially removing the electrically insulating material located in the openings. The side surfaces of the separation grooves in the area of ​​the semiconductor body assembly are completely covered, in particular, by the remaining electrically insulating material. This remaining electrically insulating material thus forms the passivation layer, or a portion thereof, which approximately completely covers the sub-regions of the separation groove sides located in the area of ​​the semiconductor body assembly and / or in the area of ​​the contact structure. The sub-regions of the separation groove sides located in the substrate assembly or the base body may be formed by a further sub-region of the passivation layer.The remaining portion of the passivation layer is applied to the side surfaces of the trenches only after the grid structure or the separation channels have been formed through the base body. This portion and the remaining portion of the passivation layer can consist of the same electrically insulating material or different insulating materials.

[0029] According to at least one embodiment of the method, the passivation layer is formed partially or completely only after the separation grooves have been created through the substrate and / or after the separation grooves have been created through the semiconductor substrate. The passivation layer can be designed such that it covers, and in particular completely covers, a rear side of the substrate facing away from the wafer assembly.

[0030] According to at least one embodiment of the method, the substrate is a growth substrate, such as a sapphire substrate. The substrate can have a structured surface on which the semiconductor composite can be epitaxially grown such that the semiconductor composite has a main surface facing the growth substrate, which replicates the structured surface of the growth substrate. The substrate can be detached from the semiconductor composite in such a way that the individual components each have a structured main surface immediately upon detachment of the growth substrate. Alternatively, it is also possible for the growth substrate to be free of a structured surface. After detachment of the growth substrate, the individual components can subsequently be structured such that they each have a structured main surface.The structured main surface of the respective component is specifically designed as a radiation transmission and / or radiation emission surface. By using a structured growth substrate, the formation of, for example, output coupling structures on a radiation transmission or emission surface of a component can be simplified. A roughening process can be omitted. Furthermore, the removal of the substrate, for example by a laser lifting process, can be performed at the end of the manufacturing process, allowing the particularly mechanically stable substrate to be used as a rigid support during the manufacturing process.

[0031] According to at least one embodiment of the method, before the substrate is detached, an auxiliary carrier, for example in the form of a film, is applied to the composite such that the composite consisting of the wafer composite and the carrier composite is arranged between the substrate and the auxiliary carrier. After the substrate is separated from the composite, the individual components lie, in particular in an ordered manner, on the auxiliary carrier and can be processed more easily. In particular, the auxiliary carrier is stretchable, especially elastically stretchable. Due to the stretchability of the auxiliary carrier, the lateral spacing of the individual components can be adjusted accordingly, thus simplifying the further processing of the individual components, for example, by means of a pick-and-place machine.

[0032] Further advantages, preferred embodiments and further developments of the method will result from the following in conjunction with the Fig. Examples of implementation are explained in sections 1A to 3C. They show: Fig. 1A to 1H schematic sectional views of various process stages of an exemplary embodiment for the production of a plurality of components, and Fig. 2A to 3C schematic sectional views of some process stages of further embodiments for the production of a plurality of components.

[0033] Identical, similar, or similarly functioning elements are marked with the same reference symbols in the figures. The figures are schematic representations and therefore not necessarily to scale. Rather, comparatively small elements, and especially layer thicknesses, for example at layer transitions, may be exaggerated for clarity.

[0034] In Fig. Figure 1A shows a wafer assembly 200. The wafer assembly 200 has a semiconductor body assembly 20 arranged on a substrate 9. The substrate 9 is, in particular, a growth substrate, such as a sapphire substrate. The semiconductor body assembly 20 can be deposited layer by layer onto the substrate 9, for example, by means of an epitaxial process.

[0035] The semiconductor body assembly 20 has a first main surface 201 facing the substrate 9 and a second main surface 202 facing away from the substrate 9. In particular, the first main surface 201 is formed by a surface of a first semiconductor layer 21 of a first approximately n-type charge carrier, and the second main surface 202 by a surface of a second semiconductor layer 22 of a second approximately p-type charge carrier. The semiconductor body assembly 20 has an active layer 23 arranged between the first semiconductor layer 21 and the second semiconductor layer 22. In particular, the active layer is a pn junction region. During operation of the device to be manufactured, the active layer 23 is preferably configured for the detection or emission of electromagnetic radiation, for example in the visible, ultraviolet, or infrared spectral range.In particular, the components to be manufactured are optoelectronic components, especially light-emitting diodes.

[0036] The semiconductor body assembly 20 can be formed from a III / V compound semiconductor material. A III / V compound semiconductor material comprises one element from group 3, such as B, Al, Ga, In, and one element from group 5, such as N, P, As. In particular, the term "III / V compound semiconductor material" includes the group of binary, ternary, or quaternary compounds containing at least one element from group 3 and at least one element from group 5, for example, nitride and phosphide compound semiconductors. For example, semiconductor layers 21 and 22 are GaN-based. The semiconductor material can also include one or more dopants and additional components. The semiconductor body assembly 20 can also be formed from a II / VI compound semiconductor material.

[0037] It will be according to the Fig. 1B A contact structure 8 of the wafer assembly 200 is formed for electrical contacting the semiconductor body assembly 20. The semiconductor body assembly 20 is arranged between the substrate 9 and the contact structure 8. The contact structure 8 has an electrically conductive layer 80 and connection layers 81 and 82. The electrically conductive layer 80 can be formed as a highly reflective mirror layer. In particular, the electrically conductive layer 80 is part of a first connection layer 81. The first connection layer 81 also has a via 811, which extends in the vertical direction approximately from the second main surface 202 of the semiconductor body assembly 20 through the second semiconductor layer 22 and the active layer 23 into the first semiconductor layer 21.An insulating structure 812 is arranged in the semiconductor body composite 20 in certain areas, which completely surrounds the via 811 and electrically isolates the via from the second semiconductor layer 22 and from the active layer 23.

[0038] According to Fig. In 1B, a second connection layer 82 is arranged vertically between the semiconductor body composite 20 and the electrically conductive layer 80. The second connection layer 82 has an opening through which the via 811 extends. The electrically conductive layer 80 also has an opening through which the second connection layer 82 extends in certain areas. The connection layers 81 and 82 are specifically assigned to different electrical polarities of a component to be manufactured. In particular, the first connection layer 81 is intended for electrical contacting the first semiconductor layer 21, and the second connection layer 82 is intended for electrical contacting the second semiconductor layer 22. The connection layers 81 and 82 are electrically insulated from each other by an insulating layer 34, for example, by a silicon oxide or silicon nitride layer.In plan view, the insulation layer covers 34 - as in the . Fig. 1B shown - the connection layers 81 and 82 completely.

[0039] The insulating layer 34 has an exposed, in particular planar, contact surface 31. Preferably, the planar contact surface 31 is microscopically flat such that it can serve as an interface for direct bonding of the wafer composite 200. Fig. 1B, the planar contact surface 31 is formed exclusively by the surface of the insulating layer 34. Alternatively, it is also possible that the insulating layer 34 is polished in such a way that the resulting planar contact surface 31 is formed partly from the surface of the insulating layer 34 and partly from the surface of the connecting layers 81 and / or 82. According to Fig. 1B the wafer assembly 200 with the substrate 9, the semiconductor body assembly 20 and the contact structure 8 has a vertical layer thickness D.

[0040] In the Fig. In 1B, the wafer composite 200 has a plurality of contact structures 8, each assigned to one of the components to be manufactured, with the first contact layers 81 and the second contact layers 82 being spatially spaced apart from each other in the lateral direction. Alternatively, it is also possible that the first contact layers 81 are initially formed as a single unit at this stage of the process and are only separated from each other in a subsequent process step, for example, during the creation of separation trenches. The same applies analogously to the second contact layers 82.

[0041] According to Fig. In section 1C, a support structure 10 with a vertical layer thickness T is provided. The support structure 10 includes a base body 13 and has a connection surface 11. Preferably, the connection surface 11 is planar. The connection surface 11 is formed, in particular, by an exposed surface, such as an oxidized surface, of the base body 13. It is also possible that the connection surface 11 is formed by an exposed surface of a layer arranged on the base body 13, for example, an electrically insulating oxide layer such as an SiO2 layer. If the base body 13 is made of silicon, the connection surface 11 can be a surface of an SiO2 layer, which can be produced by oxidation of the base body 13 or by an SiO2 coating.

[0042] According to Fig. In step 1D, the wafer composite 200 is mechanically connected to the support composite 10 to form a joint composite. The contact surface 31 and the connection surface 11 are thereby brought together to form a common interface 1131. Due to the planar surfaces with particularly low roughness, the wafer composite 200 and the support composite 10 can be mechanically connected without the use of a bonding material such as an adhesion promoter, and solely due to van der Waals interactions and / or hydrogen bonds between the atoms on the planar surfaces. Alternatively, it is possible to mechanically connect the wafer composite 200 to the support composite 10 using a bonding layer.

[0043] In the Fig. Figure 1D shows the common interface 1131 resulting from a direct bonding process. The common interface 1131 is formed primarily by directly adjacent regions of the bonding surface 11 and the contact surface 31. The common interface 1131 thus represents a physical contact zone between the wafer composite 200 and the support composite 10. Particularly in a direct bonding process, a defect area may be present at the common interface 1131 (not shown here). This defect area is likely due to contamination, such as foreign particles between the wafer composite 200 and the support composite 10, or to local roughness on the planar contact surface 31 and / or on the planar bonding surface 11 that is relatively excessive for the direct bonding process.

[0044] It was found that the lateral radius of the defect area depends, among other things, on the vertical layer thickness T of the support composite 10, the vertical layer thickness D of the wafer composite 200, and on the material properties of the support composite 10 and the wafer composite 200. To reduce the potential defect area, approximately according to Fig. 1E reduces the vertical layer thickness of the support composite 10 after bonding it to the wafer carrier 200. Preferably, the base body 13 is thinned to a target thickness in the component to be manufactured. In particular, the support composite 10 can be thinned such that the vertical layer thickness of the support composite 10 and / or the base body 13 is reduced by at least 50% of its original value. Specifically, the vertical layer thickness of the support composite 10 and / or the base body 13 after the reduction is between 50% and 5%, for example between 50% and 10%, or between 50% and 30% of its original value. The reduction of the vertical layer thickness T leads to the minimization of potential defect areas, for example by locally increasing the common interface 1131, and thus to an improvement in the mechanical bond between the wafer composite 200 and the support composite 10.

[0045] According to Fig. 1E separation trenches 60 are created at least through the base body 13. The ones in the Fig. The separation trenches 60 shown in Figure 1E also extend partially through the contact structure 8 and the insulating layer 34. The semiconductor matrix 20 may be partially exposed in the separation trenches 60. The separation trenches 60 can be produced by an etching process, preferably a Bosch process, for example, by deep reactive ion etching (DRIE). For example, a mask is formed on a surface of the substrate 10 facing away from the wafer matrix 200, particularly using photostructurable material, wherein the mask defines the positions of the separation trenches 60. The mask can also be prefabricated and applied to the substrate 10.

[0046] In the Fig. In a first process step, the separation trenches 60 are formed such that at least the partial areas of the separation trenches 60 produced through the base body 13 form a grid structure 6. The grid structure 6 does not extend, or at most only partially extends, into the semiconductor body assembly 20 along the vertical direction. In a second process step, different from the first process step, the separation trenches 60 are formed through the semiconductor body assembly 20 ( Fig. 1F). For example, the grid structure 6 formed by the separation trenches 60 can serve as an etching mask in the second process step, whereby the semiconductor body assembly 20 is etched through, for example, by introducing an etchant into the grid structure 6. For example, the semiconductor body assembly 20 is etched through by reactive ion etching (RIE), for example, with chlorine as the etchant, for example, down to the substrate 9. Alternatively, a mechanical method can also be used to separate the semiconductor body assembly 20 into a plurality of semiconductor bodies.

[0047] According to Fig. 1E The semiconductor body assembly 20 is unstructured before the separation grooves 60 are formed. The semiconductor body assembly 20 is formed in one piece. The semiconductor body assembly 20 is only structured into a plurality of semiconductor bodies 2 after the separation grooves 60 have been created through the base body 13 ( Fig. 1F). The generation of the separation trenches 60 through the base body 13 and the generation of the separation trenches 60 through the semiconductor body assembly 20 are thus carried out at least partially by two different process steps, wherein the grid structure 6 is generated in a first process step and the semiconductor body assembly 20 is separated in a second process step.

[0048] According to Fig. In step 1G, a passivation layer 61 is formed, which completely covers the side surfaces of the separation grooves 60. The passivation layer 61 completely covers, in particular, the back side of the carrier assembly 10 facing away from the wafer assembly 200. Furthermore, the passivation layer 61 covers the side surfaces of the through-holes 41 and 42, which extend from the back side of the carrier assembly 10 through the base body 13 to the first connection layer 81 and the second connection layer 82, respectively. The components to be manufactured can be electrically connected externally via the back side through the through-holes 41 and 42. To form the through-holes 41 and 42, recesses are created through the base body 13 into the insulating layer 34 to partially expose the first connection layer 81 and / or the second connection layer 82.The recesses can subsequently be filled with an electrically conductive material to form the through-contacts 41 and 42. The first and second through-contacts are thus electrically connected to the first and second termination layers, respectively. The passivation layer 61 is formed, in particular, after the separation grooves 60 have been created through the semiconductor body assembly 200 and / or after the through-contacts 41 and 42 have been formed.

[0049] According to Fig. 1H Before separating the substrate 9, a particularly stretchable auxiliary carrier 90, for example in the form of a film, is applied to the composite such that the composite of the wafer composite 200 and the carrier composite 10 is arranged between the substrate 9 and the auxiliary carrier 90. The substrate 9 is then removed from the semiconductor body composite 20 or from the semiconductor bodies 2, for example by a mechanical and / or a chemical process and / or by a laser lift-off process. The composite of the carrier composite 10 and the wafer composite 200 is thus separated into a plurality of devices 100 such that the devices 100 each have a semiconductor body 2 as part of the semiconductor body composite 20 and a carrier 1 as part of the carrier composite 10.After the substrate 9 has been separated from the composite, the individual building elements 100 lie in a particularly ordered manner on the auxiliary carrier 90 and can be processed further in a simplified manner.

[0050] In the Fig. In 1H, each component 100 has a support 1 and a main body 210 arranged on the support 1. The support 1 and the main body 210 have a common interface 1131. The main body 210 comprises a semiconductor body 2 with an active layer 23 configured for radiation generation or radiation detection. The main body 210 further includes a contact structure 8, which has a via 811, an insulating structure 812, a first connection layer 81, and a second connection layer 82.

[0051] The individual components 100 each have a radiation transmission surface 101, which is formed approximately by a first main surface 201 of the semiconductor body 2. In the Fig. 1H is the radiation transmission area 101 shown above. In contrast to the Fig. The radiation transmission surface 101 of the component 100 can have coupling structures and thus be structured. The structuring of the radiation transmission surface 101 can be implemented before, during, or after the separation of the substrate 9 from the semiconductor body assembly 20. The component 100 has a back side 102 facing away from the radiation transmission surface 101. In particular, the back side 102 of the component 100 is formed by a back side 12 of the carrier 1. The component 100 can be electrically contacted externally via the back side 102 by means of the through-holes 41 and 42. The entire side surfaces of the isolated component 100 are completely covered by the passivation layer 61. Except for the through-holes 41 and 42, the passivation layer 61 completely covers the back side 102 of the component 100.

[0052] The in Fig. The embodiment shown in Figure 2A for a method for manufacturing a plurality of components essentially corresponds to the one described in the Fig. The embodiment shown in Figure 1D is different. In contrast, the semiconductor body assembly 20 is structured before wafer bonding such that it has a plurality of openings 25, particularly at the locations of the separation trenches 60 to be formed. The semiconductor body assembly 20 is already partially structured in this sense before the separation trenches 60 are formed. The openings 25 are filled, or in particular completely filled, with an electrically insulating material. For example, the insulating layer 34 has the same material as the material filling the openings 25.

[0053] In the Fig. In 2A, the openings 25 extend approximately from the second main surface 202 of the semiconductor body assembly 20 through the second semiconductor layer 22 and the active layer 23 into the first semiconductor layer 21. Alternatively, the openings 25 can extend to the substrate 9. In particular, the openings 25 are formed as a continuous structure. The openings 25 divide the semiconductor body assembly 20 into a plurality of semiconductor bodies, which are arranged according to Fig. However, 2A share the common first semiconductor layer 21. The openings 25 and the other openings provided, for example, for the vias 811, can be formed in the same process step and can have the same vertical depth.

[0054] The in Fig. The embodiment shown in Figure 2B for a method for manufacturing a plurality of components corresponds essentially to the one described in the Fig. In the embodiment shown in Figure 1E, the grid structure 6 with the separation grooves 60 is generated such that the separation grooves 60 extend into the semiconductor body composite 20. Similar to the openings 25, the separation grooves 60 extend through the second semiconductor layer 22 and the active layer 23 into the first semiconductor layer 21. In contrast, the separation grooves 60 can extend to the substrate 9. Within the semiconductor body composite 20, the separation grooves 60 are generated, at least partially, by partially removing the electrically insulating material located in the openings 25. Thus, the side surfaces of the separation grooves 60 are already covered by the remaining electrically insulating material when the separation grooves 60 are formed within the semiconductor body composite 20. The remaining material can therefore at least partially form the passivation layer 61.

[0055] According to Fig. In a further process step, the separation trenches 60 are created through the semiconductor body assembly 20. In this case, only the first semiconductor layer 21 is self-aligned to the grid structure 6, for example by means of an etching process. The semiconductor body assembly 20 is thereby separated into a plurality of individual semiconductor bodies 2. The individual semiconductor bodies 2 are arranged on the common substrate 9 and are, in particular, free of a common semiconductor layer. Further process steps, which are particularly relevant in the Fig. 1G and Fig. 1H described can also be used for the one described in the Fig. The embodiment shown in Figure 2C can be used. In particular, an electrically insulating material can be applied to the side surfaces of the separation grooves 60 and to the support composite 10 such that the passivation layer 61 formed thereby partially or completely covers the side surfaces of the separation grooves 60 and / or the side surfaces of the components 100 to be manufactured. It is also possible that the back surfaces of the respective individual components 100 are completely covered by the passivation layer 61, except for the through-contacts 41 and 42.

[0056] The in Fig. The embodiment shown in Figure 3A for a method for manufacturing a plurality of components essentially corresponds to the one described in the Fig. 2A illustrated embodiment.

[0057] In contrast, substrate 9 has a structured surface facing the semiconductor body composite 20. Unlike the Fig. In figures 1A to 2C, the substrate 9 shown in these figures can also have a structured surface. The semiconductor body assembly 20 is applied to the substrate 9 with the structured surface in such a way that the semiconductor body assembly 20 also has a structured main surface facing the substrate 9. Another difference is that the openings 25 filled with the electrically insulating material are already created before wafer bonding, i.e., before connecting the wafer assembly 200 to the support assembly 10, through the semiconductor body assembly 200, for example, through the second semiconductor layer 22 and the active layer 23 into the first semiconductor layer 21 or to the substrate 9.

[0058] According to Fig. 3B, the layer thickness T of the composite beam 10 will be analogous to the Fig. 1E and Fig. 2B reduced. Furthermore, the grid structure 6 is generated by forming a plurality of separation trenches 60 through the base body 13 during a first process step. In contrast to the approximately in the Fig. 1E and Fig. In the embodiments shown in 2B, the separation trenches 60 initially extend only from a rear side of the support assembly 10 facing away from the wafer assembly 200 to the common interface 1131. According to Fig. 3B, during the formation of the grid structure 6, first openings 51 and second openings 52 are also created, at least through the base body 13, to partially expose the first connection layers 81 and the second connection layers 82, respectively. In a subsequent process step, the first openings 51 and the second openings 52 can be filled with an electrically conductive material to form first through-contacts 41 and second through-contacts 42, respectively. Such openings 51 and 52 of the base body 13 and the carrier of the component to be manufactured can also be created in the Fig. 1E and Fig. 2B is realized during the generation of the grid structure 6. However, the generation of openings 51 and 52 can be optional when forming the grid structure 6 with the separating trenches 60.

[0059] The passivation layer 61 can be partially formed such that it completely covers the side surfaces of the separation grooves 60 of the grid structure 6 formed up to that point. The passivation layer 61 thus has sub-areas in the area of ​​the base body 13 that cover the side surfaces of the parts of the separation grooves 60 located in the base body 13, as well as the back surfaces 12 and 102 respectively, almost completely, except for the through-contacts 41 and 42. The passivation layer 61 can cover, and in particular completely cover, the side surfaces of the first openings 51 and second openings 52.

[0060] The formation of the separation trenches 60 in the area of ​​the semiconductor body assembly 20 can only be achieved by partially removing the electrically insulating material located in the openings 25 ( Fig. 3C). This can be achieved using an etching process or a mechanical process. The side surfaces of the separation grooves 60 in the area of ​​the semiconductor body composite 20 are almost completely covered with the remaining electrically insulating material, particularly during the creation of the separation grooves 60 in the area of ​​the semiconductor body composite 20. The remaining electrically insulating material can thus at least partially form the passivation layer 61.

[0061] The one in Fig. The embodiment shown in 3C with the auxiliary support 90 corresponds essentially to that shown in the Fig. 1H illustrated embodiment. In further contrast to this, the individual components 100 already have a structured main surface 101 or 201 when the structured growth substrate 9 is detached. Reference symbol list 100 building elements 101 Radiation transmission area 102 Back of the component 1 carrier 10 carrier network 11 Connecting surface 12 Back of the carrier 13 Basic body of the carrier 1131 common boundary area 2 Semiconductor bodies 20 Semiconductor composite 21 first semiconductor layer 22 second semiconductor layer 23 active layer 25 Opening of the semiconductor body composite 200 wafer composite 201 first main surface of the semiconductor body / composite 202 second main surface of the semiconductor body / composite 31 Contact area 34 Insulation layer 41 first contact 42 second through contact 51 First opening of the carrier 52 second opening of the carrier 6 Grid structure 60 Separation trench 61 Passivation layer 8 Contact structure 80 electrically conductive layer / mirror layer 81 first connection layer 82 second connection layer 811 Through-hole plating 812 Insulation structure 9 Substrate / Growing substrate 90 aid workers D layer thickness of the composite structure T layer thickness of the wafer composite

Claims

[1] Method for producing a plurality of components (100) comprising the following steps: - Providing a carrier assembly (10) with a coherent base body (13); - Providing a wafer assembly (200) with a coherent semiconductor body assembly (20) on a substrate (9); - connecting the wafer assembly to the carrier assembly to form a common assembly; - forming a plurality of separating trenches (60) at least through the base body (13) to form a grid structure (6) which defines the dimensions of the components (100) to be produced; - forming a passivation layer (61) covering the side surfaces of the separation trenches (60); and - separating the common composite, wherein the substrate (9) is detached from the semiconductor body composite (20) and the common composite is separated along the separating trenches (60) to form a plurality of components (100), wherein - the semiconductor body composite (20) is formed in one piece and free of mesa trenches before the wafer composite (200) is connected to the carrier composite (10), which define the dimensions of semiconductor bodies (2) to be formed and thus of the components (100) to be produced, and the dimensions of the components (100) to be produced are only defined during the production of the grid structure (6) with the separating trenches (60) extending through the base body (13), and - the semiconductor body composite (20) is unstructured before the separation trenches (60) are formed through the base body (13) to form the grid structure (6) and is only structured into a plurality of semiconductor bodies (2) in a self-aligned manner to form the grid structure (6) after the separation trenches (60) have been produced. [2] Method according to the preceding claim, in which the composite of the carrier composite (10) and the wafer composite (200) is formed by means of a direct bonding process in which - the carrier assembly (10) is provided with an exposed planar connecting surface (11), - the wafer assembly (200) is provided with an exposed planar contact surface (31) facing away from the substrate (9), - the planar connecting surface (11) and the planar contact surface (31) are brought together to form the common composite in such a way that a common interface (1131) is formed by directly adjacent regions of the connecting surface (11) and the contact surface (31) and is free of a connecting material. [3] Method according to claim 2, in which material of the composite is removed in places to reduce internal mechanical stresses, thereby reducing the possible defect area at the common interface (1131). [4] Method according to claim 2 or 3, wherein after the wafer composite (200) has been connected to the carrier composite (10), material of the base body (13) is removed in places such that a vertical layer thickness of the base body (13) is reduced. [5] Method according to one of the preceding claims, wherein the base body (13) is formed from an electrically insulating material or from a semiconductor material. [6] Method according to the preceding claim, wherein the base body (13) is formed from silicon and the connecting surface (11) is formed by a surface of a silicon oxide layer. [7] Method according to one of the preceding claims, in which the production of the separating trenches (60) through the base body (13) and the production of the separating trenches (60) through the semiconductor body composite (20) are carried out at least partially by two different method steps. [8] Method according to the preceding claim, in which the separating trenches (60) are formed in a first method step such that the separating trenches (60) are produced through the base body (13), wherein the separating trenches (60) do not extend or at most only partially extend into the semiconductor body composite (20) after the first method step, and the separating trenches (60) are produced through the semiconductor body composite (20) in a second method step different from the first method step. [9] Method according to the preceding claim, in which the grid structure (6) formed by the separating trenches (60) serves as an etching mask in the second method step and the semiconductor body composite (20) is etched through by supplying an etchant into the grid structure (6). [10] Method according to one of the preceding claims, wherein during the formation of the grid structure (6) a plurality of openings (51, 52) for forming through contacts (41, 42) are produced through the base body (13). [11] Method according to one of the preceding claims, in which - the substrate (9) is a growth substrate with a structured surface on which the semiconductor body composite (20) is epitaxially grown such that the semiconductor body composite (20) has a main surface (201) facing the growth substrate, which main surface replicates the structured surface of the growth substrate, and - the substrate (9) is detached from the semiconductor body composite (20) in such a way that the isolated components (100) each have a structured main surface (101, 201) upon detachment of the growth substrate (9). [12] Method according to one of the preceding claims, in which - the separating trenches (60) are formed in a first method step such that the separating trenches are produced through the base body (13), wherein the separating trenches do not extend, or at most only partially extend, into the semiconductor body composite after the first method step, and - the separating trenches are produced through the semiconductor body composite (20) in a second method step which is different from the first method step, wherein the grid structure (6) formed by the separating trenches serves as an etching mask in the second method step and the semiconductor body composite (20) is etched through by supplying an etchant into the grid structure (6).

Images