Multi-cell power conversion method with fault detection and multi-cell power converter

Abstract

A process that exhibits: Detecting a faulty converter cell (22) in a power converter that includes several first converter cells (11-1N1), several second converter cells (21-2 N3 ) and several intermediate circuit capacitors (111-1 N2 ) exhibits, wherein each of the several intermediate circuit capacitors (111-11 N2 ) one of the several first converter cells (11-1N1) and one of the several second converter cells (21-2 N3 ) connects; and deactivating the faulty converter cell (22) while maintaining power conversion operation of the power converter, wherein each of the several first converter cells (11-1N1) has a cell input and each of the several second converter cells (21-2 N3 ) has a cell output, wherein the cell inputs of the several first converter cells (11-1N1) are connected in series to one input of the power converter, wherein the cell outputs of the several second converter cells (21-2 N3 ) are connected in parallel to one output of the power converter, wherein detecting the faulty transducer cell involves detecting a faulty second transducer cell (22), and where the deactivation of the faulty second converter cell (21-2 N3 ) shows: the termination of the cell output of the faulty second converter cell (21-2 N3 ) from the output of the power converter, and either operating the first converter cell (12), which is connected to the faulty second converter cell (22), at an average output power of zero and an instantaneous output power depending on an input voltage (V) obtained at the input of the power converter IN ) or short-circuiting the cell input of the first converter cell (12) which is connected to the faulty second converter cell (22).

Description

[0001] This description generally applies to power conversion processes and power converters.

[0002] Power conversion is an important topic in many different electronic applications. A key aspect of almost every type of power conversion is to convert power efficiently, that is, to keep losses that can occur in connection with the power conversion as low as possible.

[0003] EP 1 523 088 A2 Power converter arrangement with several parallel-connected input stages connected to a voltage network and several parallel-connected output stages used to control a motor. The input stages and the output stage are coupled via a common intermediate circuit.

[0004] US 2011 / 0133461A1 describes a power converter arrangement with two parallel-connected converter stages, each comprising a first converter and a second converter coupled via a DC link capacitor. The converter stages are monitored for faults. If a fault occurs in one of the converter stages, the respective converter stage is shut down.

[0005] US 2006 / 0 214 428 A1 describes a power converter arrangement with several parallel-connected converter stages, each having a first converter and a second converter coupled via an intermediate circuit capacitor.

[0006] US patent 2009 / 0322083A1 discloses an integrated fault detection system in a wind turbine. The system is designed to interrupt the energy supplied to a power converter, thereby minimizing the energy available for arcing.

[0007] DE 102013 113 526 A1 describes a power converter arrangement and a power conversion method. The power converter arrangement comprises several input stages connected in series at one input of the power converter arrangement, and several output stages, each coupled to one of the input stages and connected in parallel at one output of the power converter arrangement.

[0008] US 2006 / 0 273 770 A1 describes a power converter arrangement with multiple DC / DC stages, the inputs of which are connected in parallel to an input voltage source and the outputs of which are connected in series to supply a load.

[0009] KASPER, M. et al.: Hyper-efficient (98%) and super-compact (3.3kW / dm3) isolated AC / DC telecom power supply module based on multi-cell converter approach. In: 2014 IEEE Energy Conversion Congress and Exposition (ECCE), Pittsburgh, PA, USA, 2014, pp. 150-157, describes a power converter arrangement with multiple converter stages, each comprising a first and a second converter coupled via DC link capacitors. The inputs of the first converter are connected in series and coupled to an input voltage source, and the outputs of the second converter are connected in parallel to supply a load.

[0010] The subsequently published patent applications DE 10 2015 115 071 A1, DE 10 2015 115 037 A1, DE 10 2015 115 042 A1, DE 10 2015 115 041 A1, and DE 10 2015 115 069 A1 each describe a power converter circuit with several first converter cells connected in parallel or in series at an input of the power converter arrangement, and several second converter cells connected in parallel or in series at an output of the power converter arrangement, wherein each of the first converter cells is coupled to one of the second converter cells via an intermediate circuit capacitor. These patent applications describe embodiments and methods for operating such a power converter circuit according to the following explanation. Fig. 1-90.

[0011] One embodiment of the invention relates to a method according to claim 1.

[0012] Further embodiments of the invention relate to a method according to claim 2 and power converters according to claims 3 and 4.

[0013] Experts will recognize additional features and benefits upon reading the following detailed description and examining the accompanying drawings.

[0014] Examples are explained below using drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are shown. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. Fig. Figure 1 illustrates a power converter circuit with two power converters; Fig. Figures 2A-2C show timing diagrams illustrating some different types of power conversion processes; Fig. Figures 3A-3C show timing diagrams illustrating some different types of power conversion processes; Fig. Figure 4 shows an embodiment of a power converter circuit with an ISOP (Input Serial, Output Parallel) topology; Fig. Figure 5 shows an embodiment of a power converter circuit with an ISOS (Input Serial, Output Serial) topology; Fig. Figure 6 shows an embodiment of a power converter circuit with an IPOS (Input Parallel, Output Serial) topology; Fig. Figure 7 shows an embodiment of a power converter circuit with an IPOP (Input Parallel, Output Parallel) topology; Fig. Figure 8 shows two converter cells of a power converter circuit, one of which has an insulating topology and the other a non-insulating topology; Fig. Figure 9 shows two converter cells of a power converter circuit, one of which has an insulating topology and one of which has a non-insulating topology; Fig. Figure 10 shows two converter cells of a power converter circuit, both of which have a non-isolating topology; Fig. Figure 11 shows an embodiment of a rectifier circuit; Fig. Figure 12 shows an embodiment of a multi-cell power converter with an IS (Input Serial) topology; Fig. Figure 13 shows an embodiment of a main controller in which the Fig. 12 multi-cell power converters shown; Fig. Figure 14 shows an embodiment of the Fig. The controllers shown in 13 are described in more detail; Fig. Figure 15 schematically illustrates an embodiment of an input voltage of the Fig. 12 multi-cell power converters shown and an associated modulation index; Fig. Figure 16 shows an embodiment of a cell controller of a converter cell in which the Fig. 12 multi-cell power converters shown; Fig. Figure 17 shows time courses representing an operating mode of the in Fig. 16 controllers shown illustrate this; Fig. Figure 18 shows an embodiment of a PWM controller in which the Fig. 17 cell controllers shown; Fig. 19A-19B show timing diagrams representing an operating mode of the in Fig. 12 illustrated multi-cell power converters at different modulation indices; Fig. Figure 20 schematically illustrates an exemplary embodiment of an input voltage signal waveform of the in Fig. 12 multi-cell power converters shown and an associated total cell input voltage; Fig. 21 illustrates how cell controllers are located in individual converter cells of the in Fig. The 12 multi-cell power converters shown can be synchronized; Fig. 22 shows a modification of the in Fig. 18 PWM controllers shown; Fig. 23 shows time diagrams that illustrate a different operating mode of the in Fig. 12 illustrated multi-cell power converters; Fig. Figure 24 shows a converter cell of a multi-cell power converter according to an exemplary embodiment; Fig. 25A-25B show timing diagrams that represent an operating mode of the in Fig. 24 illustrate the converter cell shown; Fig. Figures 26A-26B show two embodiments of a cell controller as described in the Fig. converter cell shown in 25A-25B; Fig. Figure 27 schematically illustrates an exemplary embodiment of an input voltage signal waveform of a device in Fig. 12 multi-cell power converters shown, when used with a Fig. 24 shown converter cell is realized, and an associated total cell input voltage; Fig. 28 shows a modification of the in Fig. 14 main controllers shown; Fig. Figure 29 shows an embodiment of a multi-cell power converter with an IP (Input Parallel) topology; Fig. Figure 30 shows an embodiment of a controller in one of the Fig. 29 converter cells shown; Fig. Figure 31 shows an embodiment of a multi-cell power converter with an OP (Output Parallel) topology; Fig. Figures 32A-32B show two embodiments of a converter cell, which is located in the Fig. The 31 multi-cell power converters shown can be used; Fig. Figure 33 shows an embodiment of a main controller in which the Fig. 31 multi-cell power converters shown; Fig. Figure 34 shows an embodiment of a multi-cell power converter with an OS (Output Serial) topology; Fig. Figure 35 shows an embodiment of a main controller of the in Fig. 34 multi-cell power converters shown; Fig. Figure 36 shows in further detail an embodiment of the Fig. 35 main controllers shown; Fig. Figure 37 shows an embodiment of a multi-cell power converter with an OP (Output Parallel) topology; Fig. Figure 38 shows an embodiment of a multi-cell power converter with an IP (Input Parallel) topology; Fig. Figure 39 shows an embodiment of a main controller in which Fig. 38 multi-cell power converters shown; Fig. Figure 40 schematically illustrates the efficiency of a converter cell based on the power level of the converted power; Fig. Figures 41A-41B show timing diagrams illustrating the activation and deactivation of converter cells (phase shedding) in a multi-cell power converter with OP topology; Fig. Figure 42 schematically illustrates how a number of inactive converter cells in a multi-cell power converter with OP topology can be determined depending on an output power; Fig. 43 illustrates an embodiment for operating a multi-cell converter with OP topology; Fig. Figure 44 shows an embodiment of a main controller in a multi-cell power converter which has a phase-shedding functionality; Fig. Figures 45A-45B show timing diagrams illustrating the activation and deactivation of converter cells (phase shedding) in a multi-cell power converter with IP topology; Fig. Figure 46 schematically illustrates how a number of inactive converter cells in a multi-cell power converter with IP topology can be determined depending on an output power; Fig. 47 illustrates an embodiment for operating a multi-cell converter with IP topology; Fig. Figure 48 shows an embodiment of a main controller in a multi-cell power converter with phase shedding functionality; Fig. Figure 49 shows an embodiment of a main controller in a multi-cell power converter with phase shedding functionality; Fig. Figure 50 shows timing diagrams illustrating an operating mode of an IS or OS multi-cell converter in intermittent operation; Fig. Figure 51 shows an embodiment of a main controller in an IS multi-cell converter which has functionality for intermittent operation; Fig. Figure 52 shows an embodiment of a main controller in an IS multi-cell converter which has functionality for intermittent operation; Fig. Figure 53 shows time courses illustrating an operating mode of an IP or OP multi-cell converter in intermittent operation; Fig. Figure 54 shows timing diagrams illustrating an operating mode of an IP or OP multi-cell converter in intermittent operation; Fig. Figure 55 shows a section of a power converter circuit that includes an output capacitor; Fig. Figure 56 shows an embodiment for operating a multi-cell converter with an OP topology in intermittent operation; Fig. Figure 57 illustrates an embodiment for operating a multi-cell converter with an IP topology in intermittent operation; Fig. Figure 58 shows an embodiment of a main controller in a multi-cell converter with OP topology; Fig. Figure 59 shows an embodiment of a main controller in a multi-cell converter with IP topology; Fig. Figure 60 shows an embodiment of a multi-cell converter which includes a filter cell; Fig. 61 shows an embodiment of the in Fig. 60 filter cells shown; Fig. Figure 62 shows an embodiment of a main controller in which the following is located: Fig. 60 multi-cell converters shown; Fig. Figure 63 shows time diagrams that represent an operating mode of the in Fig. 60 illustrated multi-cell converters; Fig. 64 shows an embodiment for operating the in Fig. 60 multi-cell converters shown; Fig. Figure 65 shows time diagrams that represent an operating mode of the in Fig. 60 illustrated multi-cell converters; Fig. Figure 66 shows an embodiment of a multi-cell converter which includes a filter cell; Fig. 67 shows an embodiment of the Fig. 66 filter cells shown; Fig. Figure 68 shows an embodiment of a main controller in which the following is located: Fig. 66 multi-cell converters shown; Fig. 69 shows an embodiment for operating the in Fig. 66 multi-cell converters shown; Fig. Figure 70 shows two converter cells of a multi-cell converter and a switching circuit that connects the cell inputs either in series or in parallel; Fig. Figure 71 shows time diagrams that represent an operating mode of the in Fig. 70 converter cells are shown to illustrate this; Fig. Figure 72 shows an embodiment of a main controller in a multi-cell converter with two converter cells that can be rearranged, as described in Fig. 70 are shown; Fig. Figure 73 shows two converter cells of a multi-cell converter and a switching circuit that connects the cell inputs either in series or in parallel; Fig. Figure 74 shows time diagrams that represent an operating mode of the in Fig. 73 converter cells illustrate this; Fig. Figure 75 shows an embodiment of a main controller in a multi-cell converter with two converter cells that can be rearranged, as described in Fig. 73 are shown; Fig. Figures 76A-76B illustrate an unequal distribution of power and current shares in a multi-cell converter; Fig. Figure 77 shows an embodiment of a main controller designed to control the distribution of power or current components in a multi-cell converter with an IP topology; Fig. Figure 78 shows an embodiment of a main controller designed to control the distribution of power or current components in a multi-cell converter with an OP topology; Fig. Figures 79A-79B show timing diagrams illustrating the operation of a multi-cell converter with an IS or OS topology such that the intermediate circuit voltages have different voltage levels; Fig. Figure 80 shows an embodiment of a main controller configured to control a multi-cell converter as described in the Fig. 79A-79B is shown, to operate; Fig. Figure 81 shows an embodiment of a half-bridge in a converter cell of a multi-cell converter; Fig. 82 shows timing diagrams illustrating PWM operation of the in Fig. 81 illustrates the depicted half-bridge; Fig. 83 illustrates losses that occurred in the Fig. 81 half-bridge shown, different duty cycles of a PWM operation occur with some different half-bridge designs; Fig. Figure 84 shows an embodiment of a method for optimizing the operation of a multi-cell power converter by operating the individual converter cells differently; Fig. Figure 85 shows an embodiment of a main controller in an IS multi-cell converter with optimization functionality as described in Fig. 84 is illustrated; Fig. Figure 86 shows an embodiment of a main controller in an OS multi-cell converter with optimization functionality as described in Fig. 84 is illustrated; Fig. Figure 87 shows an embodiment of a bridge circuit in a multi-cell converter; Fig. Figure 88 shows an embodiment of a power converter circuit comprising a multi-cell converter and a single-cell converter; Fig. Figure 89 shows an embodiment of a power converter circuit comprising a multi-cell converter that receives several DC voltages from different power sources; Fig. Figure 90 shows an embodiment of a power converter circuit comprising a multi-cell converter and several single-cell converters coupled to the multi-cell converter; Fig. 91 shows an embodiment of a power converter circuit with a fault management unit; Fig. Figure 92 shows an embodiment of a power converter circuit with an ISOP topology and with a fault management unit; Fig. 93A - 93B show timing diagrams that illustrate an operating mode of the in Fig. 92 illustrates the power converter circuit shown in normal operation and fault operation; Fig. 94A - 94B show timing diagrams that illustrate an operating mode of the in Fig. 92 illustrates the IS converter shown in normal operation and fault operation; Fig. Figure 95 shows an embodiment of a main controller configured to control the IS converter in the Fig. to operate as shown in 94A - 94B; Fig. 96 shows an embodiment for synchronizing converter cells in which in Fig. 92 IS converters shown; Fig. Figure 97 shows an embodiment of a PWM controller implemented in a cell controller; Fig. 98 shows time diagrams that represent an operating mode of the in Fig. Figure 92 illustrates the IS converter in fault operation; Fig. Figure 99 shows an embodiment of a main controller configured to control the IS converter as shown in Fig. 98 shown to operate; Fig. Figure 100 shows an embodiment of a converter cell in an IS converter; Fig. Figure 101 shows another embodiment of a converter cell in an IS converter; Fig. 102 shows an operating mode of the in Fig. 92 power converter circuit shown in fault operation; and Fig. Figure 103 shows an embodiment of a power converter circuit with an IPOS topology and with a fault management unit.

[0015] The following detailed description refers to the accompanying drawings. The drawings form part of the description and illustrate specific embodiments of how the invention can be implemented. Naturally, the features of the various embodiments described herein can be combined unless explicitly stated otherwise.

[0016] The following are some exemplary embodiments of power conversion methods and power converter circuits, explained with reference to the drawings. These power converter circuits comprise at least one power converter with multiple power converter cells. A power converter comprising multiple power converter cells is hereinafter referred to as a multi-cell power converter or multi-cell converter. A power conversion method that uses at least one multi-cell converter is referred to as a multi-cell power conversion method.

[0017] Fig. Figure 1 shows an embodiment of a power converter circuit designed to convert an input power P received at an input IN1, IN2. IN into an output power P provided at an output OUT1, OUT2 OUT to convert. The input power P IN is defined as the product of an input current I obtained at inputs IN1 and IN2 INand an input voltage V IN between a first input node IN1 and a second input node IN2 of the input, such that P IN =V IN ·I IN The output power P OUT is defined as the product of an output current I provided at output OUT1, OUT2 OUT and an output voltage V OUT between a first output node OUT1 and a second output node OUT2 of the output, such that P OUT =V OUT ·I OUT A load Z (in Fig. (1 shown in dashed lines) the output power P provided by the second power converter 20 OUT receive.

[0018] The power converter circuit comprises a first converter 10, configured to receive the input power at inputs IN1 and IN2, and a second power converter 20, configured to provide the output power at outputs OUT1 and OUT2. At least one of the first power converter 10 and the second power converter 20 comprises several power converter cells, which are hereinafter referred to simply as converter cells. In the circuit described in Fig. In the embodiment shown in 1, the first power converter 10 comprises several converter cells 11-I N1 , and the second power converter 20 comprises several converter cells 21-2 N3 These converter cells are in Fig. Figure 1 is only schematically illustrated. The first power converter 10 and the second power converter 20 are separated by several capacitors 111-11. N2 connected. These capacitors 111-11 N2These are also referred to as DC link capacitors. The capacitance of each DC link capacitor depends on various factors, such as the waveform of the input and / or output voltage, or the power rating of the power converter circuit, to name just a few. In one embodiment, the capacitance of the DC link capacitors is selected from a range between a few microfarads (µF), such as 2 µF, and a few millifarads (mF), such as 9 mF.

[0019] Referring to Fig. 1 The first power converter 10 can comprise a first number N1 of converter cells 11-N1, a second number N2 of capacitors 111-11 N2 can connect the first power converter 10 and the second power converter 20, and the second power converter 20 can connect a third number N3 of converter cells 21-2 N3include. According to one embodiment, the first number N1, the second number N2 and the third number N3 are equal, such that N1=N2=N3=N.

[0020] Depending on how the first power converter and the second power converter 20 are implemented, different types of power conversion methods can be performed by the power converter circuit. Some of these different types of power conversion methods are shown below. Fig. 2A-3C explained. Each of these Fig. 2A-3C schematically illustrates timing diagrams of the input voltage V IN and the output voltage V OUT .

[0021] Referring to Fig. 2A can be the input voltage V IN a rectified sinusoidal voltage and the output voltage V OUT Can a DC voltage with a voltage level lower than a peak voltage of the input voltage V be applied? IN be. Referring to Fig. 2B can measure the input voltage V IN be a sinusoidal voltage and the output voltage V OUT A DC voltage with a voltage level lower than the amplitude of the input voltage V can be generated. IN be. A rectified sinusoidal voltage, as used in Fig. The voltage shown in 2A can be obtained by rectifying a sinusoidal voltage, such as that shown in Fig. Figure 2B shows that, according to one embodiment, the sinusoidal voltage is a mains voltage of 110V. EFF or 220V EFF and a frequency of 50 Hz or 60 Hz. That in Fig. The power conversion method shown in Figure 2B can be used in a variety of different applications where a load Z is to be supplied with direct current (DC) power from a voltage network. Examples of such applications include telecommunications exchanges, computers, or similar devices. Referring to Fig. 2C can handle any of the input voltage V INand the output voltage V OUT be a DC voltage, where one voltage level is the input voltage V IN is higher than a voltage level of the output voltage V OUT .

[0022] Referring to Fig. 3A can set the output voltage V OUT a rectified sinusoidal voltage and the input voltage V IN Can a DC voltage with a voltage level lower than a peak voltage of the output voltage V OUT be. Referring to Fig. 3B can adjust the output voltage V OUT be a sinusoidal voltage and the input voltage V IN A DC voltage with a voltage level lower than the amplitude of the output voltage V can be generated. OUT be. According to one embodiment, the in Fig. The sinusoidal voltage shown in 3B represents a mains voltage of 120V. EFF or 220V EFF and a frequency of 50 Hz or 60 Hz. The type of power conversion as used in Fig. As shown in Figure 3B, it can be used in applications where power is to be supplied from a DC power source, such as a photovoltaic panel, a battery, or similar, to a power grid. Referring to Fig. 3C can handle any of the input voltages V IN and the output voltage V OUT be a DC voltage, where one voltage level is the input voltage V IN is lower than a voltage level of the output voltage V OUT .

[0023] In the Fig. In the exemplary embodiments shown in 2A-2C, the voltage level of the output voltage V is OUT lower than the voltage level or effective voltage level of the input voltage V INA power converter circuit designed to perform one of these types of power conversion will subsequently be referred to as a buck-shift power converter circuit. In the following, Fig. In the exemplary embodiments shown in 3A-3C, the voltage level of the input voltage V is IN lower than the voltage level or the effective voltage level of the output voltage. Hereinafter, a power converter circuit designed to perform one of these types of power conversion is referred to as a boost-charging power converter circuit.

[0024] Four different power converter circuits of the in Fig. The types shown below are based on the Fig. 4-7 explained. In each of these embodiments, each of the first power converter 10 and the second power converter 20 comprises several converter cells. Furthermore, in each of these embodiments, N1 = N2 = N3 = N, such that each of the several converter cells in the first power converter 10 is connected to one of the several converter cells in the second power converter 20 by an intermediate circuit capacitor. This is, however, only one example. Other examples, in which only one of the first and second power converters 10, 20 comprises several converter cells, or in which at least two of N1, N2, and N3 differ, are explained below. The examples in the Fig. The power converter circuits shown in 4-7 differ in how the converter cells of the first power converter 10 are connected to the input IN1, IN2 and how the converter cells of the second power converter 20 are connected to the output OUT1, OUT2.

[0025] Fig. Figure 4 shows an embodiment of a power converter circuit with an ISOP (Input Serial, Output Parallel) topology. In this power converter circuit, the converter cells 11-1 N1 of the first power converter at input IN1, IN2 connected in series and the converter cells 21-2 N3 The outputs of the second power converter 20 are connected in parallel at outputs OUT1 and OUT2. This is explained below.

[0026] The converter cells 11-1 N1 The first power converter 10 are hereinafter also referred to as first converter cells. Each of these first converter cells 11-1 N1 comprises a cell input and a cell output. The cell output of each converter cell 11-1 N1 is connected to one of the several intermediate circuit capacitors 111-11 N2 connected, namely to the intermediate circuit capacitor, which is connected to the respective first converter cell 11-1 N1 is assigned. The cell inputs of the first converter cells 11-1N1 are connected in series at inputs IN1 and IN2 of the power converter circuit. This means that a first cell input node of one of the first several converter cells (of converter cell 11 where in Fig. (as shown in the exemplary embodiment 4) is connected to the first input node IN1. A second cell input node of another of the several first converter cells (the first converter cell 1) N1 at the in Fig. (as shown in the exemplary embodiment 4) is connected to the second input node IN2 of the power converter circuit. The other first converter cells (which are in Fig. The four illustrated converter cells (12, 13) each have their first cell input node connected to the second cell input node of another first converter cell, and have their second cell input node connected to the first cell input node of another first converter cell. In other words, the cell inputs of each first converter cell (11-1)N1 form a cascade between the input nodes IN1, IN2 of the power converter circuit.

[0027] The converter cells 21-2 N3 The second power converter 20 are hereinafter also referred to as second converter cells. Each of these second converter cells 21-2 N3 comprises a cell input and a cell output. The cell input of each converter cell 21-2 N1 is connected to one of the several intermediate circuit capacitors. The cell outputs of the second converter cells 21-2 N3 The outputs OUT1 and OUT2 of the power converter circuit are connected in parallel. This means that a first cell output node of each of the second converter cells 21-2 N3 is connected to a first output node OUT1 of the power converter circuit and the second cell output node of each of the second converter cells 21-2 N3 is connected to the second output node OUT2 of the power converter circuit.

[0028] At the in Fig. In the power converter circuit shown in section 4 with the ISOP topology, each of the first converter cells connected in series receives 11-I N1 a proportion or part of the input voltage V IN as cell input voltage V11-V1 N1 That is, a sum of the cell input voltages V11-V1 N1 corresponds to the input voltage V IN , VIN=∑i=1N1V1i

[0029] A cell input current of each first converter cell 11-1 N1 is equal to the input current I IN Furthermore, each of the parallel-connected second converter cells represents 21-2 N3 a cell output current I21-I2 N3 available, which is a proportion or part of the output current I OUT is. That is, a sum of the cell output currents I21-I2 N3 corresponds to the output current I OUT , IOUT=∑i=1N3I2i

[0030] One cell output voltage of each of the second converter cells corresponds to the output voltage V OUT the power converter circuit.

[0031] Fig. Figure 5 shows an embodiment of a power converter circuit with an ISOS (Input Serial, Output Serial) topology. As in the Fig. The first converter cells 11-1 are shown in the 4 depicted power converter circuit. N1 At inputs IN1 and IN2, they are connected in series. The in Fig. The power converter circuit shown in section 5 differs from the one in Fig. 4 power converter circuit shown, by the fact that the second converter cells 21-2 N3 Outputs OUT1 and OUT2 are connected in series. This is explained below.

[0032] Referring to Fig. 5 is a first cell output node of one of the several second converter cells (the converter cell 21 at which in Fig. (as shown in the exemplary embodiment 5) is connected to the first output node OUT1. A second cell output node of another of the several second converter cells (the second converter cell 2) is connected. N3 at the in Fig. (as shown in the embodiment 5) is connected to the second output node OUT2 of the power converter circuit. The other second converter cells (which are in Fig. The five illustrated converter cells (22, 23) each have their first cell output node connected to the second cell output node of another second converter cell, and have their second cell output node connected to the first cell output node of another second converter cell. In other words, the cell outputs of each second converter cell (21-2) N3 They form a cascade between the output nodes OUT1 and OUT2 of the power converter circuit. In this embodiment, a cell output voltage V31-V3 is used. N3each of the several second converter cells 21-2 N3 a portion of the output voltage V OUT the power converter circuit. That means VOUT=∑i=1N3V3i

[0033] A cell output current of each of the several second converter cells 21-2 N3 is equal to the output current of the power converter circuit.

[0034] At the in Fig. The power converter circuit shown in section 5 is, as in the one described in Fig. 4 power converter circuit shown, the cell output of each of the first converter cells 11-1 N3 to one of the several intermediate circuit capacitors 111-11 N2 connected, and the cell input of each of the second converter cells 21-2 N3 is connected to one of the intermediate circuit capacitors 111-11 N2 connected, with each of the intermediate circuit capacitors 111-11 N2 only one first converter cell and only one second converter cell is connected.

[0035] Fig. Figure 6 shows an embodiment of a power converter circuit with an IPOS (Input Parallel, Output Serial) topology. As in the Fig. The second converter cells 21-2 are shown in the 5 depicted power converter circuit. N3 Outputs OUT1 and OUT2 are connected in series. The... Fig. The power converter circuit shown in section 6 differs from the one in Fig. 5 power converter circuit shown, by the fact that the first converter cells 11-1 N3 The inputs IN1 and IN2 are connected in parallel. That is, each of the first converter cells 11-1 N1 has connected its first cell input node to the first input node IN1 of the power converter circuit and has connected its second cell input node to the second input node IN2 of the power converter circuit. Thus, each of the first converter cells receives 11-1 N1 the input voltage V INas a cell input voltage, and a cell input current I01-I0 N1 each of the first converter cells 11-I N1 is a proportion or part of the input current I OUT , so that IIN=∑i=1N1I0i

[0036] Fig. Figure 7 shows an embodiment of a power converter circuit with an IPOP (Input Parallel, Output Parallel) topology. In this power converter circuit, the first converter cells are 11-1 N1 At inputs IN1 and IN2, connected in parallel, and the second converter cells 21-2 N3 are connected in parallel at the output. Regarding the parallel connection of the first converter cells 11-1 N1 will be on Fig. Reference is made to section 6 and the associated description, and regarding the parallel connection of the second converter cells 21-2 N3 will be on Fig. Reference is made to section 4 and the associated description.

[0037] Each of the first converter cells 11-1 N1and the second converter cells 21-2 N3 is implemented with a power converter topology and is designed to receive cell input power at the cell input and provide cell output power at the cell output. Each of the first converter cells 11-1 N1 Each cell receives its input power from inputs IN1 and IN2. The cell output power of each of the first converter cells 11-I N1 is the power that the respective first converter cell delivers to the intermediate circuit capacitor connected to the cell output or to the second converter cell connected to the cell output. The cell input power of each of the several second converter cells 21-2 N3This is the power that each second converter cell receives from the intermediate circuit capacitor to which it is connected, or from the first converter cell to which it is connected. Each of the second converter cells delivers its cell output power to outputs OUT1 and OUT2. The intermediate circuit capacitors 111-11 N2 are able to store energy, so that the power level of the cell output power of one of the first converter cells 11-1 N1 and the power level of the cell input power of the associated second converter cell may differ. Hereinafter, the word "associated" is used to describe the relationship between a first converter cell, the DC link capacitor connected to that first converter cell, and the second converter cell connected to that first converter cell and this DC link capacitor.

[0038] The type of converter topology used in the first converter cells 11-1 N1and the second converter cells 21-2 N3 The implementation depends, for example, on the type of power conversion performed by the power converter circuit. In general, the converter cells 11-1 N1 , 21-2 N3 This can be implemented with an isolating power converter topology or with a non-isolating power converter topology. In the first case, each converter cell includes a transformer that galvanically isolates the cell input and cell output. In the second case, the cell input and cell output of the converter cell are not galvanically isolated. This is illustrated below by the Fig. Explained in sections 8-10. Each of these figures shows a first converter cell 1. i , the intermediate circuit capacitor 11 i the first converter cell 1 i and one connected to the first converter cell 1 i connected second converter cell 2 i The first converter cell 1 i and the second converter cell 2 irepresent any pair of a first converter cell 11-1 N1 and one connected to the first converter cell 11-1 N1 connected converter cell 21-2 N3 in any of the power converter circuits described above.

[0039] At the in Fig. In the embodiment shown in Figure 8, the first converter cell is 1. i implemented with an isolating converter topology. This is indicated by the transformer symbol in the circuit block representing the first converter cell 1. i represented, schematically illustrated. The second converter cell 2 i is implemented with a non-isolating converter topology. In a power converter circuit, in which the first converter cells 11-1 N1 are implemented with an isolating converter topology, and the second converter cells 21-2 N3 are implemented with a non-isolating converter topology, as is the case in Fig. As shown in section 8, the first converter cells 11-1 ensure N1 for galvanic isolation between the input IN1, IN2 and the output OUT1, OUT2 of the power converter circuit.

[0040] At the in Fig. In the embodiment shown in Figure 9, the first converter cell is 1. i This is implemented with a non-isolating converter topology. This is indicated by the transformer symbol in the circuit block representing the second converter cell 2. i represented, schematically illustrated. The first converter cell 1 i is implemented with a non-isolating converter topology. In a power converter circuit, in which the first converter cells 11-1 N1 are implemented with a non-isolating converter topology, and the second converter cells 21-2 N3 are implemented with an isolating converter topology, as is the case in Fig. As shown in 9, the second converter cells 21-2 ensure N3for galvanic isolation between the input IN1, IN2 and the output OUT1, OUT2.

[0041] At the in Fig. The embodiment shown in 10 is not one of the first power converter circuits 1 i and the second power converter circuit 2 i implemented with an isolating converter topology. According to a further embodiment (not shown), both the first power converter circuit 1 i , as well as the second power converter circuit 2 i implemented with an isolating converter topology.

[0042] The following describes various embodiments of the first power converter 10 and the operating modes of these embodiments. A first multi-cell power converter 10 with converter cells 11-1 connected in series is described below. N1referred to as IS (Input Serial) converters or power converters with an IS topology. Accordingly, a first multi-cell power converter 10 with parallel-connected converter cells 11-1 N1 referred to as an IP (Input Parallel) converter or power converter with an IP topology. A second multi-cell power converter with converter cells 21-2 connected in series. N3 is referred to as an OS (Output Serial) converter or power converter with an OS topology. Accordingly, a second multi-cell power converter 20 with parallel-connected converter cells 21-2 is defined. N3referred to as op-amp (output parallel) converters or power converters with an op-amp topology. In the context of one of the first and second power converters 10, 20, “series-connected converter cells” are converter cells in which either their cell inputs are connected in series (in the first converter 10) or their cell outputs are connected in series (in the second converter 20), and “parallel-connected converter cells” are converter cells in which either their cell inputs are connected in parallel (in the first converter 10) or their cell outputs are connected in parallel (in the second converter 20).

[0043] First, an embodiment of a first power converter 10 with an IS topology is explained, which is designed to act as an input voltage V IN a rectified sinusoidal voltage, as in Fig. 2A is shown, to obtain and several intermediate circuit voltages V21-V2 N1at the individual intermediate circuit capacitors 111-11 N2 (where in this embodiment N1=N2) to be made available. Referring to Fig. 11, such an input voltage V IN with a rectified sinusoidal signal waveform from a sinusoidal mains voltage V GRID by a bridge rectifier 100 with four rectifier elements 101-104. These rectifier elements can be diodes, as in Fig. Figure 11 shows the rectifier elements. However, other rectifier elements, such as switches operated as synchronous rectifier elements, can also be used. These rectifier elements 101-104 are connected in a bridge configuration and receive the mains voltage V. GRID The rectifier circuit 100 takes an input voltage and delivers the rectified sine wave as an output voltage. This output voltage is the input voltage V. INthe power converter circuit, from which in Fig. 11 only shows the inputs IN1 and IN2.

[0044] The mains voltage V GRID Can a sinusoidal voltage of 110V be used? EFF or 230V EFF In the first case, a peak voltage of the rectified input voltage V is present. IN In one case, the peak voltage is approximately 160V, and in the second case, it is approximately 320V. According to another embodiment, the mains voltage is a medium voltage with a peak voltage of up to several kilovolts (kV).

[0045] According to one embodiment, the first power converter 10 is connected to the several first converter cells 11-1 N1 trained to measure the intermediate circuit voltages V21-V2 N2 from the input voltage V IN to generate such a voltage level that a total intermediate circuit voltage V2 TOT is higher than the voltage level of the peak voltage of the input voltage V INThe total DC link voltage V2 TOT corresponds to the sum of the individual intermediate circuit voltages V21-V2 N2 , That means: V2TOT=∑i=1N2V2i

[0046] According to one embodiment, the total intermediate circuit voltage V2 TOT between 1.1 and 1.3 times the peak voltage. In the case of a 220V supply EFF Sine wave voltage obtained input voltage V IN is the total intermediate circuit voltage V2 TOT for example, about 400V.

[0047] Fig. Figure 12 shows an embodiment of a first power converter 10 which has an IS topology and is configured to measure the total DC link voltage V2 TOT with a higher voltage level than the peak voltage level of the input voltage V IN to generate. In this embodiment, the individual first converter stages are 11-1 N1Each is implemented with a boost converter topology, which is a type of non-isolating converter topology. In Fig. 12 is just one of the first converter cells 11-I N1 , namely the first converter cell 11, shown in detail. The other first converter cells 12-1 N1 are implemented with the same topology. The explanation given in connection with the first converter cell 11 therefore applies accordingly to the other first converter cells 12-1. N1 .

[0048] Referring to Fig. The first converter cells comprise a half-bridge with a low-side switch. L and a high-side switch 12 H The high-side switch 12 H is optional and can be replaced by a rectifier element, such as a diode. Referring to Fig. 12. The high-side switch can be implemented with an electronic switch and a parallel rectifier element. The electronic switch is operated as a synchronous rectifier, which switches on whenever the parallel rectifier element is conducting. Thus, the high-side switch 12 functions H like an active rectifier element. However, losses occur in the high-side switch 12. H The losses that occur when the switch is on are lower than those that occur in a comparable passive rectifier element, such as a diode. The low-side switch 12 L It can also be implemented with an electronic switch and a parallel rectifier element. However, the rectifier element is optional in this case. The high-side switch 12 H and the low-side switch 12 Lcan be implemented as electronic switches. Examples of these switches include, but are not limited to: MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Field-Effect Transistors), Bipolar Junction Transistors (BJTs), HEMTs (High Electron Mobility Transistors), GaN HEMTs, or similar devices. Some types of these electronic switches, such as MOSFETs, incorporate an integrated diode (body diode), which is known as the... Fig. The rectifier element shown in section 12 can be used.

[0049] Referring to Fig. 12 is the low-side switch 12 L connected between the cell input nodes of the first converter cell 11. This forms the low-side switch 12. L the first converter cell 11 and the corresponding low-side switches (not shown) in the other first converter cells 12-1 N1A series circuit connected between the input nodes of inputs IN1 and IN2. The high-side switch 12 H and the intermediate circuit capacitor 111 of the first converter cell 11 form a series circuit, this series circuit being connected in parallel to the low-side switch 12 L is switched on.

[0050] The first power converter circuit 10 also includes at least one coil 15, such as a choke. In the case of the Fig. In the embodiment shown in 12, the individual first converter cells 11-I share N coil 15. That is, there is a coil that is in series with the low-side switch 12. L in the first converter cell 11 and the corresponding low-side switches in the other converter cells 11-1 N1 is switched. According to a further embodiment (not shown), each converter cell comprises 11-1 N1a coil that is connected between a cell input node and the circuit nodes common to the high-side switch and the low-side switch in the respective converter cell.

[0051] Referring to Fig. 12 The first converter cell 11 also includes a controller 14, which is designed to control the operation of the low-side switch 12 L and to control the high-side switch. If the high-side switch is 12 H When replaced by a passive rectifier element, the controller 14 only controls the operation of the low-side switch 12. L .

[0052] The low-side switch 12 L receives a control signal S12 L from the controller 14, wherein the control signal S12 L the low-side switch 12 L either turns it on or off. Accordingly, the high-side switch receives 12 H a control signal S12 H from the controller 14, wherein the control signal S12H the high-side switch 12 H either switches it on or off. According to one embodiment, the controller 14 controls the low-side switch 12. L and the high-side switch 12 H such that they are not switched on at the same time, in order to prevent the intermediate circuit capacitor 111 from being switched on via these switches 12 L , 12 H is unloaded.

[0053] According to one embodiment, the controller 14 is located in the first converter cell 11 and the corresponding controllers are located in the other converter cells 12-1. N1 The first power converter 10 is controlled by a controller 4. This controller 4 is hereinafter also referred to as the main controller of the first power converter 10. Operating modes of this main controller 4 and possible implementations are explained below.

[0054] According to one embodiment, the main controller is designed to measure the total intermediate circuit voltage V2. TOT via the controller 14 in the first converter cell 11 and the corresponding controllers in the other converter cells 12-1 N1 to control (regulate). According to one embodiment, the main controller 4 is further configured to monitor the current signal waveform of the input current I. IN to regulate in such a way that the signal waveform of the input current I IN essentially the signal waveform of the input voltage V IN This corresponds to a phase difference between the signal waveform of the input voltage V. IN and the resulting signal waveform of the input current I IN can be zero, or different from zero. Controlling the input current I IN so that it has the same signal waveform as the input voltage V INpossessing this can help determine the power factor of the input power P received at inputs IN1 and IN2. IN to regulate. A first power converter 10, which is designed to regulate the signal waveform of the input current I IN to regulate it so that it is essentially equal to the signal waveform of the input voltage V IN is referred to as the first power converter 10 with a PFC (Power Factor Correction) functionality or, in short, as the first PFC power converter 10.

[0055] An embodiment of a main controller 4 configured to control the total intermediate circuit voltage V2 TOT and the current signal waveform of the input current I IN to regulate is in Fig. 13 shown. Referring to Fig. The main controller 4 comprises an input reference current controller 41 and a converter cell controller 42, which is also referred to as a modulation index controller. The input reference current controller 41 is configured to generate an input current reference signal I IN_REF to generate the input current reference signal I IN_REF represents the desired current level (setpoint) of the input current I IN , which is needed to determine the total intermediate circuit voltage V2 TOT to regulate in such a way that a voltage level of the total intermediate circuit voltage V2 TOT corresponds to a predefined voltage level. A level of this input current reference signal I IN_REF can vary over time if the input voltage V IN varies. The input reference current controller 41 receives an input voltage signal V. IN M , which is the instantaneous voltage level of the input voltage V IN This input voltage signal V represents... IN_Mcan be determined by measuring the input voltage V IN or obtained in some other way. The input reference current controller 41 also receives intermediate circuit voltage signals V2. 1_M -V2 N2_M Each of these intermediate circuit voltage signals V2 1_M -V2 N2_M represents one of the intermediate circuit voltages V21-V2 N2 These intermediate circuit voltage signals V2 1_M -V2 N2_M can be obtained by measuring the individual intermediate circuit voltages V21-V2 N2 The input reference current controller 41 receives a total DC link voltage reference signal V2. TOT_REF This reference signal V2 TOT_REF represents the desired (predefined) voltage level of the total DC link voltage V2 TOT The input reference current controller 41 calculates the input current reference signal I. IN_REFbased on these input signals. Since the input reference current controller 41 determines the current level of the input current reference signal I IN_REF generated in such a way that the total DC link voltage exceeds the DC link voltage reference signal V2 TOT_REF When the input reference current controller 41 assumes the defined desired level, it can also be referred to as an intermediate circuit voltage controller in the present example, as well as in other embodiments explained below.

[0056] The modulation index controller 42 receives the input current reference signal I IN_REF and an input current signal I IN_M The input current signal I IN_M represents the instantaneous current level of the input current I IN This input current signal I IN_M can be obtained by measuring the input current I INor in some other way. The modulation index controller 42 outputs a control signal m, which is processed by the controller 141-I4. N1 in the individual first converter cells 11-1 N1 will be received. Referring to Fig. 12 Each of the controllers (more precisely, the controller in each of the converter cells) receives a control signal m1-m N1 from the main controller 4. According to one embodiment, the individual first converter cells 11-1 are provided N1 the same control signal m, such that m=m1=m2=m3=m N1 Details of this control signal m, which is also referred to below as the modulation index m, are explained below. Before discussing the modulation index m in more detail, exemplary embodiments of the input reference current controller 41 and the converter cell controller 42 are described using the following examples: Fig. 14 explained. The modulation index controller 42 serves to control the input current I INto regulate. Therefore, the modulation index controller 42 can also be referred to as an (input) current controller.

[0057] In connection with Fig. 14 The input reference current controller 41 is referred to simply as the current controller. Referring to Fig. 14, the current controller 41 can contain an error filter 411 that filters the intermediate circuit voltage signals V2 1_M -V2 N2_M and the total DC link voltage reference signal V2 TOT _REF The error filter 411 generates an error signal V2. ERR , which depends on a difference between the total DC link voltage reference signal V2 TOT_REF and the sum of the individual intermediate circuit voltage signals V2 1_M -V2 N2_M The sum of these intermediate circuit voltage signals V2 1_M -V 2N2_M represents the total intermediate circuit voltage V2 TOT The error filter can detect the difference. V2_TOT−∑i=1N2V2i_M calculate and filter this difference to find the error signal V2 ERR to generate. The filter can have one of the following behaviors: proportional (P), proportional-integral (PI), or proportional-integral-differential (PID). A multiplier 412 receives the error signal V2. ERR and the total intermediate circuit voltage signal V2 TOT_REF and delivers the product of these signals V2 ERR , V2 TOT_REF as an output signal A. An optional divider 413 receives the multiplier output signal A and a signal B, where signal B depends on the square of the peak voltage level V. IN_MAX the input voltage V IN . In the Fig. The following applies to the exemplary embodiment shown in 14: B=vIN_MAX22

[0058] An output signal C of the divider 413 equals the quotient A / B of the divider input signals A and B. A further multiplier 414 receives the divider output signal C and the input voltage signal V. IN_M and is designed to measure the instantaneous levels of these signals C and V IN_M to multiply. The further multiplier 414 provides the input current reference signal I. IN_REF as an output signal.

[0059] As demonstrated by Fig. 13 explains, defines the input current reference signal I IN_REF the desired current level of the input current I IN If the input voltage V IN The input current reference signal I varies over time and therefore also varies. IN_REF temporally. This is a result of generating the input current reference signal I. IN_REF by multiplying the input voltage signal V IN_Mwith the output signal C of the divider 413. The divider 413 can be omitted. In this case, the further multiplier 414 receives the output signal A from the multiplier 412 as an input signal. Assuming that the input current reference signal I IN_REF a periodic signal with a value determined by the input voltage signal V IN_M The defined frequency is an amplitude of the input current reference signal I. IN_REF defined by an amplitude of the input voltage signal V IN_M and by one of the divider output signal C and the multiplier output signal A. These signals C and A depend on the total DC link voltage V2. TOT The fault filter 411 is designed to filter out the fault signal V2. ERR to generate such a signal level of the error signal V2 ERR increases when the total intermediate circuit voltage V2 TOT among those determined by the total intermediate circuit voltage reference signal V2TOT_REF defined level falls in order to determine the level of the multiplier output signal A and the amplitude of the input current reference signal I IN_REF to increase the total intermediate circuit voltage V2 TOT to regulate so that a voltage level of the total intermediate circuit voltage V2 TOT essentially the one provided by the overall DC link voltage reference signal V2 TOT_REF The defined level corresponds to this. Accordingly, the error filter 411 reduces the level of the error signal V2. ERR , if the voltage level of the total intermediate circuit voltage V2 TOT the total intermediate circuit voltage reference signal V2 TOT_REF exceeds the defined voltage level in order to determine the amplitude of the input current reference signal I IN_REF to reduce and prevent a further increase in the total DC link voltage V2 TOT to counteract this.

[0060] The optional divider 413 can be used in applications where the amplitude of the input voltage V IN The 413 divider operates on the feed-forward principle and helps to adjust the amplitude of the input current I. IN by reducing the amplitude of the input current reference signal I IN_REF to reduce when the amplitude of the input voltage V IN increases. In this way, the average input power, which is the average input power over one period of the input voltage V, is IN is essentially independent of the amplitude of the input voltage V IN and is essentially defined by the error signal V2 ERR and the total DC link voltage reference signal V2 TOT REF .

[0061] refer to Fig. 14 The modulation index controller 42 includes a first filter 422, which filters the input current signal I IN_MA subtractor 421 receives the input current reference signal I. IN_REF and the filter output signal 422. This subtractor 421 subtracts the instantaneous signal level of the filter output signal I. IN_F from the current level of the input current reference signal I IN_REF An output signal I IN_ERR The subtractor 421 represents a current fault. That is, the subtractor is outputting a signal I. IN_ERR This represents an instantaneous difference between the desired input current level and the actual input current level. A second filter 423 receives this current error signal I. IN_ERR and provides the modulation index m. According to one embodiment, the first filter 422 has a low-pass characteristic. The second filter 423 can have a P, PI, or PID characteristic.

[0062] It can be shown that the modulation index m is also a periodic signal, essentially with the same frequency as the input voltage V. IN is when the input voltage V IN a periodic voltage, such as a rectified sinusoidal voltage with a frequency of 100 Hz or 120 Hz. Fig. Figure 15 schematically illustrates the relationship between the input voltage V IN and the modulation index m. Since referring to Fig. 14 the input current reference signal I IN_REF by multiplying the input voltage signal V IN_M The signal obtained with one of the signals C or A, which depend on the total DC link voltage, represents the signal in Fig. 15 Signal waveform shown, which represents the input voltage V IN also represents the input current reference signal I IN_REF (assuming that the voltage level of the total DC link voltage V TOTduring the Fig. (15 illustrated duration does not change). Referring to Fig. 15. A phase shift Φ between the input voltage V can occur. IN or the input current reference signal I IN_REF On the one hand, there must be a phase difference Φ, which is at most a few degrees, and on the other hand, a phase difference m. This phase difference can be determined based on the difference between the input current reference signal I and the input current reference signal I. IN_REF and the filtered input current signal I IN_F and on the voltage V15 across coil 15 (compare Fig. 11) vary. Furthermore, it can be shown that the amplitude of the varying modulation index m depends on the amplitude of the input voltage V. IN , where the amplitude of the modulation index m increases when the amplitude of the input voltage V INincreases. According to one embodiment, the main controller 4 is configured to generate the modulation index m as a normalized signal with a value between 0 and 1, wherein the modulation index m has an amplitude of 1 only in cases where the amplitude of the input voltage V IN the total intermediate circuit voltage V TOT corresponds.

[0063] Fig. Figure 16 shows an embodiment of the controller 14 as shown in Fig. 12 converter cell 11 shown. Each of the controllers (in Fig. 12 not shown) in the other converter cells 12-1 N1 can according to the in Fig. The controller shown in section 16 is implemented as shown in section 14. Referring to Fig. 16 The controller 14 is configured to generate a duty cycle d1 based on the modulation index m1 received from the cell controller 42. In the Fig. In the embodiment shown in Figure 16, the calculation of the duty cycle comprises the calculation of the duty cycle d as follows: d1=1−m1

[0064] For the purpose of illustration, let us assume that each of the first converter cells 11-1 N1 contains the same modulation index m from the main controller, so that in the controller each of the first converter cells 11-1 N1 The same duty cycle d=1-m is calculated.

[0065] Like the modulation index m1, the duty cycle d1 can vary between 0 and 1. A PWM controller 142 receives the duty cycle, or more precisely, a signal representing the duty cycle d1, and generates the control signal S12. L for the low-side switch 12 L and, optionally, the control signal S12 H for the high-side switch 12 H based on the duty cycle d1.

[0066] A mode of operation of the in Fig. The PWM controller 142 shown in the 16 illustrations is based on Fig. 17 explains, in the timing diagrams of the low-side switch 12 L received control signal S12 L and the one through the high-side switch 12 H received control signal S12 H are shown. Each of these control signals S12 L , S12 H It can assume an "on" level, which turns the respective switch on, and an "off" level, which turns the respective switch off. This is only for illustrative purposes. Fig. 17. An on level is represented as a high signal level and an off level as a low signal level.

[0067] Referring to Fig. 17 The PWM controller 142 is designed to control the low-side switch 12 L to switch on cyclically. The PWM controller 142 can in particular be configured to switch the low-side switch 12. Lto switch on periodically. In Fig. 17 denotes Tp as the duration of a control cycle of the low-side switch 12. L The time period Tp is defined by a switching frequency fp, where Tp = 1 / fp. The switching frequency fp is, for example, a frequency selected from a frequency range between 18 kHz and several hundred kHz. Fig. 17 denotes tone, a one-time of the low-side switch 12. L , which is a time period within a control cycle in which the low-side switch 12 L is switched on. The duty cycle d1 defines the duration of this on-time relative to the duration Tp of a control cycle, where d1=tone / Tp

[0068] This means that the on-time increases relative to the duration Tp of a control cycle when the duty cycle d1 increases, and vice versa.

[0069] Referring to Fig. 17. The PWM controller 142 can control the high-side switch 12. Hcomplementary to switching the low-side switch on and off 12 L to switch on and off. That is, the PWM controller 142 can be configured to control the high-side switch 12. H to turn on when the low-side switch 12 L is switched off, and vice versa. Between switching off the low-side switch 12 L and the activation of the high-side switch 12 H and between switching off the high-side switch 12 H There may be a delay between the low-side switch being turned back on and the circuit being reset. However, such delays are not uncommon in Fig. 17 not shown. During such delay times, the rectifier element of the high-side switch 12 conducts H If the high-side switch is 12 H When replaced by a rectifier element, the rectifier element conducts "automatically" when the low-side switch 12 is closed. L is in the off state.

[0070] Fig. Figure 18 shows an embodiment of the PWM controller 142 in which in Fig. 16 controllers shown 14. Referring to Fig. 18. The PWM controller 142 can include a clock generator 143 that generates a first clock signal CLK1. The frequency of this first clock signal CLK1 can be higher than the switching frequency fp. According to one embodiment, the frequency of the first clock signal CLK1 is at least a few MHz. A frequency divider 144, which can be implemented with a counter or similar device, receives the first clock signal CLK1 and generates a second clock signal CLK2. The second clock signal CLK2 defines the switching frequency fp. This second clock signal CLK2 is in Fig. 17 also illustrated. Referring to Fig. 17 can be the control signal S12 L of the low-side switch 12 LEach time a signal pulse of the second clock signal CLK2 occurs, the input level is set to a high level. A latch, such as an RS flip-flop 145, can receive the second clock signal CLK2 at a set input S. An input of a first driver 146 is coupled to a non-inverting first output Q of the flip-flop 145 and generates the drive signal S12. L of the low-side switch 12 L based on the output signal at the first output Q of the flip-flop 145. An optional second driver 147 generates the control signal S12. H of the high-side switch 12 H based on an output signal at a second inverting output Q' of flip-flop 145. To determine the one-time tone of the low-side switch 12. LTo set the timer, Timer 148 receives the second clock signal CLK2, the duty cycle signal d, and the first clock signal CLK1. Timer 145 is configured to reset Flip-Flop 145 to cause the drive signal S12 to be set. L the off level is assumed for a predefined time period after a signal pulse of the second clock signal CLK2, where this time period is defined by the duty cycle d.

[0071] It should be mentioned that Fig. Figure 18 shows only one of several possible implementations of the PWM controller 142. Of course, the implementation of the PWM controller 142 is not limited to the specific application in Fig. The embodiment shown in 18 is limited.

[0072] It can be shown that the modulation index generated as explained above corresponds approximately to the following: m=VIN / V2TOT where V IN the current voltage level of the input voltage V IN and V2 TOTrepresents the (desired) total DC link voltage. However, this is only an approximation. Referring to what was said above in connection with the Fig. 13 and Fig. As implemented in section 14, the modulation index m is not only dependent on the input voltage V. IN , but can also be based on the difference between the current level of the input current I IN and the reference input current I IN_REF vary.

[0073] According to one embodiment, the controller 14 in the first converter cell 11 and the corresponding controllers in the other converter cells 12-1 are provided N1 the same modulation index m from the main controller 4, and the individual converter cells 11-1 N1 are operated in a time-shifted manner (interleaved). This is determined by the Fig. 19A and Fig. 19B explained. Fig. 19A and Fig. 19B shows timing diagrams of the control signal S12 Lof the low-side switch 12 L in the first converter cell 11 and timing diagrams of the control signals S12 L2 -S12 LN1 the corresponding low-side switches in the other converter cells 12-1 N1 . In the Fig. 19A and Fig. 19B these control signals S12 L -S12 LN1 The results are shown for two different duty cycles d, namely d=0.625 in Fig. 19A and d=0.125 in Fig. 19B. The time-shifted operation of the individual converter cells 11-1 N1 This means that the control cycles of the individual converter cells 11-1 N1 with a time offset Tp / N1. Here, as in the previously explained embodiments, N1 denotes the number of the first converter cells 11-1. N1 For example, if N1=4, the time offset is Tp / 4, as in the Fig. 19A and Fig. Figure 19B illustrates this. For example, there is a delay of Tp / 4 between the start of the on-time of the control signal S12. L in converter cell 11 and the beginning of the on-time of the control signal S12 L2 In converter cell 12, there is a delay time Tp / 4 between the start of the on-time of the control signal S12. L2 in converter cell 12 and the beginning of the on-time of the control signal S12 L3 in converter cell 13 there is a delay time Tp / 4 between the start of the on-time of the control signal S12 L3 in converter cell 13 and the beginning of the on-time of the control signal S12 LN1 in converter cell 11. The time-shifted operation of the individual converter cells 11-1 N1 This results in a total switching frequency of N1·fp. This higher total switching frequency can help to reduce ripple in the input current I. INto reduce the effects of the clocked operation of the first power converter 10 or, more precisely, of the clocked operation of the individual first converter cells 11-1 N1 may result.

[0074] Referring to Fig. 12 and the associated description can be a current level of the input current I IN The voltage can be set by modulating a voltage V15 across coil 15. The voltage level of this voltage V15 depends on the instantaneous value of the input voltage V. IN , the intermediate circuit voltages V21-V2 N2 and the operating states of the individual first converter cells 11-1 N1 For the purpose of explanation, let us assume that the individual intermediate circuit voltages V21-V2 N2 are essentially the same and that the number N2 of the intermediate circuit capacitors is equal to the number N1 of the first converter cells 11-I N1 is (N1=N2). In this case, each of the intermediate circuit voltages V21-V2 is N2 same as V2TOT / N1. Furthermore, it is assumed that each converter cell 11-1 N1 an on state, which is an operating state in which the respective low-side switch 12 L is switched on, and an off state in which the respective low-side switch 12 L is switched off, can be assumed. This represents in the Fig. 19A and Fig. The timing diagrams shown in 19B depict the on-times of the control signals 12 L -12 LN1 The low-side switch determines the on-times of the individual first converter cells.

[0075] Assuming that the electrical resistances of the individual low-side switches (of which in Fig. 12 only the low-side switch 12 L the first converter cell 11 is shown) in the first converter cells 11-1 N1 The cell input voltage V11-V1 can be neglected. N1 at the cell input of the individual converter cells 11-1 N1 Zero, if the converter cell is 11-1N1 is in the on state, and equals the intermediate circuit voltage (V2). TOT / N1) of the respective converter cell when the converter cell is in the off state. The coil voltage V15 is given by V15=VIN−V1TOT where V1 TOT represents the total voltage at the cell inputs of the individual first converter cells, that is V1TOT=∑i=1N1V1i

[0076] If each of the first converter cells 11-1 N1 The coil comprises (not shown) the cell input voltages V11-V1. N1 The voltages across the individual low-side switches. V15 is then the total voltage across the multiple coils.

[0077] Operating (controlling) the individual first converter cells 11-1 N1 based on the modulation index m, as previously demonstrated by the Fig. As explained in 13-19B, this causes the coil voltage V15 to be essentially between V IN -(k·V2 TOT / N1) and V IN-((k+1)·V2 TOT / N1) varies, where k depends on the modulation index m and is equal to the number of first converter cells that are in the off state at the same time. k can be obtained by k=Round[vIN⋅N1v2TOT]=Round[m⋅N1] where Round[.] is a mathematical function that rounds the result of the operation in the square brackets to the nearest integer, V IN the current level of the input voltage V IN is and m is the modulation index. For example, if the instantaneous level of the input voltage V IN below the level of an intermediate circuit voltage (V2) TOT / N1) is, then k=0, so that the total cell input voltage V1 TOT between 0 and V2 TOT / N1 varies until the input voltage V IN V2 TOT / N1 is reached. In this way, the total cell input voltage V1 "follows". TOT the instantaneous value of the input voltage V INIn other words: The converter cells 11-1 N1 generate (modulate) the total cell input voltage V1 TOT such that the total cell input voltage V1 TOT the input voltage V IN "follows". In this way, the voltage V15 across coil 15 can be regulated. This is shown below using the Fig. 12 and Fig. 19A explained.

[0078] At the in Fig. In the embodiment shown in 19A, the individual converter cells 11-1 N1 It is operated with a duty cycle of d=0.625. In this embodiment, the modulation index m is 0.375, which indicates that the instantaneous value of the input voltage V is IN compared to the (desired) total DC link voltage V2 TOTis relatively low. Referring to the equation above, k=1 when m=0.375 and when N1=4 converter cells are present (k=Round[0.375·4]=Round[1.5]=1), so that at n=0.375 the total cell input voltage V1 TOT between V2 TOT / N1 and 2·V2 TOT / N1 varies. That is, either one or two converter cells are in the off state at the same time, or either three or two converter cells are in the off state at the same time. If three first converter cells 11-1 N1 When in the on state, the total cell input voltage V1 TOT (N1-3)·V2 TOT / N1. That is, in this specific embodiment with N1=4, the total cell input voltage V1 TOT V2 TOT / N1. If two of the converter cells 11-1 N1 When operated in the on-state, the total cell input voltage V1 TOT (N1-2)·V2 TOT / N1. The coil voltage V15 is in these two cases V15=VIN−(N1−3)⋅V2TOT / N1 V15=VIN−(N1−2)⋅V2TOT / N1

[0079] A modulation index of m=0.375 indicates that the instantaneous value of the input voltage V IN essentially 0.375·V2 TOT corresponds, so that the coil voltage V15 is positive when three of the first converter cells 11-1 N1 are in the on state, and is negative when two of the first converter cells 11-1 N1 are in the on state. Therefore, in the first case, the coil current I IN to, while in the second case it decreases. During such time periods in which the total cell input voltage V1 TOT is less than the instantaneous value of the input voltage V IN , energy is stored inductively in the coil 15, and during such time periods in which the instantaneous voltage level of the input voltage V IN below the total cell input voltage V1 TOTThe energy stored in coil 15 is transferred to the intermediate circuit capacitors of such first converter cells 11-1 N1 transmitted, which are in the off state. Since each of the first converter cells 11-1 N1 The intermediate circuit capacitors 111-11 are switched on and off in a control cycle. N2 of the individual first converter cells 11-1 N1 charged immediately when the individual first converter cells 11-1 N1 Receive the same modulation index m from the main controller 4.

[0080] Referring to the in Fig. In the embodiment shown in Figure 19B, a duty cycle of d = 0.125 corresponds to a modulation index of m = 0.875. In this case, the instantaneous voltage level of the input voltage V is IN near the total DC link voltage V2 TOT At m=0.875 and N=4, k=3, so three or four converter cells are in the off state at the same time. The total cell input voltage V1 varies accordingly.TOT between (N1-1)·V2 TOT / N1, if three of the first converter cells 11-1 N1 are in the off state (only one is in the on state), and V2 TOT , if each of the first converter cells 11-1 N1 is in the off state (none is in the on state).

[0081] Fig. Figure 20 schematically illustrates one period of the input voltage V IN and the total cell input voltage V1 TOT during this one period of the input voltage V IN . That in Fig. The embodiment shown in 20 is based on the first power converter 10 with N1=4 first converter cells 11-1 N1 and N2=4 intermediate circuit capacitors 111-11 N2 As demonstrated by Fig. As can be seen in section 20, the total cell input voltage V1 switches TOT depending on the instantaneous voltage level of the input voltage V INbetween two voltage levels. The difference between these two voltage levels is essentially V2. TOT / N1. In Fig. 20 The dashed lines mark such instantaneous voltage levels of the input voltage V IN , where the two levels change, between which the total cell input voltage V1 TOT switches. The duty cycles d and the modulation indices m, which correspond to the instantaneous voltage level of the input voltage V marked by the dashed lines. IN are assigned to are in Fig. 20 is also shown. It should be mentioned that the in Fig. 20. Signal waveform of the total DC link voltage shown by operating the individual converter cells 11-1 N1 with the same (or essentially the same) modulation index m. Referring to the explanation below, it is also possible to use the individual converter cells 11-1 N1to operate with different modulation indices and obtain a signal waveform as described in Fig. 20 is shown.

[0082] Fig. Figure 21 shows an example of how the controller 14 is in the first converter cell 11 and corresponding controllers are in the other converter cells 11-1. N1 can be synchronized so that the controllers can synchronize the individual first converter cells 11-1 N1 as based on the Fig. 19A and Fig. Section 19B explains how to operate with a time delay. Fig. Reference numeral 21 designates the controller in the first converter cell 11, as shown in Fig. 12 is shown, and the reference numbers 142-14 N1 designate corresponding controllers in the other first converter cells 12-1 N1 . In the Fig. 19A and Fig. In the embodiments shown in 19B, the control cycles of the individual first converter cells 11-1 begin. N1in a predefined order. In this case, the individual controllers can be, as in Fig. 21 shown, are synchronized. In this embodiment, the controller 14 of the first converter cell 11 forwards the second clock signal CLK2 (which is used in the first converter cell 11 to define the start of the on-time) to the controller 142 of the first converter cell 12, which, referring to the Fig. 19A and Fig. 19B is next in line to begin its associated control cycle. Controller 142 forwards its second clock signal CLK22 (which is used in the first converter cell 12 to define the start of the on-time) to controller 143, which forwards its second clock signal CLK23 (which is used in the first converter cell 13 to define the start of the on-time) to controller 14. N1forwards. The second clock signals CLK2-CLK23 are transmitted from one controller to the other via isolation barriers 161-163, which may include transformers, optocouplers, or similar devices, and which connect the controllers 14-14 N1 galvanically isolate.

[0083] If the individual controllers 141-I4 N1 as in Fig. 21 shown, synchronized, the controller 14 of the first converter cell 11 can be synchronized as shown by the Fig. 16 and Fig. 18 explained, can be implemented. The PWM controller 142 in the other controllers 142-14 N1 can be like in Fig. 22 shown, to be realized. The one in Fig. The PWM controller 142 shown in section 22 is a modification of the one described in [reference missing]. Fig. 18 PWM controllers shown 142. The one in Fig. The PWM controller shown in section 22 differs from the one in Fig. 18 shown by the fact that instead of the frequency divider 144 there is another delay element 149 which provides the second clock signal CLK2 i-1 received from another controller and the second clock signal CLK2 i based on the received second clock signal CLK2 i-1 and the desired time offset (Tp / 4 in the Fig. 19A and Fig. 19B) between the control cycles of the individual converter cells 11-1 N1 generated. In Fig. 22 refers to CLK2 i-1 the second clock signal received by the respective controller. For example, if the in Fig. 22 PWM controllers shown in the PWM controller of the in Fig. If the controller shown in section 21 is 141, then CLK2 is... i-1 The clock signal CLK2 and CLK22 received from the controller 142 is the control signal used in the converter cell 12 to control the start and end of the on-time.

[0084] The previously explained time-shifted operation of the first converter cells 11-1 N1 , in which the individual converter cells are operated with the same duty cycle, is only one way to operate the first series-connected converter cells 11-1 N1 In this embodiment, each of the converter cells is operated with pulse-width modulation (PWM) (at the switching frequency fp) such that each converter cell is in the on state for a specific time period and in the off state for a specific time period in each control cycle. That is, the individual converter cells are operated in the same mode. According to another embodiment, only one of the first converter cells 11-1 is activated in a control cycle. N1One converter cell operates in pulse-width modulation (PWM) based on its modulation index, while the other first converter cells are either on or off for the entire duration of a control cycle. This means each converter cell operates in one of three different modes: PWM, on (on-mode), and off (off-mode). An on state for a converter cell during a control cycle corresponds to a duty cycle of 1 (and a modulation index of 0) for that cell, and an off state for a converter cell during a control cycle corresponds to a duty cycle of 0 (and a modulation index of 1) for that cell. Therefore, operating one converter cell in pulse-width modulation and the other cells in either the on or off state is equivalent to operating the individual converter cells at different duty cycles or modulation indices.In general, the modulation indices are m1-m. N1 of the individual converter cells 11-1 N1 chosen so that VIN=∑i=1N1mi⋅V2i=m⋅V2TOT where N1=N2, V IN the instantaneous level of the input voltage V IN is, m i The modulation index of a converter cell is V2. i the associated intermediate circuit voltage, m the overall modulation index of the power converter, and V2 TOT The voltage level of the total DC link voltage is... If the individual DC link voltages V21-V2 N2 essentially the same and the same V2 TOT If / N1 are the case, then the following applies: VIN=V2TOTN1⋅(∑i=1N1mi)=m⋅V2TOT and (∑i=1N1mi)=N1⋅m

[0085] The operation of the individual converter cells at different modulation indices is demonstrated using: Fig. 23 explained. Fig. Figure 23 shows timing diagrams of the control signals S12 L -S12 LN1the low-side switch in the individual first converter cells, wherein the signal levels of the control signals S12 L -S12 LN1 as explained above, the operating status of the individual first converter cells 11-1 N1 represent.

[0086] For the purpose of illustration, let us assume that m = 0.625 and N1 = 4. Since 4 × 0.625 = 2.5 = 1 + 1 + 0 + 0.5, a total modulation index of m = 0.625 for the power converter 10 can be obtained by operating two converter cells at a modulation index of 1 (at a duty cycle of 0), one converter cell at a modulation index of 0 (at a duty cycle of 1), and one converter cell at a modulation index of 0.5 (at a duty cycle of 0.5). This is in Fig. 23 illustrated. In one in Fig. In the first control cycle shown in 23, m1=0.5, m2=m3=1 and m N1=0, meaning the converter cell is operated with pulse width modulation at a duty cycle of d1=0.5 (=1-m1=1-0.5), converter cells 12 and 13 are in the off state and converter cell 1 N1 is in the on state. In a subsequent control cycle, the modulation indices 1, 1, 0, and 0.5 can be assigned to the converter cells in a different way (as in Fig. 23). However, it is also possible to operate each of the converter cells with the same modulation index for several drive cycles.

[0087] The total duty cycle of the first power converter 10, such as the duty cycle d=0.375 in Fig. 23 denotes the average duty cycle of each of the first converter cells, that is d=∑i=1N1diN1 where d i the respective duty cycle of each first converter cell. In the Fig. 19A and Fig. In the embodiments shown in 19B, the individual converter cells have the same duty cycle and the same modulation index, which is the total duty cycle and the total modulation index, respectively.

[0088] Fig. Figure 24 shows an embodiment of a converter cell 1 i , which are in a multi-cell converter with IS topology of the in Fig. The type shown in 12 can be used if the multi-cell converter receives a sinusoidal voltage as the input voltage V. IN receives. That is, each of the in Fig. The 12 converter cells shown can be replaced by a converter cell of the type shown in Fig. 24 of the types shown will be replaced. Fig. 24 designates V1 I the cell input voltage, V2 i denotes the intermediate circuit voltage of the associated intermediate circuit capacitor 11 i , i1 i denotes the cell output current (which is the current in the circuit nodes to which the intermediate circuit capacitor 11 is connected).i is connected).

[0089] Referring to Fig. The converter cell 1 comprises 24. i a bridge circuit with two half-bridges 17, 18. Each half-bridge 17, 18 includes a high-side switch 17. H , 18 H and a low-side switch 17 L , 18 L Load sections of the high-side switch 17 H , 18 H and the low-side switch 17 L , 18 L Each half-bridge 17, 18 is connected in series, with the series connections each being in parallel to the intermediate circuit capacitor 11. I are switched. Each half-bridge 17, 18 includes a tap, which is a circuit node that connects to the load paths of the high-side switch 17. H , 18 H or the low-side switch 17 L , 18 L common to the respective half-bridge 17, 18. A first cell input node of the first converter cell 1 iis connected to the tap of the first half-bridge 17 and a second cell input node of the first converter cell 1 i is connected to the tap of the second half-bridge 18. The in Fig. The topology shown in Figure 24 is subsequently referred to as the full bridge topology.

[0090] A first converter 10 with an IS topology and implemented with the first converter cells of the in Fig. The type shown in section 24 can directly process a sinusoidal voltage supplied by a power grid, so that a rectifier circuit 100 (see Fig. 11), which can cause losses, is not required. The converter cell 1 i The full bridge topology can be operated in various ways. Two of these operating modes are shown below. Fig. 25A and Fig. 25B explained. In this Fig. 25A and Fig. 25B are timing diagrams of the input voltage V INduring one period of the input voltage V IN and from control signals S17 H -S18 L the high-side and low-side switches 17 H -18 L schematically illustrated.

[0091] Referring to Fig. The converter cell 1 operates at 25A. i during the positive half-wave and the negative half-wave of the sinusoidal input voltage V IN different. However, within each half-wave, the operation of converter cell 1 is... i very similar to the operation of one of the in Fig. 12 converter cells shown 11-1 N1, each comprising an electronic switch and a rectifier element. During each half-cycle, the two switches of one of the two half-bridges 17, 18 are pulse-width modulated, while the two switches of the other of the two half-bridges remain in a predefined operating state for the duration of the half-cycle. That is, the two switches of one half-bridge are switched at the switching frequency fp explained above, while the two switches of the other half-bridge are switched only once (at the beginning) in a half-cycle. During the positive half-cycle of the input voltage V IN Is the high-side switch 18 H the second half-bridge 18 in the off state and the low-side switch 18 L is in the on state. During this positive half-wave, the low-side switch 17 operates. L the first half-bridge 17 in a PWM operation, as the switching element 12 in the Fig. 12 converters 11 shown, and the high-side switch 17 H the first half-bridge 17 works like the one in Fig. 12 High-side switches (rectifier element) shown 13. That is, the high-side switch 17 H It also works using pulse-width modulation, but in a complementary way to the low-side switch 17. L During the negative half-cycle of the input voltage V IN Is the high-side switch 17 H the first half-bridge 17 in the off state and the low-side switch 17 L The first half-bridge 17 is in the ON state. The low-side switch 18 L the second half-bridge 18 is, like the switching element 12 of the in Fig. The converter 11 shown in the illustration is operated with pulse-width modulation. The high-side switch 18 H works like the one in Fig. 12 High-side switches 13 are shown. This means that the high-side switch operates in pulse-width modulation complementary to the low-side switch. By operating the switches of a half-bridge complementarily in PWM mode, the two switches are not turned on at the same time. In this embodiment, the two high-side switches 17 H , 18 H can be replaced by rectifier elements, such as diodes.

[0092] At the in Fig. In the embodiment shown in Figure 25, the first half-bridge 17 operates in pulse-width modulation during one half-wave (the positive half-wave in this embodiment), and the second half-bridge 18 operates in pulse-width modulation during the other half-wave (the negative half-wave in this embodiment). In another embodiment, based on Fig. In the operating mode described in 25B, only one of the two half-bridges 17, 18 operates in pulse-width modulation, while the other half-bridge operates at the frequency of the input voltage V. IN The circuit operates such that the other half-bridge switches only once in each half-cycle. This operating mode is subsequently referred to as totem-pole modulation. Totem-pole modulation allows the PWM-operated half-bridge to be optimized with respect to switching losses, and the other half-bridge to be optimized with respect to conduction losses. For illustrative purposes only, let us assume that the first half-bridge 17 operates in PWM mode, with a switching frequency of 18 kHz or higher, and that the second half-bridge 8 operates at twice the frequency of the input voltage V. IN works.

[0093] Referring to Fig. 25B, converter cell 1 operates i during the positive half-wave as above based on Fig. 25A explained. That means the low-side switch 17 L It operates using pulse-width modulation based on the modulation index m. i or the duty cycle d i (=1-ni) of converter cell 1 i , and the high-side switch 17 H It switches in a complementary manner. The high-side switch 18 H The second half-bridge 18 is off and the associated low-side switch 18L is on. During the negative half-wave, the control patterns of the individual switches are "inverted" compared to the positive half-wave. That is, the high-side switch 17 H It operates using pulse-width modulation based on the modulation index m. i or the duty cycle d i converter cell 1 i , and the low-side switch 17 L It switches in a complementary manner. The high-side switch 18 H The second half-bridge 18 is on and the associated low-side switch 18 L It's over.

[0094] Referring to Fig. 24 A controller 19 controls the operation of the half-bridges 17, 18. This controller 19 generates the control signals S17 H , S17 L , S18 H , S18 L for the individual high-side and low-side switches 17 H -18 L As explained above, based on Fig. 12 explained controller 14 the controller controls 19 the individual switches 17 H -18 L based on the modulation index m received from the main controller 4 i The main controller 14 can be identified as before using the Fig. 13 and Fig. 14 explains how to implement it. If the input voltage V IN an alternating voltage, such as one in Fig. The sinusoidal voltage shown in 23 is the modulation index signal m or m. i , which is generated by the main controller, is a variable signal that can vary between -1 and +1.

[0095] The Fig. 26A and Fig. Figure 26B shows two embodiments of a controller 19 configured to control the half-bridges 17, 18 in the Fig. 24 converter cell 1 shown i to be controlled based on the modulation index m. Fig. Figure 26A shows an embodiment of a controller configured to control the two half-bridges according to the diagram in Fig. to control the modulation scheme shown in 25A and Fig. Figure 26B shows an embodiment of a controller configured to control the two half-bridges 17, 18 according to the diagram in Fig. Modulation scheme shown in 25B.

[0096] Referring to Fig. 26A, the controller 19 includes a first PWM controller 191, which receives a first duty-cycle signal d17 and the high-side switch 17. H and the low-side switch 17 LThe first half-bridge 17 is controlled based on this duty cycle d17. The controller 19 also includes a second PWM controller 192, which receives a second duty cycle signal d18 and is configured to control the high-side switch 18. H and the low-side switch 18 L to control the second half-bridge 18 based on the second duty cycle d18. The controller 19 is configured to generate the first and second duty cycles d17, d18 as follows: d17=1−mi,if mi>0 d17=1,if mi≤0 d18=1+mi,if mi<0 d18=1,if mi≥0

[0097] This means that during the positive half-wave of the input voltage V IN and the positive half-wave of the modulation index (which is essentially in phase with the input voltage V) IN (is) the low-side switch 18 L one (d18=1), the high-side switch 18 H The low-side switch 17 is off. LThe first half-bridge 17 is switched on and off, with the duty cycle d17 being determined by the modulation index m. i is defined, and the high-side switch 17 H becomes complementary to the low-side switch 17 L switched on and off. During the negative half-wave, the low-side switch 17 is... L the first half-bridge 17 (d17=1), the high-side switch 17 H The low-side switch 18 is off. L The second half-bridge is equipped with the modulation index m. i The defined duty cycle d18 is switched on and off, and the high-side switch 18H is switched on and off in a complementary manner to the low-side switch 18L.

[0098] The first duty cycle d17 can be generated by multiplying the modulation index m i-1 by a first multiplier 193, adding +1 to the result by an adder following the first multiplier 193, and limiting the output signal of the adder 194 to a range between 0 and +1 by a limiter 195. The first duty cycle d17 is available at the output of the limiter 195. The second duty cycle d18 can be generated by adding one to the modulation index m. i by a second adder 196, and limiting an output signal of the second adder 196 to a signal range between 0 and 1 by a second limiter 197. The second duty cycle d18 is available at the output of the second limiter 197.

[0099] The in Fig. 26 The controller 19 shown is designed to generate the first and second duty cycles d17, d18 as follows: d17=1−mi,if mi>0 d17=−mi,if mi≤0 d18=0,if mi<0 d18=1,if mi≥0

[0100] This means that during the positive half-wave of the input voltage V IN and the positive half-wave of the modulation index (which is essentially in phase with the input voltage V) IN (is) the low-side switch 18 L one (d18=1), the high-side switch 18 H The low-side switch 17 is off. L The first half-bridge 17 is switched on and off, with the duty cycle d17 being defined by the modulation index m, and the high-side switch 17 H becomes complementary to the low-side switch 17 L switched on and off. During the negative half-wave, the low-side switch 18 is... L off (d18=0), the high-side switch 18 H is one of the high-side switches 17 H The first half-bridge 17 is switched on and off with the duty cycle d17 defined by the modulation index mi, and the low-side switch 17 L becomes complementary to the high-side switch 17 Hswitched on and off.

[0101] The second duty cycle d18 can be generated by simply detecting the polarity of the modulation index m. i using a threshold detector 198 that compares the modulation index to 0. The second duty cycle d18 available at the output of the threshold detector 198 is 1 when the duty cycle m i above 0, and is 0 when the modulation index m i is below 0. The first duty cycle can be obtained by subtracting the modulation index m. i from the output signal of the first threshold detector, that is, from the second duty cycle, using a subtractor. That is, d17=1-d18 in this embodiment. Each of the Fig. 26A and Fig. The first and second PWM controllers 191, 192 shown in 26B can be used as before based on the Fig. 18 and Fig. The PWM controller 142, as explained in section 22, can be implemented. In the case of the PWM controller 191, this corresponds to the one described in Fig. The 18 depicted duty cycle d1 corresponds to the first duty cycle d17, which is in Fig. 18 Control signal S12 shown L corresponds to the control signal S17 L of the low-side switch, and the control signal S12 H corresponds to the control signal S17 H of the high-side switch. Accordingly, in the case of the second PWM controller, 192 corresponds to the one in Fig. The duty cycle d1 shown in section 18 corresponds to the second duty cycle d18, the control signal S12. L corresponds to the control signal S18 L of the low-side switch, and the control signal S12 H corresponds to the control signal S18 H of the high-side switch.

[0102] Referring to the preceding explanation, a first power converter 10, which receives an input AC voltage, operates and the first converter cells 11-1 N1 based on the Fig. 24-26 of the type explained includes, during the positive half-wave of the input voltage V IN like the one in Fig. 12 shown first power converter 10, and operates during the negative half-wave of the input voltage V IN Similarly, during the negative half-wave, the first converter cells actuate the intermediate circuit capacitors, such as the one in Fig. 24 intermediate circuit capacitor 11 i connect to the cell input in such a way that the cell input voltage, such as that in Fig. The voltage V1 shown in section 24 is negative.

[0103] One operating mode of the first power converter 10 during one period of the input voltage V IN is in Fig. 27 illustrates this. During the positive half-wave, operation is as shown in the Fig. 20 explained. During the negative half-cycle of the input voltage V INThe total cell input voltage V1 varies TOT between negative voltage levels, where a difference between two of these voltage levels is equal to V2 TOT / N2 is. During the negative half-wave, the input current reference signal I IN_REF and, accordingly, the input current I IN negative. The intermediate circuit voltages V21-V2 N2 However, they are positive. The individual converter cells 11-1 N1 can operate in the same mode as based on the Fig. 19A, Fig. 19B explained or in other ways, such as by means of Fig. 23 explained, work.

[0104] A first power converter 10 with an IS topology is not limited to providing a rectified sinusoidal voltage or a sinusoidal voltage as the input voltage V. IN to obtain. The power converter 10 could also be used with a DC voltage as the input voltage V. INto be operated. In this case, the first power converter generates several intermediate circuit voltages V21-V2. N2 , each of which can have a voltage level that is lower than a voltage level of the input voltage V IN Nevertheless, the level of the total intermediate circuit voltage V2 can TOT be higher than the voltage level of the input voltage. The signal waveform of a DC voltage as input voltage V IN is schematically in Fig. 2C illustrates this. A multi-cell converter, which is connected to Fig. 12 converter cells shown 11-1 N1 Once realized, a positive voltage can be used as the input voltage V. IN received, and a multi-cell converter that is integrated into Fig. The converter cells shown in the diagram can receive either a positive voltage or a negative voltage as the input voltage.

[0105] If the first power converter 10 only accepts a DC voltage as input voltage VIN When operated, the main controller 4 can be used as described in Fig. 28 can be simplified. The one in Fig. 28 main controllers shown 4 are based on the ones in Fig. The main controller shown in 14 differs from the one in Fig. The main controller shown in section 14 is modified by omitting the additional multiplier 414. The input current reference signal I IN_REF corresponds to the output signal A of the multiplier 412 or the output signal C of the optional divider 413. In this embodiment, the input signal B of the optional divider V IN_MAX , which determines the voltage level of the input voltage V IN designated.

[0106] Fig. Figure 29 shows an embodiment of a multi-cell converter 10, in which the cell inputs of the individual converter cells 11-1 N1The inputs IN1 and IN2 of the multi-cell converter are connected in parallel. This means that the first cell input node of each converter cell 11-1 N1 is connected to the first input node IN1, and a second cell input node of each converter cell 11-1 N1 is connected to the second input node IN2, so that each of the converter cells 11-1 N1 the input voltage V IN receives. The in Fig. The topology of the multi-cell converter shown in Figure 29 is subsequently referred to as the IP (Input Parallel) topology.

[0107] At the in Fig. In the embodiment shown in Figure 29, the converter cells are 11-1. N1 implemented with a full-bridge topology, with only converter cell 11 shown in detail. However, a boost converter topology, as described in Fig. The figure shown in 12 can also be used. Fig. The multi-cell converter shown in Figure 29 with the IP topology differs from the one in Figure 29. Fig. The multi-cell converters shown in section 12 with the IS topology are characterized by the fact that in the Fig. 29 converters shown, each of the multiple converter cells 11-1 N1 a coil. As shown in cell 11, the coil 151 is connected in each cell between a cell input node, such as the first cell input node, and the bridge circuit with the two half-bridges 17, 18. Cell input voltages V11-V1 N1 These converter cells are the voltages between the taps of the half-bridges. This is consistent with the one in Fig. 24 converter cell 1 shown i .

[0108] At the in Fig. 29 multi-cell power converters 10 with IP topology are each first converter cell 11-1 N1 trained to determine their intermediate circuit voltage V21-V2 N1to control (regulate). For this purpose, each of these converter cells comprises 11-1 N1 a controller, whereby in Fig. 29 only shows the controller 41 of the converter cell 11. Each of these controllers can be configured according to the one described in the Fig. 13 and Fig. The main controller 4 shown in Figure 14 is implemented, with the difference that the controllers are located in the individual converter cells 11-1 N1 not receiving signals that represent each of the intermediate circuit voltages V21-V2 N2 not to represent, but only a signal representing the intermediate circuit voltage of the respective converter cell, and a signal representing the desired level of the converter cell. An embodiment of the controller 41 in the converter cell 11 is shown in Fig. Figure 30 is shown. The controllers in the other converter cells can be implemented accordingly.

[0109] The in Fig. 30 controllers shown, 41 are based on the one in Fig. The main controller shown in section 14 is 4 and differs from the one in Fig. The main controller shown in Figure 14 is distinguished by the fact that it outputs the modulation index m1 only for one converter cell 11. Furthermore, this modulation index m1 is based on the intermediate circuit voltage signal V2. 1_M the respective converter cell, the intermediate circuit voltage reference signal V2 1_REF the respective converter cell and optionally the current voltage level of the input voltage V IN calculated. In the Fig. 30 controllers shown 41 have the components of the in Fig. The controllers shown in section 14 and the corresponding components have the same reference symbols, to which a subscript "1" has been added. Regarding the operation of controller 41, reference is made to the description of the Fig. 14 Referenced. The one in Fig. The multiplier 4141 shown in the diagram can be omitted if the input voltage V INThe input signal B of the multi-cell converter 10 is a DC voltage. In this case, the input signal B of the divider corresponds to VIN MAX.

[0110] As shown by the in Fig. As can be seen in the converter cell 11 shown in 29, the switch controller (19 in cell 11) receives each converter cell 11-1 N1 the modulation index (n1 in cell 11) from the associated controller (41 in cell 11) and controls the switches (17 H -18 L in cell 11) in the converter cell based on the modulation index m1. The individual main controllers 41 can be located in the converter cells 11-1. N1 can be realized. In the case of a digital implementation of the main controller 41 and the switch controller 19 of a converter cell 11, the main controller 41 and the switch 19 can be implemented in a signal processor.

[0111] Fig. Figure 31 shows an embodiment of the second converter stage 20 with an OP topology, that is, a topology in which the cell outputs of the individual converter cells 21-2 N3 Outputs OUT1 and OUT2 are connected in parallel. Fig. 31 is only one converter cell, namely converter cell 21 shown in detail. The other converter cells 22-2 N3 can be implemented accordingly.

[0112] Converter cell 11 is implemented with a flyback converter topology. That is, converter cell 21 comprises a series connection with an electronic switch 202 and a primary winding 201. P a transformer 201, wherein this series circuit is connected in parallel to the intermediate circuit capacitor 111 to obtain the intermediate circuit voltage V21. A secondary winding 201s is inductively connected to the primary winding 201. Pcoupled. A rectifier circuit 203 is coupled to the secondary winding 201s and supplies the cell output current I21 to the cell output or output OUT1. A PWM (pulse width modulation) controller 204 receives an output current signal I2. 1_ M and the output current reference signal I2 1­_REF The output current signal I2 1_M represents the instantaneous current level (actual value) of the output current I21. The output current reference signal I2 1_REF represents a desired current level of the output current I21. This output current reference signal I2 1_REF This can vary over time because the power consumption of the load can change. In this topology, transformer 219 provides galvanic isolation between the cell input and the cell output.

[0113] The PWM controller 204 is configured to generate a PWM control signal S202, as it controls the electronic switch 202. This is based on the output current reference signal I2. 1_REF and on the output current signal I2 1_M The PWM controller 201 controls a duty cycle of the PWM control signal S202 such that a current level of the output current I21 has a current level that is at least approximately equal to that of the reference signal I2 1_REF The current level is defined. The switching frequency of the PWM control signal S202 can be in the same range as the switching frequency in converter cells 11-1 explained above. N1That is, between 18 kHz and several hundred kHz. The duty cycle is the ratio between the on-time of electronic switch 202 in a control cycle and the duration of the control cycle. The on-time of electronic switch 202 is the time for which the electronic switch 202 is switched on in a control cycle. The duration of a control cycle of electronic switch 202 is the reciprocal of the switching frequency.

[0114] The electronic switch 202, as well as the other electronic switches explained before and below, can be implemented as conventional electronic switches, such as MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field-Effect Transistor), Bipolar Junction Transistor (BJT), HEMT (High Electron Mobility Transistor), especially GaN HEMT, or similar.

[0115] Fig. Figure 32A shows a different type of converter cell, which is located in the Fig. The multi-cell converter shown in 31 can be used. Fig. 32A converter cell 2 shown i (where i denotes any one of the numbers 1 to N3) is implemented with a Dual Active Bridge (DAB) topology. Such a topology is described in the Fig. 2a and Fig. 2b von Everts, J.; Krismer, F.; Van den Keybus, J.; Driesen, J.; Kolar, JW, “Comparative evaluation of soft-switching, bidirectional, isolated AC / DC converter topologies,” Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, pp.1067-1074, 5-9 Feb. 2012, which is incorporated herein in its entirety by reference. Fig. Figure 32 shows an embodiment of a converter cell 2 i , which is implemented with a “full-bridge-full-bridge DAB topology” as described in Everts et al.

[0116] Referring to Fig. The converter cell 2 comprises 32A. i A first (full) bridge circuit with two half-bridges, each comprising a high-side switch 211, 213 and a low-side switch 212, 214. The half-bridges of the first bridge circuit are connected between the cell input nodes to maintain the respective intermediate circuit voltage V2. i switched. A series circuit with an inductive storage element 221 and a primary winding 219 p A transformer 219 is connected between the output nodes of the two half-bridges 211, 212 and 213, 214, respectively. An output node of a half-bridge is a circuit node common to the high-side switch 211, 213 and the low-side switch 212, 214 of the half-bridge. The transformer 219 provides galvanic isolation between the cell input and the cell output, with the cell output being connected between outputs OUT1 and OUT2 of the power converter circuit. The transformer 219 comprises a secondary winding 219S , which are inductively connected to the primary winding 219 P is coupled. Another inductive storage element 220, which is in Fig. 32A in parallel to the primary winding 219 P The figure shown represents the magnetizing inductance of transformer 219.

[0117] A second bridge circuit with two half-bridges, each having a high-side switch 215, 217 and a low-side switch 216, 218, is connected between the secondary winding 219s and the cell output nodes of the cell output. Each of these half-bridges 215, 216 and 217, 218, respectively, comprises an input, which is a circuit node common to the high-side switch 215, 217 and the low-side switch 216, 218 of the respective half-bridge. The input of a first half-bridge 215, 216 of the second bridge circuit is connected to a first node of the secondary winding 219s. SThe input of a second half-bridge 217, 218 of the second bridge circuit is connected to a second node of the secondary winding 219s. The half-bridges of the second bridge circuit are each connected between the cell output nodes.

[0118] Switches 211-214, 215-218 of the first and second in Fig. The bridge circuits shown in Figure 32A can each be implemented by including a rectifier element (freewheeling element), such as a diode, connected in parallel with the switch. These switches can be implemented as known electronic switches, such as MOSFETs (Metal-Oxide Field-Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Field-Effect Transistors), HEMTs (High-Electron-Mobility Transistors), or similar devices. If switches 211-214 and 215-218 are each implemented as MOSFETs, an internal body diode of the MOSFETs can be used as the rectifier element, thus eliminating the need for an additional rectifier element.

[0119] A control circuit 222 controls the operation of the two bridge circuits. For this purpose, each of the switches 211-214 and 215-218 receives its own control signal from the control circuit 24. These control signals are in Fig. 32A is designated as S211 - S214 and S215 - S218. The control circuit receives the output current signal I2. i_M and the output current reference signal I2 i_REF and is designed to control switches 211 - 214, 215 - 218 in such a way that the current level of the output current OUT is essentially that determined by the reference signal I2 i_REF The defined current level corresponds to the specified current level. There are various ways to control switches 211-214 and 215-218 to achieve this. According to one embodiment, the duty cycle of each switch 211-214 and 215-218 is modulated in the range of 50%. For details on controlling the switches, reference is made to F. Krismer and J.W. Kolar, "Closed form solution for minimum conduction loss modulation of DAB converters," IEEE Transactions on Power Electronics, Vol. 27, Issue 1, 2012, which is incorporated herein by reference.

[0120] According to one embodiment, the control circuit 222 is configured to control the timing of the switching on and off of the individual switches 211-214 of the first bridge such that at least some of the switches 211-214 are switched on and / or off when the voltage across the respective switch is zero. This is known as zero-voltage switching (ZVS).

[0121] Fig. Figure 32B shows another embodiment of a converter cell 2 i In this embodiment, the converter cell is 2. i implemented with a buck converter topology. Converter cell 2 i includes a half-bridge 241 with a high-side switch 241 H and a low-side switch 241 L The half-bridge 241 is connected to the cell input in such a way that the associated intermediate circuit voltage V2 i above the series connection with the high-side switch 241 Hand the low-side switch 241 L The voltage drops. A coil is connected between a tap of the half-bridge 241 and one of the cell output nodes. The tap of the half-bridge is a circuit node to which the high-side switch 241 is connected. H and the low-side switch 241 L are connected. A PWM controller 243 receives the output current signal I2. i_M, which the output current 12 i converter cell 2 i represents and the output current reference signal I2 i_REF , which determines the desired current level of the cell output current 12 i represented. The cell output current 12 i The current flows through coil 242. Controller 243 is designed to receive PWM control signals S241. H , S241 L for the high-side and low-side switches 241 H , 241 L to generate such a current that the output current is 12 ihas a current level that is essentially equal to one determined by the output current reference signal 12 i_REF represented current level.

[0122] At the in Fig. In the buck topology shown in 32B, the current level of the output current is 12 i by controlling the duty cycle of the high-side switch 241 H controlled. The low-side switch acts as a freewheeling element, complementary to the high-side switch 241. H switches.

[0123] It should be mentioned that the ones in the Fig. The converter cell topologies shown in Figures 31 and 32A-32B are only two of many possible examples of how the converter cells 21-2 N3 can be realized. The ones in the Fig. 31 and Fig. The topologies shown in Figure 32A each include a transformer 201 or 219, which provides galvanic isolation between the cell inputs and the cell outputs. These transformers also provide galvanic isolation between the inputs IN1, IN2 and the outputs OUT1, OUT2 of a power converter circuit, which uses a multi-cell converter 20, as shown in Figure 32A. Fig. Figure 31 is shown, and is implemented. However, possible implementations of the converter cells 21-2 are N3 not limited to topologies that include a transformer and can be referred to as isolated topologies. Non-isolated topologies can also be used, which are topologies without galvanic isolation between the cell input and the cell output. An example of such a non-isolated topology is the one in Fig. 32B shows the bottom-stop converter topology.

[0124] Referring to Fig. 31 The multi-cell converter 20 includes a main controller 3, which controls the output current reference signals I2 1_REF -I2N 3_REF generated by the individual converter cells 21-2 N3 can be obtained. An embodiment of this main controller is shown in Fig. 33 shown. The one in Fig. The main controller shown in Figure 33 includes an output voltage controller that outputs a voltage signal V. OUT_M and an output voltage reference signal V OUT_REF The output voltage signal V is received. OUT_M represents an instantaneous voltage level of the output voltage VOUT and the output voltage reference signal V OUT_REF represents the desired voltage level of the output voltage V OUT Based on these signals V OUT_REF , V OUT_M , in particular based on a difference between these signals V OUT_REF , V OUT_M , the output voltage controller 31 generates an output current signal I OUT_REFThe output current signal I OUT_REF represents a desired current level of the output current I OUT . According to one embodiment, the individual converter cells 21-2 deliver N3 equal proportions of the output current I OUT In this case, the level of each of the individual converter cells 21-2 N3 received output current reference signal I2 1_REF -I2 N3_REF =I OUT_REF / N3. In the case of the Fig. In the embodiment shown in 33, a divider 31' calculates the output current reference signals I2. 1_REF -I2 N3_REF based on the output current reference signal I OUT_REF .

[0125] The multi-cell converter 20 has a voltage source characteristic when connected to a Fig. The main controller 3 shown in section 33 is implemented. According to one embodiment, the second power converter 20 is configured to increase the output power P. OUT to generate such that the output voltage VOUT is essentially constant. Since the power consumption of the load Z can vary, the second power converter 20 in this embodiment is designed to adjust the output current I. OUT to vary the output voltage V OUT to keep the output current essentially constant, while still meeting the power requirements of the load Z. According to a further embodiment, the second power converter 20 has a current source characteristic. That is, the second power converter is designed to maintain the output current I. OUT to regulate. In this embodiment, the output voltage controller 31 can be omitted. In this case, the output current reference signal I can be used. OUT_REF provided by a (not shown) central controller, similar to the central controller that provides the output voltage reference signal V OUT_REFprovides. In principle, the second power converter can be designed to provide one of the output voltages V. OUT and to regulate the output current. This applies accordingly to each of the second power converters 20 described below, which are designed to supply a direct current.

[0126] Fig. Figure 34 shows an embodiment of the second power converter 20 with an OS (Output Serial) topology. Fig. Figure 34 shows converter cell 21 in detail. The other converter cells 22-2 N3 can be implemented accordingly. The in Fig. The OS topology shown in Figure 34 is similar to the one in Fig. 12 IS topologies are shown. As in Fig. The IS converter shown in the diagram has 12 components. Fig. 33 OS converters shown have a coil connected in series to the cell outputs of the individual converter cells 21-2 N3The series circuit with the cell outputs and the coil 24 is connected between the output nodes OUT1 and OUT2.

[0127] At the in Fig. In the embodiment shown in Figure 34, the individual converter cells are 21-2. N3 implemented with a full bridge topology, which is described in detail above using converter cell 1 as an example. i the IS topology in Fig. 24 is explained. Referring to Fig. 34 The converter cell 21 comprises a first half-bridge 231 with a high-side switch 231 H and a low-side switch 231 L and a second half-bridge 232 with a high-side switch 232 H and a low-side switch 232 L A controller 233 operates these switches 231. H -232 L by generating control signals S231 H -S232 L for these switches 231 H -232 Lbased on a modulation index m1 received from the main controller 5. Unlike in the Fig. 24 converter cell 1 shown i A cell output of converter cell 21 is formed by taps from the two half-bridges. The cell input, where the intermediate circuit voltage V21 is obtained, is formed by the circuit nodes where the two half-bridges 231 and 232 are connected in parallel. The controller can select the full bridge according to one of the above. Fig. 26A and Fig. 26B to control the modulation schemes explained.

[0128] The in Fig. The power converter 20 shown in the diagram with the OS topology can be operated in such a way that it has an output current I OUT to a voltage network connected to the output nodes OUT1 and OUT2. In this case, the output voltage V OUTThe outputs OUT1 and OUT2 are defined by the power grid. In other words, the power converter 20 receives the output voltage V. OUT at the output and supplies the output current I OUT at the output. The instantaneous level of the output power is determined by the instantaneous level of the output voltage V. OUT and defines the instantaneous level of the output current. The output voltage can have a sinusoidal waveform, as shown schematically in Fig. Figure 34 shows that in this case, the second converter 20 generates the output current I. OUT such that the output current I OUT essentially in phase with the output voltage V OUT is (or that a predefined phase difference exists). Furthermore, the second converter 20 can control the amplitude of the output current I. OUTsuch that the intermediate circuit voltage has a predefined voltage level. A second power converter 20, which is designed to control the signal waveform of the output current I OUT to regulate it so that it is essentially identical to the signal waveform of the output voltage V OUT is referred to as the second power converter 20 with a PFC (Power Factor Correction) functionality or, in short, as the second PFC power converter 20.

[0129] At the in Fig. In the embodiment shown in Figure 34, the individual converter cells 21-2 are shared. N3 a coil connected in series with the cell outputs. According to another (not shown) embodiment, each of the converter cells comprises 21-2 N3 A coil is connected between a cell output node and the tap of the first half-bridge 231. In any case, the individual converter cells 21-2 function N3as a buck converter. That is, the cell output voltage of each converter cell 21-2 N3 is lower than the intermediate circuit voltage V21-V2 N2 of the associated intermediate circuit capacitor 111-11 N2 The topology of the in Fig. The converter cell shown in Figure 34 is also referred to below as the full bridge topology (or full bridge bottoming topology).

[0130] The in Fig. The second converter 20 shown in section 34, with the OS topology, can be operated to output an alternating voltage, such as a sine wave, as the output voltage V. OUT from the intermediate circuit voltages V21-V2 N2 to generate a rectified sine wave or a DC voltage as the output voltage. In this case, the output voltage is V. OUTa rectified sinusoidal voltage or a DC voltage, the converter cell 21 can be simplified by omitting the high-side switch 232. H the second half-bridge 232 and by replacing the low-side switch 232 L through a conductor. The converter cell 21 (and each of the other converter cells 22-2) N3 ) then only includes the first half-bridge 231, wherein the first half-bridges of the individual converter cells 21-2 N3 are connected in series. Such a modified topology of the converter cells 21-2 N3 is subsequently referred to as deep-seated topology.

[0131] It should be mentioned that the converter cells 21-2 N3 are not limited to using a full-bridge depression topology, as described in Fig. as shown in 34, or can be implemented with a deep-setting topology as explained above. Other topologies, in particular modifications of the one shown in Fig. The topologies shown in section 34 can also be used. Such a modification is described in Fig. Figure 34 shows this modification. This modification includes an additional switch 234, which is connected between the DC link capacitor 111 and the full bridge. Such a modified topology is known as the H5 topology. The additional switch 234 can be switched on and off synchronously with the one switch that operates in PWM mode in the respective modulation scheme. Another modification includes (not shown) additional switches between the taps of the two half-bridges. Such a modified topology is known as the HERIC topology.

[0132] An embodiment of a main controller 5 configured to control the converter cells 21-2 N3 to operate in such a way that the second converter 20 supplies the total intermediate circuit voltage V2 TOT regulates and the output current I OUTgenerated in such a way that it is essentially in phase with the output voltage V OUT is, is in the Fig. 35 and Fig. 36 shown. Fig. Figure 35 shows a block diagram of an exemplary embodiment of the main controller 5 and Fig. Figure 36 shows an embodiment of the Fig. The main controller shown in section 35 is discussed in more detail below. Fig. 35 and Fig. The main controller 5 shown in Figure 36 is very similar to the main controller 4 of the one shown in the Fig. 13 and Fig. The IS converter shown in 14. Instead of the input reference current controller 41 in the main controller 4, the one shown in Fig. 35 The main controller 5 shown has an output reference current controller 51, which provides an output voltage signal V OUT_M receives the instantaneous voltage level of the output voltage V OUT represented. The output reference current controller 51 also receives intermediate circuit voltage signals V2. 1_M -V2 N2_M, which are the intermediate circuit voltages V21-V2 N2 represent, and a total intermediate circuit voltage reference signal V2 TOT_REF The total DC link voltage reference signal V2 TOT_REF represents a desired signal level of the total intermediate circuit voltage V2 TOT Based on these signals, the output reference current controller 51 generates an output reference signal I. OUT_REF , which is obtained by a modulation index controller 52. Based on the output current reference signal I OUT_REF and based on an output current signal I OUT_M The modulation index controller 52 generates a modulation index m. According to one embodiment, the individual converter cells 21-2 are N3 , which in Fig. 34 are shown, obtained modulation indices m1-m N3 equal to the modulation index m generated by the modulation index controller 52. The output current signal I OUT_Mrepresents a momentary current level of the output current.

[0133] Fig. Figure 36 shows an embodiment of the output reference current controller 51 and the modulation index controller 52. The design and operation of the output reference current controller 51 is similar to the design and operation of the input reference current controller 41 of the [reference to be added]. Fig. The main controller 4 shown in Figure 14 is referenced. Referring to Fig. 36 The output reference current controller 51 includes an error filter 511, which filters the intermediate circuit voltage signals V2 1_M -V2 N3_M and the total DC link voltage reference signal V2 TOT_REF receives and an error signal V2 ERR calculated from these signals. The error filter 511 can have the same filter characteristics as those shown in Fig. The error filter 411 shown in Figure 14 is explained. A multiplier 512 multiplies the error signal V2. ERRwith the total DC link voltage reference signal V2 TOT_REF An output signal A of the multiplier 512 is obtained by a divider 513, which divides the output signal A of the multiplier 512 by a value that is determined by the amplitude of the output voltage V. OUT depends (in this example: V OUT_MAX 2 / 2). An output signal C of the divider 513 is obtained by a further multiplier 514, which combines the divider output signal C with the output voltage signal V OUT_M multiplied. As with the one in Fig. The main controller 4 shown in section 14 is the divider 513 in which it is located. Fig. The main controller 5 shown in Figure 36 is optional. If the divider 513 is omitted, the additional multiplier 514 receives the output signal A from the multiplier 512.

[0134] The in Fig. The second converter 20 shown in Figure 34 is not limited to supplying power to an AC network. The second converter 20 can also supply power to a DC network (a DC bus) that provides the output voltage V OUT defined. In this case, multiplying the divider output signal C or the multiplier output signal A by the output signal V is possible. OUT_M This may not be necessary. In this case, the input signal B of the divider V is OUT_MAX instead of V OUT_MAX 2 / 2.

[0135] The further multiplier 514 outputs the output current reference signal I- OUT_REF If the additional multiplier 514 is omitted, either the output signal C of the divider 513 or the output signal A of the multiplier 512 is the output current reference signal I. OUT_REF .

[0136] Referring to Fig. 36 The modulation index controller 52 subtracts a filtered output current signal I OUT_F from the output current reference signal I- OUT_REF , to generate an output current error signal I OUT_ERR to generate the filtered output current signal I. OUT_F is obtained by filtering the output current signal I OUT_M by a first filter 522. The modulation index m is obtained by filtering the output current error signal I. OUT_ERR by a second filter. The first and second filters 522, 523 can be implemented as shown in Fig. Filters 422 and 423 shown in section 14 are explained.

[0137] Fig. Figure 37 shows an embodiment of the second converter 20 with an op-amp topology. This converter 20 is based on the one described in Fig. 34 shown converter 20 and differs from the one in Fig. 34 converters shown, by the fact that the cell outputs of the individual converter cells 21-2 N3are connected in parallel at output OUT1. In the case of the Fig. In the embodiment shown in 37, each converter cell comprises 21-2 N3 a coil, as shown in the first converter cell 21, where the coil is designated with the reference numeral 241. Furthermore, each converter cell 21-2 comprises N3 a controller that generates the modulation index of the respective converter cell. This is shown in the first converter cell 21, where the controller is designated with the reference symbol 51. The controller in each converter cell, such as controller 51 in converter cell 21, can be assigned to the one described in the Fig. 35 and Fig. 36 shown, corresponding to controller 5, with the difference that the controller (especially the error filter) of a converter cell only receives the DC link voltage signal of the respective converter cell and a DC link voltage reference signal of the respective converter cell instead of the DC link voltage signals V2 1_M -V2N3_M and the total DC link voltage reference signal V2 TOT_REF receives.

[0138] Fig. Figure 38 shows another embodiment of a first power converter 10 with an IP topology. In this embodiment, the individual converter cells 11-1 N1 implemented with Dual Active Bridge (DAB) topology, where in Fig. 38 only shows the topology of the first converter cell 11 in detail. With reference to converter cell 11, the cell topology is based on the one in Fig. 32 cell topology shown. That is, the cell topology comprises two full bridges, each comprising two half bridges, with each half bridge having a high-side switch 101, 103, 108, 110 and a low-side switch 102, 104, 109, 111. As in the Fig. The cell topology shown in 32 is a full bridge (which is in Fig. 38 (full bridge shown with switches 101-104) connected to the cell input, and a full bridge (which is in Fig. The full bridge shown in figure 38 (with switches 108-111) is connected to the cell output. A primary winding 105 P A transformer 105 is connected to taps of the first full bridge 101-104, and a series connection with a secondary winding 105s and another coil is connected to taps of the second full bridge 108-111. Another coil 106, shown in parallel to the secondary winding 105s, represents the magnetizing inductance of the transformer 105. A controller 112 controls the operation of the individual switches of the full bridges by generating control signals S101-S111 of the switches such that a cell input current I01 has a current level determined by an input current reference signal I 1_REF is defined. For this purpose, the controller 112 receives an input current signal I0. 1_M, which represents an instantaneous current level of the input current I01, and the input current reference signal I0 1_REF A main controller 6 generates the input current reference signals I0 1_REF -I0 N1_REF of the individual converter cells 11-1 N1 .

[0139] The in Fig. 38 converter cell 11 shown (just like the other converter cells 12-1 N1 It has a boost and a buck characteristic. This means it can increase the DC link voltage V21 at a higher voltage level or at a lower voltage level than the input voltage V. IN produce. The one in Fig. The converter 10 shown in Figure 38 is not limited to being implemented with converter cells that have a DAB topology. Other previously explained topologies, such as the flyback converter topology or the buck converter topology, can also be used.

[0140] Fig. Figure 39 shows an embodiment of the main controller 6. In this embodiment, the main controller 6 comprises an input voltage controller 61, which receives an input voltage signal V. IN_M and an input voltage reference signal V IN_REF receives and is designed to determine the voltage level of the input voltage V IN to regulate. The input voltage controller 61 generates an input current reference signal I. IN_REF based on these signals. In this embodiment, each of the input current reference signals corresponds to I0. 1_REF -I0 N1_REF , which is achieved through the individual converter cells 11-1 N1 is obtained from the input current reference signal I generated by the input voltage controller 61. IN_REF The input current reference signal I IN_REF represents a desired current level of the input current I IN . According to one embodiment, the individual converter cells 11-1 are provided N1equal proportions of the input current I IN In this case, the level of each of the individual converter cells 11-1 N1 received input current reference signals I1 1_REF -I1 N1_REF equal I IN_REF / N1. In the case of the Fig. In the embodiment shown in 39, a divider 61' calculates the input current reference signals I1 1_REF -I1 N1_REF based on the input current reference signal I IN_REF .

[0141] The input voltage V INThis is regulated, for example, in applications where the input power is supplied by a solar panel with multiple photovoltaic (PV) cells. The efficiency of a PV cell receiving solar power depends on the input voltage, so it may be necessary to vary the input voltage at the PV panel when the solar power received by the solar panel varies. An operating point at which a PV cell has its maximum efficiency (delivers maximum power) for a given solar power is called the maximum power point (MPP). The MPP can be found by varying the voltage at the PV cell or solar panel and by measuring the power received by the solar panel. This is generally known. According to one embodiment, an MPP tracker (not shown), configured to measure the power received at inputs IN1, IN2, provides the input voltage reference signal V.IN_REF , to the power source that provides the input voltage V IN delivers, to operate in MPP.

[0142] According to another embodiment, a central controller (not shown) generates the input voltage reference signal V IN_REF .

[0143] According to another embodiment, the first power converter 10 is designed to measure the input current I IN_ to regulate. In this embodiment, the input voltage controller 61 can be omitted. In this case, the input current reference signal I can be used. IN_REF provided by a central controller (not shown), similar to the central controller that provides the input voltage reference signal V IN_REF can provide.

[0144] Several different topologies of the first power converter 10 and the second power converter 20 are described above. When designing the power converter circuit, the type of first power converter 10 and the type of second power converter can be selected depending on the desired type of power conversion performed by the power converter circuit. Some of the several combinations and their possible applications are explained below.In the following, a power converter circuit designed to obtain a periodic (alternating) input voltage (such as a sinusoidal voltage or a rectified sinusoidal voltage) and to supply a DC output voltage is referred to as an AC / DC power converter circuit; a power converter circuit designed to obtain a DC input voltage and a periodic output voltage, and to supply an alternating current output, is referred to as a DC / AC power converter circuit; and a power converter circuit designed to obtain a DC input voltage and to supply a DC output voltage is referred to as a DC / DC power converter circuit.

[0145] The design and operating modes of a multi-cell power converter, such as one of the previously discussed IS, IP, OS, or OP multi-cell power converters, offer various degrees of freedom that can be used to increase the efficiency of the multi-cell converter and the power converter circuit in which it is used. These degrees of freedom include the number of converter cells in a multi-cell converter, the operating modes of the converter cells, the type of connection between the converter cells, the voltage levels of the DC link voltages, the design of the converter cells, and so on. Some of these degrees of freedom and how they can be used to increase the efficiency of a multi-cell converter are explained below.

[0146] In a multi-cell converter, such as one of the previously described multi-cell converters, each of the multiple converter cells has a maximum rated power. The maximum rated power defines the maximum power that the converter cell can convert. That is, the maximum input power the converter cell can receive or the maximum output power the converter cell can provide.

[0147] Referring to Fig. 40 The efficiency of the individual converter cells can vary depending on a ratio between the instantaneous power and the maximum power. Fig. Figure 40 schematically illustrates the efficiency of a converter cell based on this ratio. Referring to Fig. 40 The converter cell can have its maximum frequency at about 50% of the maximum power, with efficiency decreasing towards lower power levels and towards higher power levels.

[0148] Referring to the preceding explanation, the individual converter cells can be implemented as switched-mode converter cells. This means that these converter cells are implemented as switched-mode power converters and each includes at least one semiconductor switch that operates at a switching frequency. In an operational-mode converter or an integrated power converter, switched-mode operation is used, for example, to control the output currents I21-I2. N3 or the input currents I01-I0 N3 of the individual converter cells 11-1 N1 , 21-2 N3to regulate. The switching frequency can be 18 kHz or higher. Switching the at least one semiconductor switch in a converter cell on and off causes losses. These losses, which can be called switching losses, include a component that is essentially independent of the output power of the respective converter cell. These constant losses, resulting from losses in drivers, microcontrollers, or similar components, are one reason why the efficiency of the converter cell decreases significantly as the output power decreases.

[0149] According to one embodiment, the individual converter cells in a multi-cell converter with an xP topology can be activated (operated in active mode) or deactivated (operated in inactive mode) to operate the multi-cell converter efficiently, that is, to convert the power received by the multi-cell converter efficiently. A multi-cell converter with an xP topology is a multi-cell converter with either an IP topology or an OP topology. Deactivating at least one converter cell in an xP topology can help to increase the efficiency of the other converter cells. This is demonstrated for an OP topology by the Fig. 41A-44 and for an IP topology based on the Fig. 45A-49 explained.

[0150] The individual converter cells in an xP topology can be referred to as "phases." An operating mode in which at least one of these converter cells is inactive is referred to below as "phase-shedding" operation. In phase-shedding operation, active converter cells take over the function of the inactive converter cells, so that the total converted power varies only depending on a power reference signal. The "power reference signal" defines the power that is to be converted by the multi-cell converter.

[0151] For the purpose of explanation, let it be assumed that the power consumption of the load Z is such that each of the converter cells 21-2 N3 a second power converter 20 with an OP topology delivers an output power that is significantly less than 50% of its maximum output power. If one of the converter cells 21-2 N3When one cell is deactivated, so that its output power becomes 0, the power level of the other converter cells must increase to match the power level of the output power P. OUT to keep constant. However, the higher power levels of the other (active) converter cells can lead to a higher efficiency of these active converter cells.

[0152] “Operating a converter cell in inactive mode” means that during inactive operation, the input power received by the respective converter cell and the output power provided by the respective converter cell are essentially zero. Nevertheless, the DC link capacitor associated with the inactive converter cell can continue to be charged by the first power converter 10, as explained below. In active operation, the individual converter cells operate in a clocked fashion at a switching frequency fp, as explained above. During inactive operation, the DC link voltage of the respective converter cell can rise because the first converter 10 charges the respective DC link capacitor 111-11. N2can continue to supply power. This is independent of the specific topology of the first power converter 10. The DC link voltage of the inactive converter cell can rise until the converter cell is reactivated and receives cell input power from the respective DC link capacitor. The DC link capacitors 111-11 N2 They function as a buffer between the first power converter 10, which receives input power from inputs IN1 and IN2, and the second power converter 20, which provides the output power P OUT provides. The energy storage capacity of these DC link capacitors 111-11 N2 allows the converter cells 21-2 N3 to operate cyclically in inactive mode to increase the efficiency of the second power converter 20 when the output power P OUT is low (under low load conditions).

[0153] Fig. Figure 41A shows a first operating scenario of the second power converter 20. In this scenario, one converter cell is in inactive operation at a time. Fig. 41A are only deactivation states of the individual converter cells 21-2 N3 This is shown. That is, the individual time diagrams only show whether the respective converter cell 21-2 N3 is active or inactive. The in Fig. The curves shown in Figure 41A do not show the power levels of the power converter and do not show the current levels of the output current of the respective converter cells 21-2. N3 According to another scenario, which is described in Fig. As shown in 41B, two of the converter cells 21-2 can be N3Up to N3-1 converter cells can be inactive at any given time. Generally, up to N3-1 converter cells can be inactive at any one time, leaving only one converter cell active at any given time. Several different criteria can be used to decide which converter cells belong to the group of N3-K active converter cells and which belong to the group of K inactive converter cells at any given time, and how long each converter cell remains active / inactive before the next decision is made. This is explained in more detail below.

[0154] According to one embodiment, a number K of converter cells that are inactive at a given time are selected based on a reference signal P derived from the output power signal. OUT_REF and an output current reference signal I OUT_REF discontinued. This is in Fig. 42 illustrates the output power reference signal P. OUT_REF defines a desired power level of the output power P OUT, which is to be provided by the second converter 20. If the output voltage V OUT The output current reference signal I is essentially constant. OUT_REF a measure of the desired power level of the output power P OUT . Instead of the output power reference signal P OUT_REF can the current level of output power P OUT and instead of the output current reference signal I OUT_REF can the instantaneous level of the output current I OUT be used.

[0155] Fig. Figure 42 illustrates K based on the output power reference signal P OUT_REF or the output current reference signal I OUT_REF . In the Fig. In the embodiment shown in Figure 42, none (K=0) of the converter cells is inactive when the output power reference signal P OUT_REF above a first threshold P OUT_TH1 is (if the output current reference signal I OUT_REFabove a first current threshold I OUT_TH1 is). A (K=1) converter cell is deactivated (inactive) when the output power reference signal P OUT_REF between the first threshold P OUT_TH1 and a second threshold P OUT_TH2 is (if the output current reference signal I OUT_REF between the first threshold I OUT_TH1 and a second current threshold I OUT TH2 is), two (K=2) converter cells are inactive when the output power reference signal P OUT_REF between the second performance threshold P OUT_TH2 and a third threshold P OUT_TH3 is (if the output current reference signal I OUT_REF between the second current threshold I OUT_TH2 and a third current threshold I OUT_TH3 is), and so on. The difference between adjacent power thresholds or current thresholds can be essentially the same or it can be different.

[0156] Fig. Figure 43 illustrates an embodiment of a method for determining the number K of converter cells to be deactivated and for identifying the cells that are deactivated at any given time. Referring to Fig. 43 The procedure includes determining the number K of cells to be operated in inactive mode, based on the output current reference signal I OUT_REF (1001). The output current reference signal I OUT_REF represents the desired output current I OUT of the second power converter 20. According to one embodiment, K is based on the output current reference signal I OUT_REF according to a curve as it appears in Fig. 40 is shown, fixed.

[0157] Referring to Fig. 43 The procedure also includes identifying the K converter cells that currently have the lowest input voltage (DC link voltage) (1002). Such identification can be used to sort the converter cells 21-2 N3 based on the voltage level of their intermediate circuit voltages 111-11 N3 and include selecting the K converter cells that have the lowest DC link voltages. These K identified converter cells are operated in inactive mode, and the other converter cells are operated in active mode (1003). By operating the converter cells that have the lowest DC link voltages in inactive mode and, correspondingly, by operating the other N3-K converter cells that have the highest DC link voltages in active mode, it is possible to prevent the individual DC link voltages V21-V2 from N2 (see, for example) Fig. 1) become too different. Referring to Fig. 43. The process of determining the number K of converter cells (1001), identifying the K cells with the lowest DC link voltage (1002), and operating the K identified cells in inactive mode (1003) is repeated. The repetition of these process steps 1001-1003 can be time-based or event-based. Time-based repetition of these process steps 1001-1003 can include the regular repetition of these steps 1001-1003. According to one embodiment, the frequency at which process steps 1001-1003 are repeated is less than 0.1 times, or even less than 0.01 times, the switching frequency. According to one embodiment, the frequency at which process steps 1001-1003 are repeated is 500 Hz or less.

[0158] Event-based repetition of these process steps 1001-1003 can include repeating these steps 1001-1003 each time a predefined event occurs. Examples of such events include, but are not limited to, a drop in the DC link voltage V21-V2. N2 below a predefined first voltage threshold, and the increase of an intermediate circuit voltage V21-V2 N2 via a predefined second voltage threshold that is higher than the first threshold. According to a further embodiment, the power drawn by the load at the output is measured and process steps 1001-1003 are repeated when a significant change in the power consumption of the load Z is detected.

[0159] According to one embodiment, the duration during which at least one converter cell is inactive is significantly longer than the period of a drive cycle of the converter cells during active operation. According to another embodiment, the duration during which at least one converter cell is inactive is at least ten times the period of the drive cycle. Referring to the foregoing, the duration Tp of the drive cycle is the reciprocal of the switching frequency fp during active operation.

[0160] Referring to the above explanation, the second power converter 20 includes a main controller 3, which is designed to control the operation of the individual converter cells 21-2. N3 to control. Fig. Figure 44 shows an embodiment of the controller 3, which is configured to operate at least one converter cell in inactive mode. The in Fig. The 44 depicted converter 3 is based on converter 3, which is in Fig. 33 is shown (to whose description reference is made), and differs from the one in Fig. The converter shown in Figure 33 is distinguished by the fact that it additionally includes a cell activation / deactivation controller 32. The cell activation / deactivation controller 32 receives the output current reference signal I. OUT_REF from the output voltage controller 31 (which can be omitted if the output current I OUT (to be regulated). The operation of the cell activation / deactivation controller 32 is based on the following: Fig. The procedures described in section 43 are explained below. The activation / deactivation controller 32 activates / deactivates the individual converter cells. That is, the controller 32 sets the following based on the output current reference signal I- OUT_REF the number K of converter cells to be deactivated, and selects based on the intermediate circuit voltages V21-V2 N2 of the individual converter cells 21-2 N3Select the cells to be deactivated. To identify converter cells 21-2 N3 , which have the lowest intermediate circuit voltage, the controller 32 receives the intermediate circuit voltage signals V2 1_M -V2 N2_M , which are the individual intermediate circuit voltages V21-V2 N2 These voltage signals V2 represent. 1_M -V2 N2_M can be determined from the individual intermediate circuit voltages V21-V2 using conventional voltage measurement circuits (not shown in the figures). N2 will be obtained.

[0161] Referring to Fig. The cell activation / deactivation controller generates 32 current reference signals I2. 1_REF -I2 N3_REF These reference signals I2 1_REF -I2 N3_REF represent desired current levels of the output currents I21-I2 N3 of the individual converter cells 21-2 N3 The cell activation / deactivation controller 32 generates the individual reference signals I2.1_REF -I2 N3_REF such that their sum corresponds to the output current reference signal. That is to say, ∑i=1N3I2i_REF=IOUT_REF

[0162] In this way, the converted power depends only on the output power reference signal P. OUT_REF or the output current reference signal I OUT_REF Operating the multi-cell converter 20 in phase-shedding mode does not result in significant changes to the converted power. The converted power is the product of the input power received by the second converter 20 from the DC link capacitors or the first converter 10, and the output power delivered to the load. The current reference signal of the at least one converter cell to be deactivated is set to zero by the cell activation / deactivation controller 32 to reduce the output power of the deactivated converter cell to zero.

[0163] According to one embodiment, the cell activation / deactivation controller 32 is configured to generate the current reference signals of the active converter cells such that these reference signals are essentially the same, so that the active converter cells provide essentially the same output current. However, this is only one example. According to another embodiment, the cell activation / deactivation controller 32 is configured to generate the individual reference signals I2 1_REF -I2 N3_REFto generate the current reference signals of the active converter cells such that these reference signals are different. According to one embodiment, the cell activation / deactivation controller 32 generates the current reference signal of an active converter cell such that the current reference signal of a converter cell depends on the DC link voltage of the respective converter cell. The current reference signal can be generated such that the current reference signal increases when the DC link voltage of the associated DC link capacitor increases. In this embodiment, those active converter cells that have a higher DC link voltage deliver a higher output current than other active converter cells that have a lower DC link voltage.

[0164] According to another embodiment, the cell activation / deactivation controller 32 generates the reference signals I2 1_REF -I2 N3_REFThe active converter cells are configured according to efficiency curves such that these converter cells operate in a high-efficiency range. A high-efficiency range is, for example, a range in which the efficiency is at least 60% or at least 75% of a maximum efficiency. Referring to the following explanation, the individual converter cells can have their maximum efficiency or a high-efficiency range at different currents. In this case, operating the active cells at different currents, in addition to phase shedding, can help to increase the overall efficiency of the power converter 20.

[0165] It should be mentioned that the block diagrams shown in the drawings represent each of the converters, such as the one in Fig. The controllers 3 shown in Figure 44 and in other drawings, and the controllers 4, 5, and 6 shown in other drawings, serve only to illustrate the functionality of the respective controller and not its implementation. The individual functional blocks can be implemented using conventional technologies suitable for realizing a controller. In particular, the functional blocks of controller 3 can be implemented as analog circuits, digital circuits, or can be implemented using hardware and software, such as a microcontroller running special software to realize the functionality of controller 3.

[0166] Operating converter cells of a multi-cell power converter in active or inactive mode, as described above, Fig. As explained in 41A-44, this is not limited to converter cells in a second power converter 20. Such activation or deactivation of converter cells to operate a power converter circuit efficiently can also be applied to converter cells 11-1. N1 in a first power converter 10 with an IP topology (where the cell inputs of the individual converter cells are connected in parallel). This is shown below using the Fig. 45A-49 explained.

[0167] The Fig. 45A and Fig. 45B shows timing diagrams illustrating how converter cells 11-1 N1 of the first power converter 10 can operate in an active or inactive mode. In the case of the Fig. In the embodiment shown in 45A, only one of the converter cells 11-1 is shown. N1 deactivated at a time when in Fig. In the embodiment shown in 35B, two of the converter cells 11-1 are N1deactivated at one time. In general, up to N1-1 of the converter cells 11-1 can be used. N1 to be deactivated at one time. Activating and deactivating converter cells 11-1 N1 The activation and deactivation of converter cells of the first power converter 10 is similar to the activation and deactivation of converter cells of the second power converter 20, with the difference that in the first power converter 10 at least one converter cell is based on an input power reference signal P IN_REF can be activated or deactivated. The input power reference signal P OUT_REF defines a desired power level of the input power P IN , which is to be obtained by the first converter 10. If the input voltage V IN The input current reference signal I is essentially constant. IN_REF a measure of the desired power level of the input power P IN . Instead of the input power reference signal P IN_REFcan the instantaneous level of the input power P IN and instead of the output current reference signal I OUT_REF can the instantaneous level of the input current I IN be used.

[0168] Referring to Fig. 46 The number K of converter cells that are deactivated at any one time can increase when the input power reference signal P IN_REF or the input current reference signal I IN_REF decreases. The input current reference signal I IN_REF represents a desired current level of the input current I IN . Referring to Fig. 46. ​​A converter cell (K=1) can be deactivated if the input power reference signal P IN_REF below a first threshold P IN_TH decreases or the input current reference signal I IN_REF below a first current threshold I IN_TH1 as the input power reference signal P drops, two converter cells (K=2) can be deactivated. IN_REFor the input current reference signal I IN_REF below a second threshold P IN_TH2 or I IN_TH2 drops, and three (K=3) converter cells are deactivated when the input power reference signal P IN_REF and the input current reference signal I IN_REF below a third threshold P IN_TH3 or I IN_TH3 sink.

[0169] In the previously described embodiments, there are four converter cells 11-1 N1 (N1=4). However, this is only an example. The number N1 of converter cells connected in parallel is not limited to N1=4. In general, two or more converter cells can be connected in parallel.

[0170] Fig. Figure 47 illustrates an embodiment of a method for deactivating at least one of the converter cells 11-1 N1 The procedure includes determining the number K of converter cells to be operated in inactive mode (1011). The in Fig. The 47 illustrated method uses the input current reference signal I IN_REF , to detect the desired input power and set K. However, any other signal representing the instantaneous or desired input power can also be used. Setting the number K can be done in accordance with the Fig. The procedure is carried out as shown in the curve 46. It also includes identifying the K cells with the highest output voltages (DC link voltages) (1012), operating these K identified cells in inactive mode, and operating the other cells in active mode (1013). Process steps 1011-1013, which determine the number K, identify the K cells with the highest output voltage, and operate the K identified cells in inactive mode, can be repeated periodically (time-based) or event-based. According to one embodiment, event-based repetition of these process steps 1011-1013 can include repeating process steps 1011-1013 when the voltage level of an DC link voltage V21-V2 N2 one of the several converter cells 11-1 N1 rises above a predefined first threshold or the voltage level of one of the several intermediate circuit voltages V21-V2N2 falls below a predefined second threshold, which is lower than the first threshold.

[0171] Fig. Figure 48 shows a block diagram of an embodiment of a main controller 6, which is configured to control the individual converter cells 11-1 N1 to activate or deactivate. This main controller 6 is based on the main controller 6, which is in Fig. Figure 39 (whose description is referenced) and differs from this main controller 6 in that it additionally includes a cell activation / deactivation controller 62. The cell activation / deactivation controller 62 receives the input current reference signal I IN_REF from the input voltage controller 61 (which can be omitted if the input current is to be regulated) and generates input current reference signals I0 1_REF , I0 2_REF , I0 3_REF , I0 N1_REF for the individual converter cells 11-1 N1These input current reference signals I0 1_REF -I0 N1_REF are through the individual converter cells 11-1 N1 received, which are trained to manage their input streams I01-I0 N1 as explained above, based on these reference signals I0 1_REF -I0 N1_REF to regulate.

[0172] The cell activation / deactivation controller 62 is configured to set the reference current of the at least one converter cell to be deactivated to zero. According to one embodiment, the levels of the input current reference signals of the converter cells to be activated (operating in active mode) are the same. According to another embodiment, the cell activation / deactivation controller 62 is configured to generate the input current reference signals of the activated converter cells with different current levels. The cell activation / deactivation controller 62 generates the signal levels of the active converter cells, for example, based on the DC link voltages, such that the reference signal decreases when the DC link voltage increases to recharge the DC link capacitors of the converter cells 11-1. N1 to charge more slowly, which has a relatively high intermediate circuit voltage V21-V2 N2 have.

[0173] According to a further embodiment, the activation / deactivation controller 32 is configured to generate the current reference signals of the active converter cells based on efficiency curves of the active converter cells such that these converter cells operate in a high-efficiency range. A high-efficiency range is, for example, a range in which the efficiency is at least 60% or at least 75% of a maximum efficiency.

[0174] In any case, the sum of the reference signals corresponds to the input current reference signal I. IN_REF . That means, ∑i=1N1I0i_REF=IIN_REF

[0175] This means that the input power depends only on the input power reference signal P. IN_REFor the input current reference signal. Therefore, operating the multi-cell converter 10 in phase-shedding mode does not lead to significant changes in the converted power. The converted power is the input power received by the first converter 10 at its input and the output power delivered to the DC link capacitors or to the second converter.

[0176] Activating / Deactivating converter cells 11-1 N1 of the first power converter based on an input current reference signal I IN_REF can be achieved in particular by a power converter circuit that takes a DC voltage as the input voltage V IN receives.

[0177] However, enabling / disabling converter cells in a power converter with an IP or OP topology is not limited to power converters that maintain or generate a DC voltage. Such enabling or disabling of converter cells can also occur in a multi-cell converter of the type described in the text. Fig. 29 of the type shown, which includes several converter cells 11-1 N1 includes devices whose cell inputs are connected in parallel, which has PFC functionality and which has a periodic input voltage V IN receives. As shown below in the Fig. 50 and Fig. As explained in more detail in section 53, the input power P varies. IN in such a power converter periodically at a frequency that is twice the frequency of the input voltage V IN The input power is zero when the instantaneous level of the input voltage V is zero. INzero, and increases as the level of the input voltage increases, until the input voltage V IN The maximum is reached. After the input voltage reaches its maximum (or minimum in the shallower half-wave), the input power decreases until the input voltage reaches zero again. According to one embodiment, the converter cells 21-2 N1 based on the level of at least one of the input voltage V IN and the input current I IN_ activated and deactivated in such a way that the number of activated converter cells increases within a half-wave when the input voltage V IN and / or the input current increases and decreases when the input voltage V IN and / or the input current decreases. The sequence in which the converter cells are activated and deactivated in a half-wave can change, so that the DC link capacitors 111-11 N2will be loaded immediately. A controller (in Fig. (29 not shown) can the individual converter cells 11-1 N1 based on at least one of the input voltages V IN and the input current I IN_ activate and deactivate.

[0178] Accordingly, in a multi-cell converter of the in Fig. 37 of the type shown, which includes several converter cells 21-2 N3 features cell inputs connected in parallel, a PFC function, and a periodic output voltage V OUT receives the converter cells 21-2 N3 based on the level of at least one of the output voltage V OUT and the output current I OUT are activated and deactivated in such a way that the number of activated converter cells increases within a half-wave when the output voltage V OUT and / or the output current I OUT increases and decreases when the output voltage VOUT and / or the output current I OUT from drops. Fig. Figure 49 shows a main controller 6 according to a further embodiment. In this embodiment, the main controller 6 comprises, instead of the input voltage controller 61, an intermediate circuit voltage controller 60, which is configured to measure the input current reference signal I. IN_REF based on a difference between the total intermediate circuit voltage V2 TOT and to generate the desired intermediate circuit voltage.

[0179] Another way to increase the efficiency of a multi-cell power converter under low-load conditions is to operate the multi-cell power converter intermittently, such that the average converted power changes. According to one embodiment, the multi-cell power converter is an IS, OS, IP, or OP power converter with PFC functionality, such as one of the previously described IS, OS, IP, or OP power converters with PFC functionality. Operating such power converters in an intermittent operation mode is described by the Fig. 50-53 explained. According to a further embodiment, the multi-cell converter is one of an IS, OS, IP, or OP power converter configured to maintain or provide a DC voltage. The operation of such power converters in an intermittent operating mode is explained by the Fig. Explained in sections 54-59.

[0180] In general, the converted power of an IS, OS, IP, or OP converter with PFC functionality varies periodically because the input voltage and current also vary periodically. For example, if the input voltage V IN in an IS, IP converter (or the output voltage V) OUT in an OS or op-amp converter) is a sinusoidal voltage and the input current I IN (the output current I OUT Since the signal waveform is sinusoidal, the converted power has a sinusoidal square waveform and a frequency that is twice the frequency of the sinusoidal voltage. The converted power is the input power received at inputs IN1 and IN2 in an IS or IP converter and the output power P provided at outputs OUT1 and OUT2. OUTin an OS or op-amp converter. In normal operation (non-intermittent operation), the average and peak power levels of the converted power depend only on the power being converted. This power to be converted can be defined by the input current reference signal I. IN_REF or the output current reference signal I OUT_REF .

[0181] In intermittent operation, the average power level and the peak power level fluctuate. This is demonstrated by... Fig. 50 explains, which schematically illustrates the signal waveform of an input voltage V IN of an IS power converter or the signal waveform of an output voltage V OUT illustrated by an OS power converter. The in Fig. The voltage shown in Figure 50 is a sinusoidal voltage. However, the operating mode explained below applies accordingly to a rectified sinusoidal voltage. Fig. 50 further illustrates the input current I IN or the output current I OUT and the input power P IN or the output power P OUT .

[0182] At the in Fig. In the embodiment shown in section 50, the power converter only converts power during negative half-waves of the input voltage V. IN or the output voltage V OUT During these negative half-waves, the signal waveform of the current I follows IN , I OUT the signal waveform of the voltage V IN / V OUT That is, the current I IN / I OUT is essentially in phase with V IN / V OUT , and a current level is essentially proportional to a voltage level of voltage V IN / V OUT The power P IN , P OUT It exhibits a sinusoidal signal pattern during the negative half-cycles. Fig. 50 also illustrates the average power levels P IN_AVG , P OUT_AVG during the negative half-waves.

[0183] At the in Fig. In the embodiment shown in section 50, the multi-cell converter is operated in such a way that the current I IN , I OUT , and thus the average power level P IN_AVG , P OUT_AVGThe voltage is zero during the positive half-waves. However, this is just one example. Generally, operating the multi-cell converter in intermittent mode means operating it in such a way that the average power level alternates between different levels, one of which is less than 80%, less than 50%, or even less than 30% of the other. The "average power level" is the average power level in a half-cycle, that is, in a time period between two successive zero crossings of the voltage V. IN / V OUTThis applies to both sinusoidal and rectified sinusoidal voltages. For a sinusoidal voltage, zero crossings are the times when the voltage level is zero, that is, when the voltage changes from a positive to a negative level, and vice versa. For a rectified sinusoidal voltage, zero crossings are the times when the voltage becomes zero or nearly zero before the voltage level rises again.

[0184] At the in Fig. In the illustrated embodiment 50, the average power level P changes. IN_AVG , P OUT_AVG with each half-wave, so that the frequency of changes in the average power level is twice the frequency of the voltage V IN / V OUTThis is just one example. Instead of reducing the average power only in every other half-cycle (every positive half-cycle), there can be two or more half-cycles in which the average power is reduced to a lower level before another half-cycle occurs in which the average power is at the higher level. It is also possible to have the higher level for two or more consecutive half-cycles and then switch to the lower level for one, two, or more consecutive half-cycles. In any case, in intermittent operation, the average power level alternates between different levels. The average power levels between which the average power alternates can vary.This means that the lower level can change, for example, between a first point in time when the average power reaches the lower level, and a second point in time that lies after the first point in time.

[0185] Fig. Figure 51 shows an embodiment of a main controller 4, an IS power converter, which has functionality for intermittent operation. The in Fig. The main controller 4 shown in section 51 is based on the main controller 4, which is in Fig. 13 is shown (to whose description reference is made), and differs from the one in Fig. The main controller 4 shown in Figure 13 is modified by the fact that it additionally includes a controller for intermittent operation between the input reference current controller 41 and the modulation index controller 42. The controller 43 for intermittent operation receives the input current reference signal I. IN__REFfrom the input reference current controller 41 and is designed to provide a modified input current reference signal I IN_REF 'to generate such that the modified input current reference signal I IN_REF 'the input current reference signal I IN_REF during certain half-cycles of the voltage V IN / V OUT corresponds and that the modified input current reference signal I IN_REF ' during certain half-waves of the voltage V IN / V OUT a lower amplitude, such as zero. In the case of the Fig. In the embodiment shown in Figure 50, the controller 43 directs the input current reference signal I for intermittent operation. IN__REF during the negative half-waves of the voltage V IN / V OUT to the modulation index controller 42 and sets the modified input current reference signal I IN_REF ' during the positive half-waves of the voltage V IN / V OUTto zero. During such time periods, in which the modified input current reference signal I IN_REF 'If zero, the modulation index controller 42 generates the modulation index m such that the input current I IN of the power converter is zero. During this period, the individual converter cells can continue to operate in clocked mode, so there can be periods in which the multi-cell power converter receives an input current. However, there are also periods in which the input current is negative (the multi-cell power converter supplies current to the power source), so the average input current during such periods, in which the modified input current reference signal I IN_REF 'Zero is, zero is.'

[0186] During such time periods, in which the modified input current reference signal I IN_REF'If zero is, the multi-cell power converter can measure the cell input voltages V11-V1 N1 As explained previously, this still generates. In particular, during periods when the average input current is supposed to be zero, the main controller can only operate one converter cell per drive cycle. This is demonstrated by the Fig. The time diagram shown in section 27 is explained. Referring to Fig. 27, switches the total cell input voltage V1 TOT between two voltage levels that are assigned to a range of the modulation index m. In the case of the Fig. In the embodiment shown in 27, the total cell input voltage V1 is switched off. TOT between zero and V2 TOT / N1, if the modulation index is between 0 and 0.25, switches between V2 TOT / N1 and V2 TOT / 3 if the modulation index is between 0.25 and 0.5, and so on.

[0187] According to one embodiment, the multi-cell power converter is operated in such a way that only one converter cell is clocked to determine the total cell input voltage V1. TOT between two different voltage levels (such as between V2) TOT / N1 and V2 TOT / 3 at the in Fig. (27 illustrated embodiment) to switch one converter cell off and operate the other converter cells statically. “Operating the other converter cells statically” means that a converter cell switches to the off state when the modulation index reaches a certain level and remains in this off state until the modulation index falls below this certain level again. For example, a converter cell can be switched off when the modulation index reaches the level shown in Figure 27. Fig. 27 illustrated embodiment 0.25 is achieved to achieve a proportion of V2 TOT / N1 to the total cell input voltage V1 TOTto contribute, and remains in the off state until the modulation index falls below 0.25. This operating mode, in which only one converter cell is clocked and the other converter cells are operated "statically," is subsequently referred to as block operation. The number of converter cells operating statically in the off state increases as the input voltage level increases. That is, based on the input voltage level V IN The converter cells are operated in PWM mode, on mode and off mode, with one embodiment in which only one converter cell is operated in PWM mode at a time.

[0188] At the in Fig. In the embodiment shown in Figure 50, the average power received / provided by the multi-cell converter during the negative half-wave is zero and differs from zero during the positive half-waves. In this embodiment, the average power provided during the negative half-waves is twice the average power that would be received / provided if the multi-cell converter were operated continuously (not intermittently). However, as shown by Fig. As explained in section 40, the efficiency of the converter cells of the multi-cell converter can decrease if the power converted by the individual converter cells decreases. Intermittent operation of the multi-cell converter, that is, operating the multi-cell converter at a higher power during certain time periods (such as the negative half-waves during the period described in section 40), can lead to a decrease in efficiency. Fig. The efficiency of the multi-cell power converter can be increased (as illustrated in the embodiment shown in section 50).

[0189] According to one embodiment, the controller 43 calculates the average input power received during a half-cycle for intermittent operation and decides, based on this calculation, whether the multi-cell power converter should operate in intermittent mode or in normal operation. In normal operation, the controller 43 passes the input current reference signal I for intermittent operation. IN_REF to the modulation index controller 42. In intermittent operation, the ratio between time periods in which the input power is zero and time periods in which the input power differs from zero (this ratio is 1:1 in the case of the Fig. (Exemplary embodiment shown in section 50) is calculated based on the calculated power. Referring to Fig. 51. The controller can use the input voltage signal V for intermittent operation. IN_M and the input current signal I IN_M to obtain the average input power during one half-cycle of the voltage V IN / V OUT to calculate.

[0190] Fig. Figure 52 shows an embodiment of a main controller 5 in an OS multi-cell converter, which has functionality for intermittent operation. This main controller 5 is based on the main controller 5 described in Fig. 35 is shown (to whose description reference is made) and differs from the one in Fig. The main controller 5 shown in Figure 35 is distinguished by the fact that it includes a controller 53 for intermittent operation between the output reference current controller 51 and the modulation index controller 52. This controller 53 for intermittent operation receives the output current reference signal I. OUT_REFfrom the output reference current controller and provides a modified output current reference signal I- OUT_REF ' to the modulation index controller 52. The operation of the in Fig. The main controller 5 shown in section 52 can be used for the operation of the [unclear text] in Fig. The main controllers shown in section 51 correspond to 4, with the difference that the one in Fig. 52 Main controllers shown 5 the output voltage signal V OUT_M and the output current signal I OUT_M instead of the input voltage signal V IN_M and the input current signal I IN_M processed. However, regarding the input voltage V IN and the input current I IN As explained in the context of an IS power converter, the following applies to the output voltage V OUT and the output current I OUT in an OS power converter accordingly.

[0191] Operating a multi-cell power converter in an intermittent mode is not limited to multi-cell power converters with an IS topology or an OS topology. The previously discussed approach... Fig. The intermittent operating mode described in sections 50-52 can be implemented accordingly in an IP power converter of the type described in Fig. 29 of the type shown and an OP power converter of the type shown in Fig. 37 types shown are used. Fig. 53 shows timing diagrams of the input voltage V IN or the output voltage V OUT of the cell input current I0 i or the cell output current I2 i a converter cell and the input power P IN or the output power P OUTof the multi-cell converter with one of these IP and OP topologies. Each of these parallel-connected converter cells can be operated in an intermittent mode as previously described. In intermittent operation, the average power converted by a converter cell alternates between a higher level and a lower level, where the lower level can be less than 80%, less than 50%, or even less than 30% of the first level. Cell controllers of these converter cells can control the power consumption described in the Fig. The main controllers 4 and 5 shown in sections 51 and 52, respectively, correspond to the difference that one controller uses a total DC link voltage signal V2 instead of the other. TOT _REF and each of the intermediate circuit voltage signals V2 1_M -V2 N2_M It only processes one DC link voltage reference signal and the DC link voltage signal of the respective converter cell.

[0192] According to one embodiment, in the intermittent operating mode of a power converter with parallel-connected converter cells, the number of converter cells operating at the lower level is the same in each half-cycle. If the first average power level of the individual converter cells is the same, and if the lower average power level of the individual converter cells is the same, the overall average power level (which is the sum of the average power levels of the individual converter cells) is essentially the same in each half-cycle. In this case, operating the individual converter cells in intermittent mode does not result in a varying average power level of the multi-cell converter.

[0193] According to one embodiment, each converter cell in a power converter with parallel-connected converter cells is operated intermittently, and the converter cells are synchronized so that they change their average power level at the same time. In this case, the average power level of the multi-cell converter varies. This is in Fig. 53 shows where the average converted power level P IN_AVG , P OUT_AVG is drawn in such a way that it varies. According to one embodiment, at least one converter cell is operated in intermittent mode and at least one converter cell is operated in normal mode. In this case, the converted power P can IN , P OUT have a signal waveform as it appears in Fig. 53 is shown in dashed lines.

[0194] If in one of the previously based on the Fig. In sections 1 and 4-7, the power converter circuits described show that the first power converter has an IS or IP topology and, as shown by the Fig. As explained in sections 50-53, when operated in an intermittent operating mode, the intermediate circuit capacitors 111-11 act. N2 as buffers that ensure a continuous power flow to the second power converter 20 and the load. If the second power converter 20 is implemented with an OS topology and an OP topology, the first power converter 10 can continuously draw power from the power source and charge the DC link capacitors 111-11. N2 load.

[0195] Fig. Figure 54 shows an embodiment for operating a multi-cell power converter with an IP topology or an OP topology, such as one of the previously described examples. Fig. 29 and Fig. 38 topologies were explained, in an intermittent operation. Fig. Figure 54 shows timing diagrams of the activation states of the individual converter cells. These converter cells are converter cells 21-2. N3 in an OP power converter and converter cells 11-1 N1 in an IP power converter. According to the in Fig. In the embodiment shown in Figure 54, operating the power converter in intermittent mode can involve activating only one converter cell at a time. In the embodiment shown in Fig. During the time period shown in section 54, a first converter cell 21 or 11 and a second converter cell 21 or 22 are activated. OP This refers to an activation time, which is the duration during which the respective converter cell is activated. These activation times are specified in the Fig. The embodiment shown in Figure 54 is drawn so that they are identical. However, this is only an example. These activation times can vary depending on various parameters. This is explained in more detail below. In the embodiment shown in Figure 54, the activation times can vary depending on various parameters. This is explained in more detail below. Fig. In the embodiment shown in Figure 54, there is a time period between the activation times of the converter cells 21, 22. Thus, the converted power P changes. OUT (P IN This means that there are times when the power level of the converted power changes from a higher level to a lower level, and times when the power level of the converted power changes from the lower level to the higher level. The higher level and the lower level can vary. However, each time a change in power level occurs from the higher level to the lower level, the lower level is less than 80%, less than 50%, or even less than 30% of the higher level.

[0196] At the in Fig. In the embodiment shown in Figure 54, the lower level is zero. This means that there are times when none of the converter cells are active. However, this is only one example. It is also possible that one or more converter cells are active while at least one other cell is operating intermittently. In this case, the lower level is different from zero.

[0197] If, in one of the previously described power converter circuits, the second power converter 20 is implemented as an operational converter with intermittent operation functionality, an output capacitor 30 can ensure a continuous power flow to the load Z. This is in Fig. 55 schematically represented. Fig. Figure 55 shows a section of the power converter circuit. Referring to Fig. An output capacitor 30 can be connected between the output nodes OUT1 and OUT2. This output capacitor 30 is intermittently supplied with power by the second power converter 20, which has an op-amp topology. However, due to the charge storage capability of the output capacitor 30, the load Z can continuously draw power from the power converter circuit at the outputs OUT1 and OUT2.

[0198] Fig. Figure 56 shows an embodiment of a method for operating a multi-cell converter with OP topology in intermittent operation. Referring to Fig. 56 The procedure includes the evaluation of the output current reference signal I OUT_REF(1031). The output current reference signal represents the desired output power of the multi-cell converter. Instead of the output current reference signal, another signal representing the output power can also be used. Evaluating the output current reference signal I OUT_REF This includes comparing the output current reference signal I OUT_REF with an optimal output current signal I OUT_OPT of a converter cell. This optimal output current signal represents an output power at which the converter cell either exhibits its maximum efficiency or at which the efficiency of the converter cell does not fall below a predefined efficiency level. Instead of the optimal output current signal, another signal representing the output power at which the converter cell exhibits its maximum efficiency can also be used.

[0199] Referring to Fig. 56 The multi-cell converter is operated in non-intermittent mode when the output current reference signal I- OUT_REF not below the optimal output current I OUT_OPT This operation is considered normal operation (1030) in Fig. 56. This normal operation may include a phase shedding, so that in normal operating mode some of the converter cells may be inactive, as previously shown by the Fig. 40, Fig. 41, Fig. 42, Fig. 43, Fig. 44, Fig. 45, Fig. 46, Fig. 47, Fig. 48 to Fig. 49 explained. However, in normal operating mode at least one converter cell is active at any given time, so there is no period in which each of the converter cells is inactive (deactivated).

[0200] If, referring to Fig. 56, the output current reference signal I OUT_REF below the level of the optimal output current signal I OUT_OPTWhen a converter cell is in operation, the multi-cell converter switches to intermittent operation, in which the operating time T OP is calculated (1032), as in Fig. Figure 56 is shown. Then the converter cell with the highest input voltage is identified, and the reference current of the identified converter cell is used for the calculated time period T. OP on I OUT_OPT The reference currents of the other converter cells are set to zero. According to one embodiment, the power converter first switches to phase-shedding operation when the level of the power reference signal (such as the output current reference signal) drops, and finally switches to intermittent operation when the power reference signal (such as the output current reference signal) continues to drop.

[0201] According to one embodiment, the individual converter cells are designed such that they essentially produce the same optimal output current I OUT_OPT have. According to a further embodiment, the individual converter cells are designed such that they have different optimal output currents I. OUT_OPT have. In this embodiment, intermittent operating mode can begin when the output reference signal I OUT_REF If the voltage drops below the level of the lowest optimal output current, then the converter cell with the highest input voltage is identified, and the operating time is determined based on the output current reference signal I- OUT_REF and the optimal output current I OUT_OPT The output current of the identified converter cells is calculated. The identified converter cell is then operated at its optimal output current for the calculated duration, while the other converter cells are operated at an output current of zero.

[0202] Fig. Figure 57 shows an embodiment of a method for operating a multi-cell converter with an IP topology in intermittent operation. The in Fig. The 57 methods presented are based on the one described in Fig. The procedure described in section 56 is referenced. The difference between the procedure described in section 56 is as follows: Fig. 56 explained procedures and the one in Fig. The method described in section 57 consists in the fact that in the multi-cell converter with the IP topology the input current reference signal I IN_REF with an optimal input current I IN_OPT is compared (compare 1041 in Fig. 57) and that the operating time T OP based on the input current reference signal I IN_REF and the optimal input current I IN_OPT is calculated. Everything is based on the in Fig. The procedure illustrated in section 56, which was explained in detail, applies to the procedure in Fig. 57 illustrated procedures accordingly.

[0203] Fig. Figure 58 shows an embodiment of a main controller 3 in a multi-cell converter with OP topology. The main controller 3 is based on the one described in Fig. 33 shown main controller 3 and differs from this in Fig. The main controller shown in 33 is designed by the fact that the controller 33 uses the output current reference signal I for intermittent operation. OUT_REF from the output voltage controller 31 (which can be omitted if the output current is to be regulated) and the output current reference signals I2 1_REF -I2 N3_REF according to the based on Fig. The procedure described in section 56 is generated. That is, the controller 33 for intermittent operation sets the signal level of the identified converter cell to I. OUT_OPT for the calculated operating time T OP firmly.

[0204] Fig. Figure 59 shows an embodiment of a main controller 6 in a multi-cell converter which has an IP topology and functionality for intermittent operation. This in Fig. 59 main controllers shown 6 are based on the one in Fig. 39 shown controller 6 and differs from this in Fig. 39 controller shown, in that it additionally has a controller 63 for intermittent operation, which provides the input current reference signal I IN_REF from the input voltage controller 61 (which can be omitted if the output current is to be regulated) and the input current reference signals I0 1_REF -I0 N1_REF according to the based on Fig. The procedure described in section 57 is generated. That is, the controller 63 for intermittent operation sets the signal level of the identified converter cell for the calculated operating time T. OP on I IN_OPT .

[0205] Each of the based on the Fig. 56 and Fig. The 57 explained intermittent operating modes can determine the output current reference signal I OUT_REF or the input current reference signal I IN__REF are evaluated periodically. According to one embodiment, the multi-cell converter switches to intermittent operation, which reduces the power reference signal below a first threshold (which is defined in the Fig. 56 and Fig. 57 illustrated embodiments with I OUT_OPT and I IN_OPT The power reference signal (designated as the reference signal) drops and exits intermittent operation when it rises above a second threshold higher than the first. This hysteresis prevents the multi-cell converter from frequently switching between intermittent and non-intermittent operation when the power reference signal is close to the first threshold.

[0206] Fig. Figure 60 shows an embodiment of a power converter circuit in which the power converter 10 has an IS topology and in addition to the converter cells 11-1 N1 It has a filter cell 10. As explained above, the converter cells are 11-1 N1 each is designed to receive a cell input power at a cell input and a cell output power at a cell output, to which the intermediate circuit capacitor 111-11 is connected. N2 is connected, to provide. The second power converter 20 is connected to the intermediate circuit capacitors 111-11. N2 The first power converter 10 is connected. The second power converter 20 can be implemented using one of the previously described topologies for the second power converter.

[0207] The filter cell 10 includes a capacitor 110 (which is in Fig. 60 is drawn outside the block representing filter cell 10). Unlike the intermediate circuit capacitors 111-11N2 The capacitor 110 of filter cell 10 is not connected to the second power converter 20. Filter cell 10 can be operated in input power mode, where the filter cell receives input power at one terminal, and in output power mode, where the filter cell provides output power at the terminal of filter cell 10. The filter cell terminal comprises two nodes and is connected in series with the cell inputs of converter cells 11-1. N1 switched. The series connection with the cell inputs of the converter cells 11-1 N1 and the connection of filter cell 10 is connected to the input IN1, IN2 of the power converter circuit.

[0208] Filter cell 10 can be built with the same topology as converter cells 11-1. N1 can be realized. An embodiment of the filter cell 10 is shown in Fig. 61 shown. In the Fig. In the embodiment shown in 61, the filter cell 10 is implemented with a full bridge topology, which is described above based on Fig. 24 is explained. In the Fig. In the filter cell 10 shown in section 61, the individual components have the same reference symbols as the corresponding components in the Fig. 24 converter cell 1 shown i , where a subscript “0” is added to the reference sign of the in Fig. Filter cell 10, shown in Figure 61, was added. The operation of filter cell 10 corresponds to the operation of converter cell 1. i That is, a controller 190 of the filter cell 10 receives a modulation index m0 and controls the operation of the low-side switch 17. 0L and the high-side switch 17 0H the first half-bridge 170 and the low-side switch 18 0L and the high-side switch 18 0H the second half-bridge 180 based on the modulation index m0 according to one of the based on the Fig. 26A and Fig. 26B explained the modulation schemes.

[0209] Implementing filter cell 10 with a full bridge topology is just one example. Filter cell 10 could also be implemented with only a half bridge (as shown in...). Fig. 12 explained), if the input voltage V IN a rectified sinusoidal voltage or a direct current voltage.

[0210] The operation of the in Fig. The first power converter 10 shown in Figure 60 is controlled by a main controller 4. An embodiment of this main controller is shown in Figure 60. Fig. Figure 62 shows this main controller 4. This main controller 4 is based on the main controller 4 shown in Fig. 13 is shown (to whose description reference is made) and differs from the one in Fig. The main controller shown in Figure 13 is further modified by the fact that it additionally includes a converter and filter cell controller 44, which receives the modulation index from the modulation index controller 42. The converter and filter cell controller 44 supplies a modulation index m0 to the filter cell 10 and modulation indices m1-m N1 to the converter cells 11-1 N1 .

[0211] Fig. 63 illustrates one operating mode of the in Fig. 60 of the power converter 10 shown during one period of a sinusoidal input voltage V IN In Fig. 63 designates V1 TOT The total cell input voltage and V10 denotes the average cell input voltage of the filter cell, that is, the cell input voltage averaged over one or more drive cycles. In the case of the Fig. In the first power converter 10 shown in Figure 60, only the filter cell 10 is clocked at the switching frequency, such as 20 kHz or higher. The converter cells can be operated in block mode. This means that these converter cells can switch at a frequency that is twice the frequency of the input voltage V. IN is such that each converter cell is only activated once during one half-cycle of the input voltage V IN It is switched between the off and on states. That is, based on an instantaneous voltage level of the input voltage V. IN The converter cells are operated in one of two modes: on-mode or off-mode. However, it is also possible to switch the converter cells at the switching frequency of filter cell 10.

[0212] Fig. Figure 64 shows an embodiment of a method for calculating the modulation index m0 of the filter cell and the modulation indices of the converter cells. For the purpose of explanation, it is assumed that the DC link voltages of the converter cells are essentially the same, i.e., equal to V2. TOT / N1. Referring to Fig. 64 The procedure includes calculating a number F of converter cells to be operated in off-mode (1051). The total cell input voltage V1 TOT , which is provided by these F converter cells, is F·V2 TOT / N1. Calculating this number F involves determining the number F of converter cells that are in the They are to be operated in off state by calculating F=Round[m⋅N1] That is, by the product of the modulation index m and the number N1 of converter cells, and by rounding the result. The modulation index m0 of filter cell 10 is then calculated based on the voltage V20 across capacitor 110 and the desired average voltage V10 at the terminal of filter cell 10 during a drive cycle by m0 = V10 / V20 (1052), where V20 is the voltage across capacitor 110 and V10 is the desired voltage at the terminal of the filter cell. The desired voltage V10 at the terminal of the filter cell corresponds to V10=m⋅V2TOT−F⋅V2TOTN1 where m is the modulation index calculated by the modulation index controller and V2 TOT The total DC link voltage is.

[0213] The converter and filter cell controller 44 then operates the filter cell at the calculated modulation index m0, and operates F converter cells in off mode (modulation index m). i=1) and operates N1-F converter cells in single-mode operation (modulation index m) i =0) (1053). This determining (1051), calculating (1052), and operating (1053) can be repeated cyclically. According to one embodiment, these steps are repeated regularly. According to one embodiment, the frequency at which these steps are repeated is less than 0.1 times, or even less than 0.01 times, the switching frequency of filter cell 10.

[0214] Referring to the explanation above, the converter cells can be operated in block mode, meaning they are switched from off to on only once per half-cycle. In a multi-cell converter implemented with a filter cell, where the converter cells are operated in block mode, the filter cell can be optimized for low switching losses, while the converter cells can be designed for low line losses.

[0215] The in Fig. The illustrated procedure in section 64 applies to the positive half-wave of the input voltage. During the negative half-wave, the procedure differs from the one in section 64. Fig. The method described in 64 is achieved by calculating F based on the absolute value of the modulation index (which is negative during the negative half-wave) and by using F converter cells at a modulation index m i =-1 can be operated.

[0216] During one half-cycle of the input voltage V IN The converter cells are either equipped with m i =1 (or -1) or m i=0. The sign of the modulation index m0 of filter cell 10 can vary; that is, the modulation index m0 can be positive or negative during a half-cycle. During the positive half-cycle, when the modulation index m0 is positive, filter cell 10 receives power from inputs IN1 and IN2. When the modulation index m0 is negative, filter cell 10 supplies power to the series connection with converter cells 11-1. N1During the negative half-cycle, a positive modulation index m0 indicates that filter cell 10 is delivering power, and a negative modulation index m0 indicates that filter cell 10 is receiving power. Thus, the filter cell receives power (is in input power mode) when the sign of the modulation index m0 is the same as the sign of the total modulation index m, and delivers power (is in output power mode) when the signs are different. Essentially, the average power that filter cell 10 delivers in one half-cycle of the input voltage V is... IN receives zero, so that the voltage V20 across the capacitor 110 oscillates around a certain voltage level, such as zero.

[0217] For example, during the positive half-cycle, the modulation index is positive if the sum of the cell output voltages of the F converter cells that are in the off state is less than the level of the input voltage, and is negative if the sum of the cell output voltages of the F converter cells that are in the off state is greater than the level of the input voltage V. IN During the negative half-cycle, the modulation index is negative if the sum of the cell output voltages of the F converter cells that are in the off state is less than the (absolute value of the) level(s) of the input voltage, and is positive if the sum of the cell output voltages of the F converter cells that are in the off state is greater than the (absolute value of the) level(s) of the input voltage V. IN .

[0218] Fig. 65 illustrates the operation of the in Fig. 60 first power converter 10 shown during a control cycle (which has a duration T) pexhibits). In the exemplary embodiment, two of the converter cells are present for the entire duration T. p of the control cycle in the off state and two of the converter cells are during the entire duration of the control cycle T p in the on state. Filter cell 10 is operated in a clocked manner based on the modulation index m0 (where the duty cycle d0 is given by d0=1-m0).

[0219] Referring to the foregoing, the converter cells can be operated in block mode. However, it is also possible to operate the multi-cell converter in such a way that a group of converter cells in the off state and, correspondingly, another group of converter cells in the on state alternate from drive cycle to drive cycle. It is also possible to operate the same converter cells in the off state and the same converter cells in the on state until the modulation index m0 of filter cell 10 is recalculated. In this way, the DC link capacitors are charged more evenly.

[0220] Fig. Figure 66 shows an embodiment of a second power converter 20, which includes a filter cell 20. As shown in Fig. Filter cell 10, as shown in Figure 60, comprises one connection. The connection of filter cell 20 is in series with the cell outputs of converter cells 21-2. N3switched. The series connection with the connection of the filter cell 20 and the cell outputs of the converter cells 21-2. N3 is connected to outputs OUT1 and OUT2. So that the in Fig. 66 shown representation with the in Fig. The representation shown in 60 is consistent with the fact that a capacitor of filter cell 20, as shown in Fig. Capacitor 60, labeled 110. V20 is the voltage across the capacitor of filter cell 20. The operation of the in Fig. Filter cell 20 shown in 66 corresponds to the operation of the one in Fig. 60 filter cells shown, with the difference that the one in Fig. 66 The filter cell 20 shown provides a voltage V30, which contributes to a total cell output voltage V3. TOT the converter cells are added.

[0221] Fig. Figure 67 shows an embodiment of the filter cell 20. The full-bridge topology of this filter cell 20 corresponds to the topology of the one in Fig. 34 converter cell 2 shown i However, a topology with only one half-bridge can also be used. This is just to illustrate that filter cell 20 differs from converter cell 2. i The distinction was made by adding a subscript "0" to the reference symbols of the individual components of filter cell 20. The operation of filter cell 20 corresponds to the operation of converter cell 2. i . That is, a controller 2330 of the filter cell 20 receives a modulation index m0 and controls a first half-bridge 2310 and a second half-bridge 2320 with a duty cycle calculated based on the modulation index m0.

[0222] Fig. Figure 68 shows an embodiment of a main controller 5 in which the following is located: Fig. 66 shown second power converter 20. This main controller 5 is based on the one in Fig. The main controller shown in section 35 differs from the one in Fig. 35 main controller 5 shown in the illustration by additionally comprising a converter and filter cell controller 54, which receives the modulation index m from the modulation index controller 52 and the modulation index m0 of the filter cell 20 and modulation indices m1-m N3 the individual converter cells 21-2 N3 provides Fig. 68 converter and filter cell controllers shown; 54 works like the one in Fig. 62 converter and filter cell controllers 44, which are referenced. A difference between the one in Fig. 68 converter and filter cell controllers shown and the one in Fig. The converter and filter cell controller shown in section 62 consists in the fact that the one in Fig. 68 converter and filter cell controllers shown, the modulation indices m0-m N3 based on the total cell output voltage V3 TOT instead of the total cell input voltage V1 TOT generated.

[0223] Fig. 69 shows an embodiment of a method which is described in Fig. The converter and filter cell controller 54 shown in Figure 68 can be implemented. This method includes determining the number F of converter cells to be operated in the off state by F=Round[m⋅N3] That is, by calculating the product of the modulation index m and the number N3 of converter cells and rounding the result (1061). Then the modulation index m0 is calculated similarly to the calculation of the modulation index m0 in the Fig. The 64 methods shown are calculated, with the difference that the modulation index m0 is used in the method shown. Fig. The method shown in Figure 69 is calculated based on the desired cell output voltage V30 of filter cell 20 (instead of the desired cell input voltage V10). The desired cell output voltage V30 of filter cell 20 is V30=m⋅V2TOT−F1⋅V2TOTN3 and the modulation index m0 = V30 / V20. The converter and filter cell controller 54 then operates the filter cell 10 at the modulation index m0, and the converter cells at a modulation index m i =1 and N3-F converter cells at a modulation index m i =0.

[0224] The in Fig. The time diagrams shown in 63 apply to the one in Fig. The parameters of the second power converter 20 are shown in Figure 66. Fig. 63 is given in parentheses. Filter cell 20 delivers power to output Out1, OUT2 (is in output line operation) when the modulation index m0 has a sign equal to the sign of the total modulation index m, and receives power (is in input line operation) when the signs are different. The signs are the same when the sum of the cell input voltages of the converter cells that are in the off state is lower than the instantaneous level of the output voltage, and the signs are different when the sum of these voltages is higher than the instantaneous level of the output voltage.

[0225] Another degree of freedom offered by a multi-cell converter topology is the type of connection between the individual converter cells. In the previously described embodiments, the inputs of the converter cells of a multi-cell converter are connected in series (IS topology) or parallel (IP topology), or the outputs are connected in series (OS topology) or parallel (OP topology). According to one embodiment, the multi-cell converter comprises at least two converter cells, where the type of connection between the two converter cells can alternate between a parallel connection and a series connection. That is, these two converter cells are either connected in series or in parallel. This is demonstrated for two converter cells of a first multi-cell power converter 10 by means of the Fig. 70-73 and for two converter cells of a second multi-cell power converter 20 based on the Fig. Explained on pages 73-75.

[0226] In Fig. 70 designates the reference numerals 1 k and 1 k+1 two converter cells of the first power converter 11. 11 k , 11 k+1 designate the associated intermediate circuit capacitors and V2 k , V2 k+1 These denote the associated intermediate circuit voltages. Each of the converter cells l k , 1 k+1 It comprises a cell input with a first cell input node and a second cell input node. A switching arrangement 7 is connected between the cell inputs of the converter cells l. k , 1 k+1 The switching arrangement 7 comprises a first switch 71, which is connected between a first cell input node of the converter cell 1. k+1 and a second cell input node of converter cell 1 k is switched. A second switch 72 is located between a first cell input node of the first converter cell 1. kand the first cell input node of converter cell 1 k+1 switched. A third switch 73 is connected between a second cell input node of converter cell 1. k and the second cell input node of converter cell 1 k+1 switched. The cell inputs of the converter cells 1 k , 1 k+1 They are connected in series when the first switch 71 is on and when the second and third switches are off. In this case, the second cell input is of converter cell 1. k to the first cell input of converter cell 1 k+1 connected. The cell inputs of the two converter cells 1 k , 1 k+1 are connected in parallel when the first switch 71 is off and when each of the second and third switches 72, 73 is on. In this case, the first cell input node of converter cell 1 k at the first cell input node of converter cell 1 k+1connected and the second cell input node of converter cell 1 k is at the second cell input node of converter cell 1 k+1 connected.

[0227] As through the in Fig. As indicated by the 70 dotted lines shown, the multi-cell power converter can, in addition to converter cells 1 k , 1 k+1 further converter cells are included. The ones in Fig. 70 converter cells shown 1 k , 1 k+1 They can be arranged in various ways within the multi-cell converter. According to one embodiment, the cell input node of converter cell 1 is k connected to the first input node IN1 of the multi-cell converter 10 and at least one further converter cell is between the second cell input nodes of converter cell 1 k+1and the second input node IN2 of the multi-cell converter 10 is connected. According to one embodiment, two or more converter cells are connected between converter cell 1. k+1 and the second input node IN2 connected, wherein the cell inputs of these two or more converter cells are connected in series between the second cell input node of converter cell 1 k+1 and the second input node IN2 is connected. According to a further embodiment, the second cell input node of the converter cell 1 is k+1 connected to the second input node IN2 of the multi-cell converter 10 and at least one further converter cell is located between the first cell input nodes of converter cell 1 k and the first input IN1 is connected. According to one embodiment, two or more converter cells are connected between the first input node IN1 and the first cell input node of converter cell 1. kconnected, wherein the cell inputs of these two or more converter cells are connected in series. According to a further embodiment, two or more converter cells are connected between each input IN1, IN2 and the converter cells 1. k or 1 k+1 switched on.

[0228] Furthermore, each of the two converter cells comprises 1 k , 1 k+1 a coil (which is in Fig. 70 is not shown, but was previously explained using different converter cell topologies).

[0229] According to one embodiment, the in Fig. 70 converter cells shown 1 k , 1 k+1 (and the other converter cells that are in Fig. 70 are not shown) one of the based on the Fig. 12 and Fig. 24 converter topologies were explained (upshift topology or full bridge topology).

[0230] Fig. 71 shows one way to operate the in Fig. 70 multi-cell power converter 10. In this embodiment, the type of connection between converter cell 1 is k and the converter cell 1 k+1 depending on the instantaneous voltage level of the input voltage V IN If the voltage level of the input voltage V IN For example, if the voltage is below a threshold V1, the two converter cells 1 k , 1 k+1 connected in parallel. In Fig. 71 is represented by an on level (high level) of the control signals S72, S73 of the second and third switches 72, 73 and an off level (low level) of a control signal S71 of the first switch 71. An on level of one of the control signals S71-S73 indicates that the respective switch is in the on state, or an off level indicates that the respective switch is in the off state. When the voltage level of the input voltage V INAbove the voltage threshold V1, the converter cells are 1 k , 1 k+1 connected in series. Fig. 71 this is represented by an off level of the control signals S72, S73 of the second and third switches 72, 73 and an on level of the control signal S73 of the first switch 71.

[0231] Each of the converter cells 1 k , 1 k+1 It can be operated in an on-state and an off-state. In the on-state, the cell input voltage V1 is k , V1 k+1 Each converter cell is essentially zero. If the converter cells are 1 k , 1 k+1 When connected in series, the total cell input voltage V1 is k_k+1 the converter cells 1 k , 1 k+1 0 (zero), V2 k , V2 k+1 or V2 k +V2 k+1 depending on which of the two converter cells 1 k , 1 k+1 is in the on state or in the off state. If the two converter cells 1k , 1 k+1 When connected in parallel, the total cell input voltage V1 k_k+1 Zero if both converter cells are 1 k , 1 k+1 are in the ON state. If both converter cells are 1 k , 1 k+1 When in the off state (and the converter cells are implemented with a full bridge topology), the total cell input voltage V1 k_k+1 depending on the voltage V2 k , V2 k+1 about the intermediate circuit capacitors 11 k , 11 k+1 If these voltages are equal (V2) k =V2 k+1 ) corresponds to the voltage level of the total cell input voltage V1 k_k+1 the voltage level of the intermediate circuit voltages V2 k , V2 k+1 If these voltages V2 k , V2 k+1Since the voltages are not equal, a charge equalization can occur such that electrical charge is transferred from the intermediate circuit capacitor with the higher voltage to the intermediate circuit capacitor with the lower voltage, until these voltages are balanced to such an extent that the voltage levels of these two voltages V2 k , V2 k+1 are equal. The voltage level of the total cell input voltage V1 k_k+1 then equals the voltage level of the balanced intermediate circuit voltages V2 k , V2 k+1 .

[0232] Referring to the foregoing, the maximum level of the total cell input voltage V1 is k_k+1 , if the converter cells 1 k , 1 k+1 are connected in parallel, lower than the maximum level of the total cell input voltage V1 k_k+1 , while the converter cells 1 k , 1 k+1 are connected in series. If the input voltage V INIf the voltage is below the threshold V1, the lower cell input voltage (in conjunction with the cell input voltages of the other converter cells) may be sufficient to compensate for the voltage level of the input voltage V. IN to follow, while a higher cell input voltage may be necessary if the voltage level of the input voltage V IN above the threshold V1.

[0233] Connecting the two converter cells in parallel 1 k , 1 k+1 , if the input voltage V IN Being below the voltage threshold V1 can be advantageous at a high level of converted power. If the input current I IN for example, relatively high, even before the input voltage V IN When the voltage threshold V1 is reached, such that the input power of a converter cell is higher than the power at which the converter cell might have its maximum efficiency, two converter cells connected in parallel can be used.k , 1 k+1 This input power is divided so that each of these converter cells operates at an efficiency higher than the efficiency of a single converter cell converting the input power. Operating two converter cells connected in parallel at a power level that is only 50% of the maximum power can be more efficient than operating only one converter cell at the maximum power.

[0234] Fig. Figure 72 shows an embodiment of a main controller 4 configured to control the converter cells in the Fig. to control the 70 multi-cell power converters 10 shown. This main controller 4 is based on the one in Fig. The main controller shown in 13 is 4 and differs from the one in Fig. The main controller shown in Figure 13 is distinguished by the fact that it additionally includes a switch controller 45. This switch controller 45 receives the input voltage signal V. IN_Mand is designed to control the individual switches 71-73 of the switching circuit 7 depending on a voltage level of the input voltage V IN to operate. The switch controller 45, which generates the control signals S71-S73 for switches 71-73, can operate switches 71-73 as shown in Fig. 71 shown, operate. That is, the switch controller 54 can operate the switches 71-73 in such a way that the cell inputs of the converter cells 1 k , 1 k+1 are connected in parallel when a voltage level of the input voltage V IN below the threshold V1, and are connected in series when the voltage level of the input voltage V IN above the threshold V1. The one in Fig. The main controller 4 shown in Figure 72 is configured to operate the individual converter cells of the multi-cell converter 10 with the same modulation index m. However, it is also possible to operate the individual converter cells with different modulation indices.

[0235] According to one embodiment, the main controller 4 is configured to control the two converter cells 1 k , 1 k+1 to connect in series and only one of the converter cells 1 k , 1 k+1 to operate when the level of the input voltage V IN below a second threshold, which is lower than the first threshold V1, the two converter cells 1 k , 1 k+1 to connect in parallel if the level of the input voltage V IN below the second and third thresholds, and the converter cells 1 k , 1 k+1 to be switched back into series when the level of the input voltage V IN above the first threshold. “Operating only one converter cell” of the two parallel converter cells is equivalent to regulating the input current of one of the two converter cells so that it is zero.

[0236] Although the in Fig. Although the multi-cell converter 10 shown in Figure 70 is drawn such that it has only two converter cells whose inputs can be connected in parallel or in series, the multi-cell converter 10 is not limited to having only two of these rearrangeable converter cells. "Rearrangeable" converter cells are converter cells whose cell inputs are connected either in parallel or in series by a switching circuit. According to one embodiment, the converter cell 10 comprises further rearrangeable converter cells. This can be achieved by providing a switching circuit of the Fig. 70 of the type shown between two other than those in Fig. 70 converter cells shown 1 k , 1 k+1 It is also possible to use a switching arrangement of the in Fig. 70 of the type shown between one of the converter cells 1 k , 1 k+1and to provide a further converter cell (not shown). In this case, an arrangement of converter cells is obtained in which two or three converter cells can be connected in parallel. According to one embodiment, in a multi-cell converter 10 with N1 converter cells, there are N1-1 switching arrangements, such that a switching arrangement is present between each pair of two adjacent converter cells. In this embodiment, up to N1 converter cells can be connected in parallel.

[0237] At the in Fig. In the illustrated embodiment 70, there are two converter cells 1 k , 1 k+1 which can be connected in parallel. According to another embodiment, each of the two converter cells is replaced by a series connection (a string) of two or more converter cells. In this embodiment, the two strings are selected based on the signal level of the input voltage V. INconnected in parallel or in series, whereby the criteria for connecting in series or parallel can be the same as above using the two converter cells 1. k , 1 k+1 explained.

[0238] Fig. Figure 73 shows an embodiment of a second power converter 20, which has two converter cells 2 k , 2 k+1 features that can be rearranged. Each of these converter cells 2 k , 2 k+1 comprises a cell output with a first cell output node and a second cell output node. A switching arrangement 8 with a first switch 81, a second switch 82 and a third switch 83 is connected between the cell outputs of the two converter cells 2. k , 2 k+1 such that a first switch 81 is connected between a second cell output node of the converter cell 2 k and a first cell output node of converter cell 2 k+1A second switch 82 is connected between the first cell output nodes of converter cell 2. k and the first cell output node of converter cell 2 k+1 is switched, and a third switch 83 is located between the second cell output nodes of converter cell 2 k and the second cell output node of converter cell 2 k+1 is switched. The cell outputs of the converter cells 2 k , 2 k+1 are connected in series when the first switch 81 is switched on and the second switch 82 and the third switch 83 are each switched off, and the cell outputs are connected in parallel when the first switch 81 is switched off and the second switch 82 and the third switch 83 are each switched on.

[0239] In Fig. 73 denotes 11 k , 11 k+1 the intermediate circuit capacitors that are connected to the cell inputs of the converter cells 2 k , 2 k+1 are switched, and V3k , V3 k+1 denote cell output voltages of the two converter cells 2 k , 2 k+1 . A (in Fig. 73 (not shown) power converter, which supplies power to the intermediate circuit capacitors 11 k , 11 k+1 The power converter supplied can have one of the converter topologies previously explained using the first power converter as an example. That is, the first power converter, which supplies power to the in Fig. 73 intermediate circuit capacitors shown 11 k , 11 k+1 delivers is not necessarily a first power converter with converter cells that can be rearranged, although it may have converter cells that can be rearranged.

[0240] According to one embodiment, the type of connection between the cell outputs of the two converter cells 1 is k , 1 k+1 depending on a voltage level of the output voltage V OUTAccording to one embodiment, the output voltage V OUT defined by an external voltage source, such as a power grid. In this case, the multi-cell converter 20 delivers the output power "against" the output voltage V defined by the external voltage source. OUT .

[0241] A possible operation of the in Fig. The multi-cell converter 20 shown in 73 is in Fig. 74 shown. Fig. 74 shows the voltage level of the output voltage V OUT during one half-cycle of a sinusoidal output voltage. Referring to Fig. 74 can be the cell outputs of the converter cells 2 k , 2 k+1 They can be connected in parallel if the voltage level of the output voltage is below a voltage threshold V2, and can be connected in series if the voltage level of the output voltage V OUTabove the voltage threshold V2. A parallel connection of the converter cells 2 k , 2 k+1 A series connection of the cell outputs is represented by the on level (high level) of the control signals S82, S83 of the second switch 82 and the third switch 83 and an off level (low level) of a control signal S81 of the first switch 81.

[0242] In Fig. 73 designates V3 k_k+1 a total cell output voltage of the two converter cells 2 k , 2 k+1 If the converter cells 2 k , 2 k+1 When connected in series, the total cell output voltage V3 k_k+1 same as V2 k (if 2 k in the off state and 2 k+1 (in the on state), V2 k+1 (if 2 kis in the on state and 2 k+1 (is in the off state) and V2 k +V2 k+1 (if both 2 k as well as 2 k+1 (is in the off state). If the converter cells 2 k , 2 k+1 When connected in parallel, the total cell output voltage V3 k_k+1 a balanced voltage level. The balanced voltage level is the voltage level obtained by balancing the charge between the two intermediate circuit capacitors 11. k , 11 k+1 , if both converter cells 2 k , 2 k+1 are in the off state.

[0243] As with the one in Fig. 70 of the power converters shown, there is a coil (in Fig. 73 not shown) in each of the converter cells 2 k , 2 k+1 Furthermore, other converter cells of the multi-cell converter 20 are in Fig. 73 not shown. These converter cells can be placed between converter cells 2. kand the output node OUT1, between converter cell 2 k+1 and the second output node OUT2. Alternatively, one or more converter cells can be connected between each of the converters 2. k and 2 k+1 and each of the output nodes OUT1, OUT2 be switched.

[0244] Fig. Figure 75 shows an embodiment of a main controller 5, which is configured to control the operation of the in Fig. to control the second power converter 20 shown in figure 73. The one in Fig. 75 main controllers shown 5 are based on the one in Fig. The main controller shown in section 35 differs from the one in Fig. The main controller shown in Figure 35 is distinguished by the fact that it additionally includes a switch controller 55, which controls the control signals S81, S82, S83 of the individual switches in the Fig. The switching arrangement 8 shown in 73 is generated. The switch controller 55 can be configured to control these switches 81-83 according to the arrangement shown in 73. Fig. to generate the embodiment shown in figure 74 such that the switching arrangement 8 controls the cell outputs of the converter cells 2 k , 2 k+1 switches in series when a voltage level of the output voltage V OUT above the threshold V2, and to connect the cell outputs in parallel if the voltage level of the output voltage V2 is below the threshold.

[0245] Referring to the Fig. 71 and Fig. 74 will be the reconfigurable converter cells 1 k , 1 k+1 or 2 k , 2 k+1 , in the in the Fig. 70 and Fig. 73 multi-cell converters shown 10, 20 twice in each half-wave of the input voltage V IN or the output voltage V OUT rearranged. In the Fig. 71 and Fig. In the exemplary embodiments shown in 74, the type of connection changes from a parallel circuit to a series circuit when the respective voltage exceeds a threshold (V1, V2 in the Fig. 71 and Fig. 74) increases, and from a series circuit back to a parallel circuit when the respective voltage drops below the threshold.

[0246] The Fig. 76A and Fig. Figure 76B shows a possible operation of a first power converter 10 with an IP topology. Fig. 76A illustrates a power level of the input power P IN (if the input power is AC power, P IN denotes the average input power in one period of the input voltage V. IN ) and the proportions of the input power P IN , which the individual converter cells 11-1 N1received. For illustrative purposes only, let us assume that the power converter N1=3 comprises converter cells, where P IN1 , P IN2 , P INN1 denote the input power of the individual converter cells, and P IN1_REL =P IN1 / P IN , P IN2_REL =P IN2 / P IN , P INN1_REL =P IN3 / P IN denotes the proportion of the individual converter cells, whereby PIN=∑i=1N1PINi_REL=100% where P INi_REL to denote the input power shares of the individual converter cells, and in this embodiment N1=3.

[0247] Referring to Fig. 76A are the input power components P IN1_REL -P INN1_REL of the individual converter cells 11, 1 N1 depending on the power level of the input power P IN , which is between a maximum level P IN_MAX and a minimum level P IN_MIN can vary. In the case of the Fig. In the embodiment shown in 76A, the converter cell 11 has at the maximum level P IN_MAX the highest proportion, converter cell 1 N1 has the lowest proportion, and converter cell 12 has a proportion that is lower than that of converter cell 11, but higher than that of converter cell 1. N1 At the lowest level P IN_MIN (which differs from zero) converter cell 11 has the lowest proportion, converter cell 1 N1 has the highest proportion, and converter cell 12 has a proportion that is lower than that of converter cell 1. N1 but higher than that of converter cell 11. In Fig. 76A illustrates the dashed line as the input power share of a converter cell in a power converter, in which the individual converter cells receive equal shares of the input voltage regardless of the level of the input power P. INThese proportions depend on the number of converter cells. In a power converter with N1=3 converter cells, each converter cell receives 33.33% (= 1 / N1) of the input power P. IN .

[0248] At the in Fig. In the embodiment shown in 76A, the distribution of the input power components is independent of the input power level if the input power level is between the maximum level P IN_MAX and a first level P IN_1 is, where for example P IN1_REL =60%, P IN2_REL =30%, P INN1_REL =10%. If the input power level falls below the first level P IN_1 As the input power level decreases, the proportion of converter cell 11 decreases, while the proportion of converter cell 1 N1 increases. If the input power level falls below a second level P IN_2 drops, which is lower than the first level P IN_1, the proportion of converter cell 12 decreases when the input power level decreases, while the proportion of converter cell I N1 continues to rise. If the power level between a third level P IN_3 , which is lower than the second level P IN_2 , and the minimum level P IN_MIN If the distribution of input power components is independent of the input power level, for example P IN1_REL =10%, P IN2_REL =15%, P INN1_REL =75%.

[0249] The in Fig. The distribution of power components at the individual input power levels shown in Figure 76A is only one example. While in the Fig. In the embodiment shown in Figure 76A, where each of the converter cells changes its input power share when the input power level decreases, it is also possible to have only two converter cells that change their input power shares and to keep the input power shares of the other converter cell(s) essentially constant.

[0250] According to one embodiment, the individual converter cells 11-1 N1 trained to accept a DC voltage as input voltage V IN to obtain. In this case, the input power of the individual converter cells can be adjusted by setting the respective input currents I01-I0. N1 be hired. Fig. Figure 76B illustrates the distribution of the input currents I01-I0 N1 depending on the power level of the input power. Referring to Fig. 76B takes the input current I IN linearly decreases when the power level of the input power deviates from the maximum level P. IN_MAXto the minimum level P IN_MIN decreases. The individual input currents I01-I0 N1 However, they do not decrease linearly across the entire input power range. There can even be regions where the input current of a converter cell is essentially constant or increases as the power level decreases. In the case of the Fig. In the embodiment shown in 76, for example, the input current I0 N1 converter cell 1 N1 to, if the input power level is between the second level and the third level P IN_2 and P IN_3decreases. In general, the ability of the power converter to distribute the input power shares of the individual converter cells unequally can be used to keep the input power level (input current level) of at least one converter cell within a predefined power range (current range) in which the respective converter cell has a high efficiency, that is, for example, an efficiency higher than 60% or higher than 80% of the maximum efficiency.

[0251] In Fig. 76B designates I01-I0 N1 The average input currents of the individual converter cells. This means that the power converter can operate in phase-shedding mode or intermittent mode when the input power level drops. In this case, there can be periods in which the instantaneous current level of one or more of the input currents I01-I0 N1 It becomes zero.

[0252] Fig. Figure 77 shows an embodiment of a main controller 6 configured to control the individual converter cells 11-1 N1 in the based on the Fig. 76A and Fig. 76B to control in the manner explained. The one in Fig. 77 Main controllers 6 shown are based on the one in Fig. 39 main controller 6 and differs in that it has a power distribution controller 64 which is configured to measure the input current reference signals I0 1_REF -I0 N1_REF to generate the individual converter cells based on a desired input power level. The power distribution controller can determine the desired input power level based on the input current reference signal I. IN _ REF (which is calculated by the input voltage controller 61, can be obtained from a central controller or by an MPP tracker) and the input voltage signal V IN_MAccording to another embodiment, the power distribution controller 64 generates the input current reference signals I0 1_REF -I0 N1_REF based solely on the input current reference signal I IN_REF .

[0253] The power distribution controller 64 is designed to measure the input current reference signals I0 1_REF -I0 N1_REF to generate such that the (average) input currents I01-I0 N1 the individual converter cells as before based on the Fig. 76A and Fig. Section 76B explains how this can be regulated. The power distribution controller 64 can additionally have a phase shedding functionality. This means that the power distribution controller can alternately operate one or more of the converter cells in active and inactive mode in order to regulate the input current of the respective converter cell.

[0254] This is based on one of the Fig. 76A and Fig. The method described in Section 76B, in which the input power is unequally distributed among the individual converter cells, is not limited to use in a power converter with an IP topology, such as one of the previously described power converters with an IP topology. Instead, this type of operation can also be used in a multi-cell converter with an OP topology, such as the one described in Section 76B. Fig. 31 multi-cell converters are used. That is, a multi-cell converter with an OP topology can be configured to distribute the input power components to the individual converter cells 21-2. N3 based on a power level of the output power P OUT to vary. In the Fig. 76A and Fig. 76B shows the output power components and output currents that occur in an operational converter, indicated in parentheses. Here, P denotes OUT1_REL =P OUT1 / P OUT , P OUT2_REL =P OUT2 / P OUT , P OUTN3_REL =P OUTN3 / P OUT denote the proportions of the individual converter cells, whereby POUT=∑i=1N3POUTi_REL=100%.

[0255] Fig. Figure 78 shows an embodiment of a main controller 3 configured to control the individual converter cells 21-2 N3 based on one of the Fig. 76A and Fig. 76B to control in the manner explained. The one in Fig. 78 Main controller 3 shown is based on the one in Fig. 33 main controller 3 shown and differs in that it includes a power distribution controller 34 which is designed to control the output current reference signals I2 1_REF -I2 N3_REF to generate the individual converter cells based on the desired input power level. The power distribution controller 34 can generate the desired output power level based on the output current reference signal I. OUT_REF(which can be calculated by the output voltage controller 31 or obtained from a central controller) and the output voltage signal V OUT_M calculated. According to another embodiment, the power distribution controller 34 generates the output current reference signal I2. 1_REF -I2 N3_REF based solely on the output current reference signal I OUT_REF .

[0256] The power distribution controller 34 is designed to measure the output current reference signal I2. 1_REF -I2 N3_REF to generate such that the (average) output currents I21-I2 N3 the individual converter cells as before based on the Fig. 76A and Fig. Section 76B explains how this can be regulated. The power distribution controller 34 can additionally have a phase shedding functionality. This means that the power distribution controller can alternately operate one or more of the converter cells in active and inactive mode in order to regulate the input current of the respective converter cell.

[0257] In an IP or OP multi-cell converter, which, according to the specifications in the Fig. 76A and Fig. The procedure illustrated in 76B works, the individual converter cells 11-1 N1 (21-2 N3 ) with regard to losses that may occur, they can be implemented differently. Each type of converter cell described above includes at least one electronic switch. According to one embodiment, the individual converter cells 11-1 N1 (21-2 N3) are designed differently with regard to line losses. According to one embodiment, this is achieved by designing the at least one electronic switch in at least two of the converter cells 11-1 N1 (21-2 N3 ) with different on-resistances (R ONThe on-resistance of an electronic switch is the electrical resistance that the electronic switch exhibits in the on-state (switched-on) condition. For example, the on-resistance of a MOSFET, when used as an electronic switch, is the electrical resistance between a drain node (D) and a source node (S) of the MOSFET in the on-state. A MOSFET can be designed to have multiple transistor cells connected in parallel. In this case, the on-resistance is essentially proportional to the number of transistor cells, and thus proportional to the area that the MOSFET occupies on a semiconductor chip. When designing a MOSFET, the on-resistance can be adjusted by appropriately selecting the number of transistor cells connected in parallel.In a GaN-HEMT, as another example of an electronic switch, the on-resistance can be adjusted by appropriately selecting a channel width during the design of the component.

[0258] For example, it is assumed that in a multi-cell converter that, according to the Fig. 76A and Fig. 76B is operating, four converter cells are present, one converter cell is optimized for "low load conditions" (corresponding to cell 1). N1 (2 N3 ) in the Fig. 76A and Fig. 76B), a converter cell optimized for “medium load conditions” (corresponding to cell 12 (22) in the Fig. 76A and Fig. 76B), and a converter cell optimized for “high load conditions” (corresponding to cell 11 (21) in the Fig. 76A and Fig. 76B). In this case, at least one electronic switch is located in low-load cell 1. N1 (2 N3) designed so that it has the highest on-resistance, which is subsequently referred to as the first on-resistance R ON1 is designated as having at least one electronic switch in the intermediate load cell 12 (22) designed such that it has a second on-resistance R ON2 , which is lower than the first on-resistance R ON1 , possesses, and the at least one electronic switch in the high-load cell 12 (21) is designed such that it has a third on-resistance R ON3 possesses a resistance that is lower than the second switching resistance R ON2 . That means, RON1>RON2>RON3.

[0259] A ratio R ON1 :R ON2 :R ON3 For example, 1:0.5:0.1. That means the first on-resistance R ON1 is twice the value of the second on-resistance R ON2 and 10 times the third on-resistance R ON3This is, of course, only one example. The ratio of the individual on-resistances can vary widely. Furthermore, not all on-resistances of the converter cells are necessarily different. That is, at least one electronic switch in two or more converter cells can be implemented with essentially the same on-resistance. However, there are at least two converter cells that are implemented with different on-resistances. That is, the on-resistance of the at least one electronic switch in one converter cell differs from the on-resistance of the at least one electronic switch in the other converter cell. "Differs" means that the on-resistance in one converter cell is less than 80% of the on-resistance in the other converter cell.

[0260] If the individual converter cells of the multi-cell converter are implemented with multiple electronic switches, such as two switches in a boost topology, four switches in a full-bridge topology, or eight switches in a DAB topology, there will be at least two converter cells in which two corresponding electronic switches have different turn-on resistances. "Corresponding" means that the electronic switches have the same position and function in the respective topology. For example, in converter cells with a boost topology using a half-bridge (as in...) Fig. (As shown in Figure 12), the high-side switch in one converter cell can have an on-resistance that differs from the on-resistance of the corresponding high-side switch in the other converter cell. If the multi-cell converter is implemented with converter cells that have multiple electronic switches, there can be other electronic switches that have essentially the same on-resistance in each converter cell.

[0261] Another degree of freedom of a multi-cell converter topology is provided by the ratio between the individual intermediate circuit voltages V21-V2. N2In the previously described embodiments, it was assumed that the individual DC link voltages have essentially the same voltage level. However, this is only one example. According to one embodiment, a multi-cell converter with an IP or IS topology is configured to regulate the DC link voltages at the cell outputs such that they have at least two different voltage levels. "Different" means that the voltage level of one group of DC link voltages is less than 80% of the voltage level of another group of DC link voltages, each group comprising at least one of the previously described DC link voltages. According to another embodiment, a multi-cell converter with an OP or OS topology is configured to regulate the DC link voltages at the cell inputs such that they have at least two different voltage levels.“Different” means that the voltage level of one group of DC link voltages is less than 80% of the voltage level of another group of DC link voltages, with each group including at least one of the previously explained DC link voltages.

[0262] Since – referring to the explanation above – in a multi-cell converter with an IP or OP topology each converter cell can be configured to regulate its associated DC link voltage, different DC link voltage levels can be achieved by setting the DC link voltage reference signals in the individual converter cells to different levels. For example, in the Fig. The IP topology shown in 29 can have different intermediate circuit voltages V21-V2. N1This is obtained by setting the DC link voltage reference signal in the controller 41 of converter cell 11 and in the controllers (not shown) of the other converter cells to different values. The DC link voltage reference signal of controller 41 is the one in Fig. 30 displayed signal V2 1_REF . This signal and the corresponding signals from the other controllers can be provided by a central controller (not shown in the drawings).

[0263] Generating DC link voltages with different voltage levels is not limited to IP and OP topologies. According to one embodiment, a multi-cell converter with an IS topology is configured to generate DC link voltages V21-V2. N2 to generate different voltage levels at the cell outputs. A possible operation of such a multi-cell converter with an IS topology is shown below. Fig. 79A andFig. 79B explained. Fig. 79A and Fig. Figure 79B shows timing diagrams of a half-wave of a sinusoidal input voltage or a full-wave of a rectified sinusoidal input voltage and timing diagrams of the total cell input voltage V1. TOT For the purpose of explanation, let us assume that the multi-cell converter comprises three converter cells that generate different intermediate circuit voltages V21, V22, V23 at their respective cell outputs. In this embodiment, V21 > V22 > V23.

[0264] The multi-cell converter can be implemented with a topology such as that described in Fig. As shown in Figure 12 (when N1=3), the individual converter cells can have either a boost topology (if the input voltage is a rectified sinusoidal voltage) or a full-bridge topology (if the input voltage is a sinusoidal voltage). The various intermediate circuit voltages V21, V22, V2 are described below. N1These are referred to as the first, second, and third DC link voltages. The converter cells that supply these DC link voltages are referred to as the first, second, and third converter cells.

[0265] In the Fig. 79A and Fig. In the embodiments shown in 79B, the first, second, and third converter cells are operated in block mode. That is, based on the instantaneous level of the input voltage V IN Only one of the converter cells is operated using pulse-width modulation. The other converter cells are either in the on state or in the off state. In the case of the Fig. In the embodiment shown in 79A, the first converter cell operates in pulse-width modulation when the level of the input voltage V IN Between 0 and the level of the first intermediate circuit voltage V21, the other two converter cells are in the on state. When the level of the input voltage V INWhen the level of the first intermediate circuit voltage V21 rises above this level, the second converter cell begins to operate in pulse-width modulation mode; the first converter cell is in the off state and the second converter cell is in the on state. When the level of the input voltage V IN When the input voltage rises above a level equal to the level of the first DC link voltage V21 plus the level of the second DC link voltage V22, the third converter cell begins to operate in pulse-width modulation mode. The first converter cell and the second converter cell are in the off state. The modulation indices of the three converter cells are based on the voltage level of the input voltage V. IN are shown below in Table 1: Table 1 0 < |V IN | ≤ V21 V21 < |V IN |≤ V21+V22 V21+V22 ≤ |V IN| | m1 In IN / V21 1 1 m2 0 (V IN -V21) / V22 1 m3 0 0 (V IN -V21-V22) / V23

[0266] Table 1 shows V IN the instantaneous level of the input voltage, |V IN| is the absolute value of the instantaneous level of the input voltage, V21 is the level of the first intermediate circuit voltage, V22 is the level of the second intermediate circuit voltage and V23 is the level of the third intermediate circuit voltage.

[0267] After the level of the input voltage V IN Once the maximum level has been reached and is decreasing, the third converter cell is switched to the on state, in which the cell input power is essentially zero, then the second converter cell is switched to the on state, in which the cell input power is essentially zero, and finally, when the input voltage drops to zero, the first converter cell is switched to the on state, in which the cell input power is essentially zero.

[0268] The order in which the converter cells begin to convert power when the level of the input voltage V IN The increase is arbitrary. In the case of the Fig. In the embodiment shown in 79A, the first converter cell begins, followed by the second converter cell, which is followed by the third converter cell. However, other sequences are also possible. In the embodiment shown in Fig. In the embodiment shown in 79B, the third converter cell begins and operates in pulse-width modulation until the level of the input voltage V IN When the level of the third intermediate circuit voltage V23 is reached, the second converter cell operates in pulse-width modulation until the level of the input voltage V INThe level of the third DC link voltage V23 plus the level of the second DC link voltage is reached, and finally the first converter cell operates in pulse-width modulation mode. According to one embodiment, the sequence in which the converter cells begin to convert power differs in different half-waves (or full-waves). According to another embodiment, the sequence in which the converter cells begin to convert power depends on a (desired) power level of the input power P. IN In this case, the power level refers to an average power level averaged over one period of the input voltage. If the average power level is above a predefined threshold, for example, the power converter in the Fig. 79A start in the sequence shown, so that the first converter 11 receives the highest proportion of the input power P INhas. For example, if the average power level is below the predefined threshold, the power converter in the Fig. The sequence shown in 79B begins so that the third converter 13 receives the highest proportion of the input power P IN has. An embodiment of a main controller 4, which is configured to control a multi-cell converter with an IS topology in which, based on the Fig. 79A, Fig. to operate in the manner explained in 79B is in Fig. 80 is shown. This controller is based on the one in Fig. 13 main controller 4 shown and additionally includes a block modulation controller 47, which determines the modulation index m from the modulation index controller 42 and the input voltage signal V IN_M receives, and is trained to determine the individual modulation indices (which are in Fig. 80 as m1-m N1 (are designated) to generate the individual converter cells according to Table 1.

[0269] Based on the Fig. In the IS converters described in 79A-81, the durations during which the individual converter cells convert power differ. This can lead to different cell input powers of the converter cells. For example, if the peak level of the input voltage V IN If the voltage is 360 V, then the first intermediate circuit voltage V21 is 180 V, the second intermediate circuit voltage V22 is 120 V, and the third intermediate circuit voltage V2 N1 is 60 V (so that the total intermediate circuit voltage V2 TOT 360 V), and if P IN_AVG If the average input power in a half-wave (or full-wave) is given by [formula], then the average cell input powers P are [formula]. 1_AVG -P 3_AVG of the individual converter cells as follows, if the converter cells are as described in Fig. 79 A are shown to be operated: P1_AVG=0.61⋅PIN_AVG P2_AVG=0.31⋅PIN_AVG P3_AVG=0.08⋅PIN_AVG.

[0270] If the converter cells are in the based on Fig. If the order explained in 79B is to be operated, the situation is as follows: P1_AVG=0.39⋅PIN_AVG P2_AVG=0.40⋅PIN_AVG P3_AVG=0.21⋅PIN_AVG.

[0271] In the present embodiment, the average cell input powers are essentially balanced, that is, the average cell input power of each cell is essentially 1 / 3 (0.33) of the average input power P IN_AVG , if the converter cells in the in Fig. 79B are operated in the sequence shown and if the intermediate circuit voltages are regulated so that they have the following voltage levels: V21=161V V22=104V V23=95V.

[0272] In a multi-cell converter with an IS topology, which is designed to generate the DC link voltages with different voltage levels, the individual converter cells 11-1 N1 They can be implemented with the same topology. However, the switches in the individual converter cells can differ in their reverse voltage withstand capability. "Reverse voltage withstand capability" defines the maximum voltage that an electronic switch can withstand in the off-state (switched-off state) without being damaged. If the electronic switch is implemented as a MOSFET, for example, the reverse voltage withstand capability depends on the specific design of the MOSFET within a semiconductor chip that integrates the active areas of the MOSFET. "Different" means that the electronic switches were intentionally designed to have different reverse voltage withstand capabilities.

[0273] Referring to the foregoing, in an IS converter, the reverse voltage withstand capability of the individual switches implemented within it is higher than the level of the associated intermediate circuit voltages. In the Fig. The converter cell 11 shown in the diagram is the high-side and low-side switch 12. H , 12 L For example, each is designed to have a blocking voltage withstand capability that is higher than the associated DC link voltages V21. Accordingly, in the Fig. 24 converter cell 1 shown i the individual switches 17 H , 18 LEach electronic switch is designed to have a reverse voltage withstand capability higher than the associated DC link voltage V21. Since the on-resistance of an electronic switch increases exponentially with increasing reverse voltage withstand capability, it is desirable to design the individual electronic switches to have the lowest possible reverse voltage withstand capability. Therefore, in the previously described embodiment, the first converter cell is implemented with electronic switches that have a higher reverse voltage withstand capability than the electronic switches in the second converter cell, and the second converter cell is implemented with electronic switches that have a higher reverse voltage withstand capability than the electronic switches in the third converter cell.

[0274] In the example explained above, where the intermediate circuit voltages V21-V23 are 180 V, 120 V and 60 V, the first converter cell can be implemented with electronic switches that have a reverse voltage withstand capability of 250 V, the second converter cell can be implemented with electronic switches that have a reverse voltage withstand capability of 150 V, and the third converter cell can be implemented with electronic switches that have a reverse voltage withstand capability of 80 V.

[0275] Operating individual converter cells with different DC link voltages is not limited to a multi-cell converter with an IS topology. Instead, this type of operation can also be used with a multi-cell converter with an OS topology, such as the one in Fig. 34 multi-cell converters are shown. That is, a multi-cell converter with an OS topology can be designed such that it can handle the intermediate circuit voltages V21-V2. N2 so that these intermediate circuit voltages V21-V2 are regulated N2 They have different voltage levels. As with the previously explained IS converter, the individual converter cells can be operated in block mode. This means that, based on the current voltage level of the output voltage, only one of the converter cells is operated with pulse-width modulation, while the other converter cells are in the on-state or off-state.

[0276] In the Fig. 79A and Fig. 79B are the voltages that occur in an OS converter designed to convert the intermediate circuit voltages V21-V2 N2 to be regulated with different voltage levels, and in which the converter cells are operated in block operation, indicated in parentheses. Apart from the signal waveform of the output voltage VOUT is the signal waveform of the total cell output voltage V3 TOT As shown. It is assumed that the output voltage has the same amplitude as the input voltage V. IN in the embodiment described above, and that the intermediate circuit voltages V21-V2 N2 have the same voltage levels as in the embodiment described above.

[0277] As with an IS converter, the converter cells in an OS converter are operated in a predefined sequence within a half-wave (or full-wave). In the case of the Fig. In the embodiment shown in 77A, the converter cell starts with the highest intermediate circuit voltage when the level of the output voltage V OUT increases, and in the Fig. In the embodiment shown in 77B, the converter cell starts with the lowest intermediate circuit voltage when the level of the output voltage V OUT increases.

[0278] Based on the Fig. 79A and Fig. In the exemplary embodiment described in 79B, the voltage levels of the individual intermediate circuit voltages V21-V2 can be determined. N2 The voltage is regulated by the IS converter or the OS converter. This means that the power converter not only regulates the total DC link voltage V2. TOT , but also the different levels of the individual intermediate circuit voltages V21-V2 N2According to another embodiment, a further power converter regulates the levels of the individual DC link voltages. In the case of the IS converter described above, for example, a further power converter can be connected to the DC link capacitors and receive power from the IS converter. According to one embodiment, the further power converter has an op-amp topology with multiple converter cells, wherein each converter cell of the further power converter regulates the DC link voltage across a respective DC link capacitor. In the case of the OS converter described above, for example, a further power converter can be connected to the DC link capacitors and supply power to the OS converter. According to one embodiment, the further power converter has an IP topology with multiple converter cells, wherein each converter cell of the further power converter regulates the DC link voltage across a respective DC link capacitor.

[0279] In the above explanation, it was assumed that V IN =m·V2 TOT in an IS converter or V OUT =m·V2 TOT in an OS converter. However, there may be cases where m·V2 TOT , which will be referred to below as V REF is referred to and can be expressed more generally by VREF=m⋅V2TOT=∑iN2mi⋅V2i not exactly the input voltage V IN or the output voltage V OUT There is generally a phase shift between the input and output voltage V. IN / V OUT and m·V2 TOT , which can be several degrees and which depends on the inductance of the coil 15 explained above. In such cases as explained above, where it has been explained that the operation of the power converter depends on the input voltage or the output voltage, as for example in the Fig. In the exemplary embodiments shown in Figures 71, 74 and 79A-79B, the operation of the power converter can also depend on V REF instead of V IN and V OUT , especially in cases where the coil 15 has a relatively high inductance.

[0280] For example, in the Fig. 71 and Fig. 74 illustrated embodiments show the two converter cells depending on V REF instead of depending on V IN or V OUT They can be connected in parallel or in series. In the case of the Fig. 79A and Fig. In the embodiment shown in 79B, the voltage thresholds at which the converter cells change their operating mode can be defined by V REF instead of V IN or V OUT to be compared. In this case, the one who receives Fig. 80 block modulation controllers shown 47 the DC link voltage signals (shown in dashed lines) to V REF to calculate.

[0281] However, using V changes REF instead of V IN and V OUT , in order to decide whether the operation of the power converter should be changed, not the general behavior, so that in the above description V IN and V OUT instead of V REF were used to describe the operation of the power converter. However, the operation is based on V IN or V OUT to understand that he is operating a business based on V REF also includes. That is to say, in the Fig. 71, 74, 79A-79B can V IN and V OUT by V REF be replaced.

[0282] Another degree of freedom in a multi-cell converter is the specific design of the half-bridges in those types of converter cells that incorporate half-bridges. These types of converter cells include, for example, converter cells with a boost topology, as found in... Fig. 12 is shown, with a full bridge topology as shown in Fig. 24 is shown, and with a bottoming topology as shown in Fig. 32B is shown. Fig. Figure 81 shows a half-bridge with a high-side switch HS and a low-side switch LS. This half-bridge represents any half-bridge in such converter cells with a previously described boost topology or totem-pole topology. In multi-cell converters with converter cells of this type, there are operating scenarios in which the half-bridge is operated in PWM mode. This is shown in Fig. Section 82 explains the timing diagrams of a control signal SLS of the low-side switch LS and a control signal SHS of the high-side switch HS in a control cycle of duration Tp. Referring to Fig. 82 becomes the low-side switch LS for one period T on The low-side switch (LS) is turned on while the high-side switch (HS) is off. After the low-side switch (LS) is turned off, the high-side switch (HS) is turned on. An on state of the low-side switch is represented by an on level of the associated drive signal (SLS), and an on level of the high-side switch (HS) is represented by an on level of the associated drive signal (SHS). Fig. 82 (in which, for illustrative purposes only, on-level is represented by a high level and off-level by a low level). A delay (dead time) may exist between the time the low-side switch LS turns off and the high-side switch HS turns on. However, this delay time is in Fig. 82 not shown.

[0283] At the in Fig. In the embodiment shown in Figure 81, the two switches HS and LS are designated as MOSFETs, specifically n-type MOSFETs. However, other types of transistors, such as IGBTs, BJTs, JFETs, or similar, can also be used. Regardless of the specific type of electronic switch used to implement the high-side and low-side switches, losses (conduction losses) occur when the respective switch HS or LS is in the on-state. The conduction losses of a switch depend on the electrical resistance of the switch in the on-state. This electrical resistance is subsequently referred to as the on-resistance R. ONThis is referred to as... In the multi-cell converters described above, the individual converter cells can be operated in continuous current mode (CCM). In this operating mode, the current through the converter cell does not drop to zero during a drive cycle (except for the time during which the respective input voltage V is...). IN or output voltage V OUT (of the multi-cell converter is zero). For the purpose of explanation, it is further assumed that the current through the low-side switch LS during the on-time T ON essentially the same as the current through the high-side switch HS during the off-time T OFF is. The time out T OFFThe time between the turn-off of the low-side switch LS and the end of the drive cycle is . Losses occurring in either the high-side switch HS or the low-side switch LS increase as the on-time of each switch increases. If the high-side switch HS and the low-side switch LS have essentially the same on-resistance R ON If the duty cycle is d=0.5, essentially the same losses occur in the high-side switch HS and the low-side switch LS, since each of the switches is in the on state for a duration which, at d=0.5, is essentially equal to 0.5·Tp.

[0284] The on-resistance R ONThe on-resistance of a switch is essentially inversely proportional to the chip area of ​​a semiconductor chip in which the respective switch is implemented. For example, if a total chip area A is available to implement the first switch HS and the second switch LS, and if each of the two switches HS, LS is implemented with essentially the same chip area, namely 0.5·A, then the two switches HS, LS have essentially the same on-resistance R. ON If the two switches are implemented such that they have essentially the same on-resistances R ONThe total line losses, which are the losses occurring in the high-side switch HS and the low-side switch LS, are independent of the duty cycle d. If the duty cycle d differs from 0.5, the total line losses can be reduced by designing the two switches to have different inrush currents. This is achieved using… Fig. 79 explains. In this context, "different" means that the electronic switches are intentionally designed to have different on-resistances. How the on-resistance of an electronic switch can be adjusted is explained above.

[0285] Fig. Figure 83 shows the total line losses P LOSS (a,d) depending on the duty cycle d in relation to the total line losses P LOSS(0.5, d) for identical chip areas of the HS and LS switches for different configurations of the high-side switch HS and the low-side switch LS. The total line losses are the losses that occur in the high-side and the low-side switches HS, LS in one drive cycle. In Fig. In Figure 83, “a” denotes the chip area of ​​the low-side switch LS relative to the total chip area used to implement the high-side switch HS and the low-side switch LS. For example, if a = 0.1, then the chip area of ​​the low-side switch LS is only 0.1 times the total chip area, while the chip area of ​​the high-side switch is 0.9 times the total chip area. Accordingly, the on-resistance of the low-side switch is nine times the on-resistance of the high-side switch. Fig. Figure 83 represents the case where the high-side switch and the low-side switch are implemented with the same chip area, which is 0.5 times the total chip area. A half-bridge in which the high-side switch HS and the low-side switch have the same chip area is called a symmetrical half-bridge. Conversely, a half-bridge implemented with electronic switches HS and LS that have different chip areas is called an asymmetrical half-bridge.

[0286] As demonstrated by Fig. As can be seen in section 83, a half-bridge with an asymmetrical design can be distinguished from a half-bridge with a symmetrical design (which is shown in Fig. 83 (represented by the dashed line labeled 0.5) may be superior if the duty cycle lies within a certain range. For example, a half-bridge with an asymmetric design, where a = 0.2, has lower losses than a half-bridge with a symmetric design if the duty cycle is below d = 0.2. In general, for a < 0.5, the asymmetric design offers lower losses if d<a. Wenn a> 0.5, the asymmetric design offers lower losses when d>a.

[0287] According to one embodiment, a multi-cell converter with an IS topology or an OS topology, comprising converter cells with at least one half-bridge, such as boost converter cells or totem-pole converter cells, includes at least one converter cell with an asymmetric half-bridge. In such multi-cell converters, the modulation index, and thus the duty cycle, of the individual converter cells can vary over a relatively large range during one half-cycle of a sinusoidal input voltage (output voltage). The asymmetric design of the at least one half-bridge in at least one converter cell and the variation of the duty cycle make it possible to operate the converter cell with the asymmetric half-bridge at a duty cycle where the asymmetric design is superior to the symmetric design. This is illustrated below by reference to Fig. 84 explained.

[0288] Fig. Figure 84 illustrates a method for operating a multi-cell converter with an IS topology or with an OS topology. In particular, it illustrates Fig. 84 a method for calculating modulation indices m1-m N1 the individual converter cells, which can have an elevated topology or a totem-pole topology. This in Fig. The procedure described in Figure 84 applies to a first power converter 10 with N1 converter cells. However, this procedure also applies analogously to a second power converter with N3 converter cells. Referring to the preceding explanation, a multi-cell converter with IS topology can be operated such that the instantaneous level of the input voltage V IN essentially the product of the modulation index m and the total intermediate circuit voltage V2 TOT corresponds (a multi-cell converter with an OS topology can be operated such that the instantaneous level of the output voltage V OUTessentially the product of the modulation index m and the total intermediate circuit voltage V2 TOT corresponds).

[0289] Referring to the foregoing, the current voltage level of the input voltage V can be IN of an IS converter through the total cell input voltage V1 TOT This can be achieved by operating the individual converter cells with the same modulation index m at one time. However, it is also possible to operate the individual converter cells with different modulation indices. In this case, the individual converter cells must be operated such that V IN =m 1· V21+m2·V22+...+m N1 ·V2 N2 The multiple modulation indices m1-m N1In this equation, the values ​​can be considered as modulation index vectors. It can be shown that the above equation can be satisfied by several different modulation index vectors. For example, if converter cell 11, which receives the modulation index m1, has high efficiency at a high modulation index (corresponding to a low duty cycle), the modulation index vector can be calculated such that m1 is high, while other modulation indices can be lower. The individual modulation indices m1-m N1 , obtained by this method can be applied to the individual converter cells (1072).

[0290] Fig. Figure 85 shows an embodiment of a main controller 4 configured to control a first power converter 10 with an IS topology and with at least one converter cell having an asymmetric half-bridge. This in Fig. 85 Main controllers 4 shown are based on the one in Fig. 13 main controller 4 shown and differs from this main controller 4 in that it additionally has a converter cell controller 46 which is designed to control the modulation indices m1-m N1 according to the based on Fig. 80 explained methods to generate.

[0291] Fig. Figure 86 shows a corresponding main controller 5 of a second power converter 20 with an OS topology. This main controller 5 is based on the in Fig. 35 main controller 5 shown and differs from this in Fig. The main controller shown in 35 is further enhanced by the fact that it additionally includes a converter cell controller 56, which controls the individual converter cells 21-2. N3 obtained modulation indices m1-m N3 according to the above based on Fig. 80 explained procedures calculated.

[0292] Alternatively or additionally to operating individual converter cells of a multi-cell converter, particularly a multi-cell converter with an IS or OS topology, at different modulation indices to operate the individual converter cells near their optimal operating point, the switching frequency (referred to above as fp) can be varied. That is, at least two converter cells of a multi-cell converter with an IS or OS topology can be operated in PWM mode with different switching frequencies. The modulation index can be the same for the two converter cells or it can be different. The two converter cells can be operated in PWM mode at the same time or at different times.Nevertheless, by operating at least two converter cells in PGM mode with different switching frequencies, the efficiency curves of the two converter cells differ, so that, for example, the converter cell with the higher switching frequency can have maximum efficiency at a lower power level than the converter cell with the lower switching frequency. According to one embodiment, the switching frequency of the converter cell with the higher switching frequency is at least twice the switching frequency of the converter cell with the lower switching frequency.

[0293] Fig. Figure 87 shows an embodiment of a full bridge comprising two half-bridges HB1, HB2, each half-bridge HB1, HB2 comprising a high-side switch HS1, HS2 and a low-side switch LS1, LS2. Each of these high-side and low-side switches HS1-LS2 comprises at least one silicon MOSFET. In the Fig. In the embodiment shown in Figure 83, these MOSFETs are n-type MOSFETs; however, p-type MOSFETs can also be used. Instead of just one MOSFET, each of these switches can comprise two or more MOSFETs connected in parallel to the load paths, which are switched on and off simultaneously.

[0294] The in Fig. Figure 87 shows the full bridge of any converter cell with a full-bridge (totem-pole) topology in any of the IS or OS multi-cell converters described above. Referring to Fig. 25 and the associated description will describe one of these half-bridges in a PWM operation, such as the one previously described using the Fig. 81 and Fig. 82 explained PWM operation. Referring to Fig. 87 silicon MOSFETs include an internal diode that is in Fig. Figure 87 is explicitly shown. This diode is often referred to as the body diode. If one of these half-bridges is operated in PWM mode, so that there is a delay between the turning off of one of the two switches and the turning on of the other, the body diode of the other switch becomes conductive. This is shown by the diagram in Fig. The depicted half-bridge 17 is explained in detail in section 24.

[0295] If the low-side switch is 17 L conducting, the input current I0 flows i through the low-side switch 17 L If the low-side switch is 17 L When switched off, the input current I0 flows i (driven by at least one coil of the multi-cell power converter circuit) by the parallel to the high-side switch 17 H switched diode. This in Fig. The diode shown in 24 can be formed by the body diode of a MOSFET when the high-side switch 17 HIt is implemented as a MOSFET. A current flows through the diode until the high-side switch 17 is closed. H switches on. At the end of a control cycle, 17 switches on. H off and the low-side switch 17 L switches back on. There may be a delay between the high-side switch 17 switching off and the high-side switch being switched off. H and the activation of the low-side switch 17 L be present, so that the input current I0 i further through the diode of the high-side switch 17 H flows until the low-side switch 17 L turns on.

[0296] If the diode of the high-side switch 17 H the input current I0 i When the diode conducts, electrical charge is stored in it. This charge must be removed before the diode blocks. This effect of removing electrical charge from a bipolar diode is commonly known as reverse recovery.

[0297] The electrical charge stored in the body diode of a MOSFET when the body diode is conducting depends, among other things, on the MOSFET's output capacitance. This output capacitance, and thus the charge stored in the diode, increases as the MOSFET's reverse voltage withstand capability increases, with the output capacitance rising exponentially. That is, the output capacitance is a function of V. B c , with c>1, where V B The term refers to the reverse voltage withstand capability. Due to this relatively high output capacitance, silicon MOSFETs were considered unsuitable for implementing the switches in a power converter with a totem-pole topology. In this context, reference is made to Zhou et al.: “99% Efficiency True-Bridgeless Totem-Pole PFC Based on GaN HEMTs”.

[0298] However, in a multi-cell converter with an IS or OS topology, the individual switches can be implemented with a reverse voltage withstand capability lower than the DC link voltage. For example, if the total DC link voltage is 600 V and a conventional power converter (with PFC functionality) is used, the converter must be implemented with switches that have a reverse voltage withstand capability of 600 V. In the IS or OS converters described above, the switches in a converter cell can be implemented with a reverse voltage withstand capability that corresponds only to the voltage level of the respective DC link voltage. For example, if N1=4 or N3=4 converter cells 11-1 N1 or 21-2 N3If N is present, it may be sufficient to implement the individual switches with a reverse voltage withstand rating of 150 V (= 600 V / 4). If N=10 or N3=10, a reverse voltage withstand rating of only 60 V (= 600 V / 10) may be sufficient.

[0299] In an IS or OS converter, the total on-resistance is N1 times (or N3 times) the on-resistance of a switch, so the on-resistance increases linearly as the number of converter cells increases. However, the total reverse recovery charge stored in the switches of each converter cell decreases exponentially. This is explained below with an example. In a silicon MOSFET, there is a figure of merit (FOM) that describes the ratio between the on-resistance and the charge that must be removed from the MOSFET when the body diode switches from the forward-biased to the reverse-biased state, namely RDS(on). ON ·Q REV_REC (QREV_REC is often referred to as QRr+Q OSS denoted by Q OSS The charge stored in the output capacitance and Qrr the charge stored in the diode when it switches from a forward current to a reverse current). The on-resistance can be reduced by implementing the MOSFET with a larger chip area, where the on-resistance R ON is essentially inversely proportional to the chip area. However, since Q REV_REC The FOM is essentially proportional to the chip area, while the FOM defined above is essentially independent of the chip area and mainly depends on the blocking voltage withstand capability and the specific design.

[0300] A 600 V blocking voltage MOSFET from the Cool-MOS™ CFD2 series by Infineon Technologies AG, Munich, has a FOM of approximately 78,000 (7.8 E4). A 60 V blocking voltage MOSFET from the same supplier's OptiMOS series has an FOM of only 346. The total FOM of 10 series-connected converter cells is 3460, which is 22 times better than the FOM of a single 600 V blocking voltage MOSFET. Therefore, a multi-cell converter with several cells connected in series, such as 4, 6, 10, or more, exhibits competitive reverse recovery performance.

[0301] Referring to the description in connection with Fig. 1. The power converter circuit includes at least one multi-cell converter. That is, any type of the previously described first power converter 10 with a multi-cell topology can be coupled with a second power converter that does not have a multi-cell topology, or it can be used alone, without a second power converter. Similarly, any type of the previously described second power converter 20 with a multi-cell topology can be coupled with a first power converter that does not have a multi-cell topology, or it can be used alone, without a first power converter. This is illustrated below with reference to two examples. Fig. 88 and Fig. 89 explained.

[0302] Fig. Figure 88 shows an embodiment of a power converter circuit in which the second power converter 20 is a multi-cell converter of any of the types described above. The first power converter is a single-cell converter. That is, the first power converter comprises only one converter cell 11, which is configured to receive power from the inputs IN1, IN2 and to supply power to the multiple intermediate circuit capacitors 111-112. N1 to supply which are connected in series at the cell output of converter cell 11. Converter cell 11 can have either a boost or buck switching characteristic. That is, the DC link voltage can be higher or lower than a (peak) level of the input voltage.

[0303] Fig. Figure 89 shows an embodiment of a power converter circuit comprising a second power converter 20 of any of the types described above. In this embodiment, there is no further power converter (no first converter). The individual intermediate circuit capacitors 21-2 N2 couple the second power converter 20 to a DC power source 9 with several power source cells 91-9 N2 , wherein each power source cell is connected to an intermediate circuit capacitor 21-2 N2 is connected. Examples of power source cells include, but are not limited to, batteries, photovoltaic (PV) panels, fuel cells, or similar devices. According to one embodiment, the second power converter 20 comprises an OS topology and PFC functionality and is configured to supply power to an AC power grid (AC network).

[0304] Fig. Figure 90 shows an embodiment of a power converter circuit with a first power converter 10 and a second power converter 20. The second power converter comprises several converter cells 21-2. N3 , the power output of the first converter 10 and the associated intermediate circuit capacitors 111-11 N2 The topology of the second converter 20 differs from each of the previously explained topologies of a second converter in that the cell output of each of the multiple converter cells 21-2 N3 to one of several loads Z1-Z N3 is connected, which are supplied by the second converter 20. This means the cell outputs of the converter cells 21-2 are connected. N3 not connected (neither in series nor in parallel). According to one embodiment, the loads Z1-Z N3 Direct current loads (DC loads), so that the individual converter cells 21-2 N3These are DC / DC converter cells. The first converter can have an IS topology and PFC functionality.

[0305] According to one embodiment, the first converter 10 is configured to receive the input voltage from a medium-voltage network. Using the Fig. The converter circuit shown in 90 can handle DC loads, such as loads Z1-Z. N3They can be supplied directly from a medium-voltage network without the need to transform the medium AC voltage to a low AC voltage. Depending on the specific type of medium-voltage network, the input peak voltage can reach up to several tens of kV. However, due to the IS topology in the first converter 10, semiconductor switches with a reverse voltage withstand capability significantly lower than the input peak voltage can be used in the converter cells of the first converter 10. In this embodiment, more than 10 and up to several 10 converter cells can be used in the first converter 10 and, correspondingly, in the second converter 20. The "reverse voltage withstand capability" defines the maximum voltage that an electronic switch can withstand in the off-state (switched-off state) without being damaged.

[0306] The first and second power converters 10 and 20 described above can be combined in a variety of ways to create power converter circuits for many different AC / DC, DC / AC, or DC / DC power conversion applications. Some of these applications are explained below. In these applications, the specific design of the first power converter 10 and the second power converter 20 can be selected based on various parameters, such as the (peak) level of the input voltage and the (peak) level of the output voltage. An IS topology can be used when the input voltage level is relatively high, such as above 100 V, while an IP topology can be used when the voltage level is lower.Accordingly, an OS topology can be used when the output voltage level is relatively high, such as above 100 V, and an OP topology can be used when the voltage level is lower. When designing the power converter circuit, the number of converter cells in the first power converter circuit (10) and the second power converter circuit (20) can depend on the input peak voltage and can be higher the higher the input peak voltage.

[0307] An AC / DC power converter circuit can be configured to obtain a low voltage from a low-voltage network or a medium voltage from a medium-voltage network. A low-voltage network supplies a sinusoidal voltage of 100 V. EFF or 220 V EFF(so that a peak voltage is approximately 155 V or 310 V). A medium-voltage network supplies a sinusoidal voltage with a peak voltage of a few kilovolts (kV), up to 10 kV. The AC / DC power converter circuit can include a first power converter 10, which converts the intermediate circuit voltages V21-V2. N2 regulates, and a second power converter 20, which regulates the output voltage V OUT regulates, encompass.

[0308] A DC / AC power converter circuit can be configured to receive DC power from a DC voltage source and to supply AC power to an AC power grid. In one embodiment, the DC power source comprises a solar panel. In another embodiment, the DC power source comprises a high-voltage direct current (HVDC) power transmission network. The power grid supplied by the DC / AC power converter can be a low-voltage or medium-voltage power grid. The DC / AC power converter can include a first power converter, which transforms one of the input currents I IN and the input voltage V IN regulates, and a second power converter 20, which regulates the intermediate circuit voltages V21-V2 N2 or regulates the output voltage.

[0309] During operation of the multi-cell converter, a fault may occur in a converter cell of the first power converter 10 or the second power converter 20. Examples of such faults include, but are not limited to, a short circuit of at least one cell input and / or cell output of the respective converter cell, a malfunctioning electronic switch (permanently on or permanently off) in the respective converter cell, or similar issues. To avoid the need to shut down the multi-cell power converter, it is desirable to isolate the faulty converter cell and keep the other converter cells running to maintain the power supply to the load connected to outputs OUT1 and OUT2.A multi-cell power converter capable of isolating converter cells while maintaining power supply, and corresponding methods for operating the multi-cell power converter are explained below using examples.

[0310] Fig. Figure 91 schematically illustrates an embodiment of a multi-cell power converter. This multi-cell power converter is based on the principles described in the Fig. 1 and Fig. 90 illustrated embodiments. That is, the multi-cell power converter can only have one output, as shown in Fig. 1 is shown, or can have several different outputs (as in Fig. 91 (shown in dotted lines), as in Fig. 90 is shown. In addition to those shown in the Fig. 1 and Fig. The 90 multi-cell power converters shown are included in the Fig. Figure 91 shows a multi-cell power converter with a fault management unit 310. This fault management unit is designed to detect a fault in the individual converter cells of at least one of the first and second power converters, to isolate a faulty converter cell, and, optionally, to change the operating mode of at least one of the other (non-faulty) converter cells. For this purpose, the fault management unit 310 communicates with at least one of the first and second power converters 10, 20. This signal communication is described in Fig. Figure 91 is only schematically illustrated by arrows. The signal communication between the fault management unit 310 and at least one of the first power converters 10 and the second power converters 20 can include the receipt of measurement signals by the fault management unit 310 from at least one monitored converter cell in at least one of the first and second power converters 10, 20. The at least one monitored converter cell 10 is a converter cell that is monitored by the fault management unit 310 in order to be able to detect a fault occurring in the respective converter cell. According to one embodiment, each of the converter cells in at least one of the first power converters 10 and the second power converters 20 is monitored by the fault management unit 310, so that each of the converter cells in at least one of the first and second power converters 10, 20 is a monitored converter cell.

[0311] Measurement signals received by the fault management unit 310 from the at least one monitored converter cell are those signals representing parameters in the monitored converter cell that are suitable for detecting a fault. Such measurement signals may include, but are not limited to, measurement signals representing an input current, an input voltage, an output current, and an output voltage of the monitored converter cell. The signal communication between the fault management unit 310 and at least one of the first and second power converters 10, 20 further includes receiving control signals by at least one of the first and second power converters 10, 20 from the fault management unit, wherein these control signals serve to isolate the faulty converter cell and, optionally, to modify the operating mode of at least one non-faulty converter cell.

[0312] In Fig. 91 shows the fault management 310 as a circuit block, which is separated from other components of the multi-cell power converter, such as the first power converter 10, the second power converter 20 and the intermediate circuit capacitors 111-11. N2 is separate. However, this is merely for illustrative purposes. The fault management unit 310 and the at least one main controller 4 in the first power converter 10 and the main controller 5 in the second power converter 20 can share hardware, such as a microprocessor. That is, software implementing the functionality of at least one of the main controllers 4, 5 and software implementing the functionality of the fault management unit 310 can run on one and the same microprocessor.

[0313] The following drawings explain the Fault Management Unit 310 and circuits associated with it. "Circuits associated with the Fault Management Unit 310" are those circuits controlled by the Fault Management Unit 310 to isolate a faulty converter cell and maintain proper operation of the non-faulty converter cells. These drawings focus on illustrating the functionality of such circuits rather than on their implementation. These circuits can be implemented in a variety of ways, including purely hardware implementations or hardware and software implementations.

[0314] Basically, two different types of faults can occur: a fault in a first converter cell (a converter cell of the first power converter 10) or a fault in a second converter cell (a converter cell of the second power converter 20). First, exemplary embodiments of the fault management unit 310 and associated circuits capable of handling a fault in a converter cell of the second power converter 20 are explained.

[0315] Fig. Figure 92 shows an embodiment of a multi-cell power converter implemented with an ISOP topology. In the Fig. In the embodiment shown in Figure 92, the multi-cell power converter comprises an output OUT1, OUT2, that is, the cell outputs of the converter cells 21, 2 N3The second power converter 20 are connected in parallel. In this embodiment, the fault management unit 310 is configured to control an interrupter circuit 311. This interrupter circuit 311 comprises a switch between the output of each converter cell monitored by the fault management unit 310 and the output OUT1, OUT2 of the multi-cell power converter. In the embodiment described in Fig. In the embodiment shown in 92, each of the converter cells 21-2 N3 monitored, so that the interrupter circuit 311 is a switch 3111-311 N3 between each of these converter cells 21-2 N3and the output OUT1, OUT2. The fault management unit 310 is designed to open the switch in the interrupter circuit 311 between the respective converter cell and the output upon detection of a fault in a converter cell, in order to disconnect the faulty converter cell from the output OUT1, OUT2. In a multi-cell power converter of the in Fig. The type shown in 90, in which several different outputs are present, can be an interrupter circuit of the one in Fig. The 92 types shown are omitted.

[0316] The individual switches 3111-311 N3 The interrupter circuit 311 can be implemented as semiconductor switches (e.g., MOSFETs, IGBTs, BJTs, JFETs), relays, controllable fuses, or similar devices. "Controllable fuses" are fuses that can be triggered by the fault management unit 310.

[0317] Various types of faults can occur in converter cells 21-2N3 of the second power converter 20. Some types of faults and how they can be detected are explained below. A first type of fault is a short circuit between the output nodes of the cell output of a converter cell.

[0318] In the multi-cell power converter of the in Fig. For the type shown in Figure 90, this fault can be detected by measuring the output voltages of the individual converter cells 21-2. N3 If the output voltage of a converter cell drops to zero or below a predefined voltage threshold close to zero, a short circuit is assumed to exist at the cell output of that converter cell. To detect such a fault, the fault management unit 310 monitors the output voltages V31-V3. N3 of the individual converter cells 21-2 N3 Alternatively or additionally to monitoring the output voltages V31-V3 N3 of the individual converter cells 21-2N3 The fault management unit 310 can control the output currents I21-I2 N3 of the individual converter cells 21-2 N3 monitor, where a fault occurs in a converter cell 21-2 N3 is detected when a level of the associated output current I21-I2 is reached. N3 exceeds a predefined current threshold.

[0319] If the cell outputs of the individual converter cells 21-2 N3 are connected in parallel, as is the case in Fig. As shown in Figure 92, a short circuit at the cell output of a converter cell causes the output voltage of each of the second converter cells 21-2 to N3 drops. In this multi-cell power converter, the fault management unit 310 can be configured to regulate the output voltage V. OUT to monitor. After detecting that the output voltage V OUTIf the voltage drops to zero or below a predefined voltage threshold, the fault management unit 310 can subsequently activate switches 3111-311. N3 The interrupter circuit 311 is switched off for a predefined period of time, which is hereinafter referred to as the off-time. If, during the off-time, one of these switches 3111-311 N3 the output voltage V OUT If the voltage rises again, the converter cell whose output is connected to the respective switch is the faulty converter cell. The fault management unit 310 then keeps the respective switch in the off state to isolate the faulty converter cell from outputs OUT1 and OUT2.

[0320] A short circuit at the input of one of the converter cells 21-2 N3 can be detected by the fault management unit 310 by monitoring the input voltage V21-V2 N2 of the individual converter cells 21-2 N3 and the output currents 111-11 N2the associated first converter cells 11-1 N1 of the first power converter 10. If the input voltage V21-V2 N2 a converter cell 21-2 N3 drops to zero or below a predefined voltage threshold, and when the associated converter cell 11-1 N1 If an output current is present, it can be assumed that there is a short circuit at the input of the respective second converter cell. In this case, the switch assigned to this second converter cell in the interrupter circuit 311 is opened to isolate this converter cell from the output OUT1, OUT2.

[0321] Alternatively or additionally to detecting a short circuit at the input by monitoring the input voltages V21-V2 N2 A short circuit at the input of one of the converter cells 21-2 can occur N3 can be detected by monitoring the output currents I11-I1 N2 the converter cells 11-1 N2and compare the current levels of these currents I11-I1 N2 with a current threshold. When the current level of the output current of one of the converter cells 11-1 N1 If the current threshold of the first converter 10 is exceeded, it can be assumed that there is a short circuit at the input of the associated converter cells 21-2. N3 in the second converter 20 is present.

[0322] Isolating the faulty second converter cell includes not only interrupting an electrical connection between the faulty converter cell and the output OUT1, OUT2 by the interrupting circuit 311, but also modifying the operation of the first converter cell associated with the faulty second converter cell so that the first converter cell ceases to transfer power to the faulty second converter cell. According to one embodiment, "ceases to transfer power to the second converter cell" includes completely interrupting any power transfer from the first converter cell to the associated DC link capacitor or the faulty second converter cell.According to another embodiment, this includes operating the first converter cell such that the average power transferred to the intermediate circuit capacitor is zero, in the same way as explained above with reference to the operation of the filter cells.

[0323] The following section describes exemplary embodiments of methods for completely interrupting power transmission from the first converter cell to the faulty second converter cell while maintaining power transmission from first converter cells associated with non-faulty second converter cells to these non-faulty second converter cells. Completely interrupting power transmission from a first converter cell associa...

Claims

[1] Method which features: Detecting a faulty converter cell (22) in a power converter that includes several first converter cells (11-1N1), several second converter cells (21-2 N3 ) and several intermediate circuit capacitors (111-1 N2 ) exhibits, wherein each of the several intermediate circuit capacitors (111-11 N2 ) one of the several first converter cells (11-1N1) and one of the several second converter cells (21-2 N3 ) connects; and deactivating the faulty converter cell (22) while maintaining power conversion operation of the power converter, wherein each of the several first converter cells (11-1N1) has a cell input and each of the several second converter cells (21-2 N3 ) has a cell output, wherein the cell inputs of the several first converter cells (11-1N1) are connected in series to one input of the power converter, wherein the cell outputs of the several second converter cells (21-2 N3 ) are connected in parallel to one output of the power converter, wherein detecting the faulty transducer cell involves detecting a faulty second transducer cell (22), and where the deactivation of the faulty second converter cell (21-2 N3 ) shows: the termination of the cell output of the faulty second converter cell (21-2 N3 ) from the output of the power converter, and either operating the first converter cell (12), which is connected to the faulty second converter cell (22), at an average output power of zero and an instantaneous output power depending on an input voltage (V) obtained at the input of the power converter IN ) or short-circuiting the cell input of the first converter cell (12) which is connected to the faulty second converter cell (22). [2] Method which features: Detecting a faulty converter cell in a power converter that includes multiple first converter cells (11-1N1) and multiple second converter cells (21-2) N3 ) and has several intermediate circuit capacitors (111-11N2), each of the several intermediate circuit capacitors (111-11 N2 ) one of the several first converter cells (11-1N1) and one of the several second converter cells (21-2 N3 ) connects; and deactivating the faulty converter cell while maintaining power conversion operation of the power converter, wherein each of the several first converter cells (11-1N1) has a cell input and each of the several second converter cells (21-2 N3 ) has a cell output, wherein the cell inputs of the several first converter cells (11-1N1) are connected in parallel to one input of the power converter wherein the cell outputs of the several second converter cells (21-2N3 ) are connected in series at one output of the power converter, where the detection of the faulty converter cells involves the detection of a faulty first converter cell, and where deactivating the faulty first converter cell exhibits: the disconnection of the cell input of the faulty first converter cell from the input of the power converter, and either operating the second converter cell, which is connected to the faulty first converter cell, with an average input power of zero and an instantaneous output power dependent on an output voltage obtained at the output of the power converter, or short-circuiting the cell output of the second converter cell, which is connected to the faulty first converter cell. [3] Power converter, which features. several first converter cells (11-1N1), several second converter cells (21-2 N3) and several intermediate circuit capacitors (111-11 N2 ), wherein each of the several intermediate circuit capacitors (111-11N2) is one of the several first converter cells (11-1N1) and one of the several second converter cells (21-2 N3 ) connects; and a fault management unit (310) designed to detect a faulty converter cell (22) and to deactivate the faulty converter cell (22) while maintaining power conversion operation of the power converter, wherein each of the several first converter cells (11-1N1) has a cell input and each of the several second converter cells (21-2 N3 ) has a cell output, wherein the cell inputs of the several first converter cells (11-1N1) are connected in series to one input of the power converter, wherein the cell outputs of the several second converter cells (21-2 N3 ) are connected in parallel to one input of the power converter, wherein the fault management unit is designed to detect the faulty transducer cell by detecting a faulty second transducer cell (22), and wherein the fault management unit (310) is configured to deactivate the faulty second converter cell by: Terminating the cell output of the faulty second converter cell (21-2) N3 ) from the output of the power converter, and either operating the first converter cell (12), which is connected to the faulty second converter cell (22), at an average output power of zero and an instantaneous output power that depends on an input voltage obtained at the input of the power converter, or short-circuiting the cell input of the first converter cell, which is connected to the faulty second converter cell (22). [4] Power converter, which features. several first converter cells (11-1N1), several second converter cells (21-2 N3 ) and several intermediate circuit capacitors (111-11 N2 ), wherein each of the several intermediate circuit capacitors (111-11N2) is one of the several first converter cells (11-1N1) and one of the several second converter cells (21-2 N3 ) connects; and a fault management unit (310) designed to detect a faulty converter cell (22) and to deactivate the faulty converter cell (22) while maintaining power conversion operation of the power converter, wherein each of the several first converter cells (11-1N1) has a cell input and each of the several second converter cells (21-2 N3 ) has a cell output, wherein the cell inputs of the several first converter cells (11-1N1) are connected in parallel to one input of the power converter, wherein the cell outputs of the several second converter cells (21-2 N3 ) are connected in series at one output of the power converter, wherein fault management unit (310) is configured to detect the faulty converter cell by detecting a faulty first converter cell, and wherein the fault management unit (310) is configured to deactivate the faulty first converter cell by: Disconnecting the cell input of the faulty first converter cell from the input of the power converter, and either operating the second converter cell, which is connected to the faulty first converter cell, at an average input power of zero and an instantaneous output power which depends on the output voltage obtained at the output of the power converter, or short-circuiting the cell output of the second converter cell, which is connected to the faulty first converter cell (22).

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