Method and circuit for controlling a switching transistor and integrated circuit

Abstract

A method for driving a switching transistor (212; 244; 450; 452), the method comprising: Obtaining an activation signal for the switching transistor (212; 244; 450; 452); Generating a sequence of random values; and upon receipt of the activation signal, driving a control node of the switching transistor (212; 244; 450; 452) with a driving strength based on a random value from the sequence of random values.

Description

[0001] The present disclosure relates generally to an electronic device and, more particularly, to a system and method for a switching transistor driver.

[0002] Power supply systems are ubiquitous in many electronic applications, from computers to automobiles. Generally, voltages in a power supply system are generated by performing DC-DC, DC-AC, and / or AC-DC conversion by operating a switch loaded with an inductor or transformer. One class of such systems includes switched-mode power supplies (SMPS).

[0003] An SMPS typically contains at least one switch and an inductor or transformer. Some specific topologies include, among others, buck converters, boost converters, and flyback converters. A control circuit is typically used to open and close the switch to charge and discharge the inductor. In some applications, the current and / or voltage supplied to the load is controlled via a feedback loop.

[0004] In general, the efficiency of an SMPS improves as the switching speed increases because switching losses decrease. Accordingly, SMPSs utilize more advanced power semiconductor components, such as super-junction MOSFETs (metal oxide semiconductor field-effect transistors) and IGBTs (insulated gate bipolar transistors), to increase the switching speed in SMPSs. These advanced power semiconductor components exhibit very low switching losses and high switching speed due to low internal parasitic capacitances. However, one of the side effects of high switching speeds is increased electromagnetic emissions, which poses challenges for designing an SMPS that is both power-efficient and compliant with relevant electromagnetic interference (EMI) standards and requirements.

[0005] DE 10 2013 111 113 A1 describes an output driver comprising a plurality of transistors connected in parallel, which are controlled by a control circuit. The control circuit is designed to control the individual transistors individually in order to set different fall times of a signal controlled by the output driver.

[0006] The object underlying the invention is to provide a method for driving a switching transistor that conforms to relevant standards and requirements for electromagnetic interference (EMI), and to provide a corresponding circuit.

[0007] This object is achieved by a method according to claim 1, a circuit according to claim 12 and an integrated circuit according to claim 24.

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings: Fig. Figure 1 illustrates a conventional switching transistor drive system; Fig. 2a and Fig. 2b illustrates an embodiment of a switching transistor drive system in which the output impedance is varied; Fig. 3a - 3b illustrate circuit diagrams of an embodiment of a random signal generator for use in embodiment of a switching transistor drive system; Fig. 4 illustrates a switching transistor drive system according to the present invention in which the output voltage is varied; Fig. 5 illustrates a switching transistor drive system according to the present invention in which the output current is varied; and Fig. 6 illustrates a block diagram of a method according to the invention.

[0009] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise noted. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter may follow a figure number to illustrate variations of the same structure, material, or process step.

[0010] The making and using of presently preferred embodiments are discussed in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts that can be practiced in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0011] The present invention is described with respect to preferred embodiments in a specific context, a system and method for a switching transistor driver. Embodiments of the present invention may also be applied to other circuits, including, but not limited to, switching power supplies, motor control systems, communication systems, as well as other circuits potentially producing noise emissions due to switching circuits.

[0012] In one embodiment of the present invention, a switching transistor driver is operated using variable-strength driver circuits whose drive strength is varied according to a random and / or quasi-random sequence. By varying the drive strength of the switching transistor driver, the steepness of the switching edges is modulated from switching cycle to switching cycle, thereby attenuating sharp peaks in the frequency spectrum of electromagnetic emissions (EMI).

[0013] In various embodiments, modulating the strength of the driver circuitry can be performed by a gate driver circuit independently of the gating signal provided by a control unit. This enables EMI improvement in existing applications through a plug-and-play replacement of the gate drivers without requiring replacement of other system components. In other examples, systems and methods according to the present invention can be combined with other known systems and methods for attenuating noise emissions.

[0014] Fig. 1 illustrates an exemplary switching transistor driver system 100 including gate driver circuit 101 driving IGBT switching transistor 112. As shown, gate driver circuit 101 includes transistor 108, driven by buffer 102, and transistor 110, driven by inverting buffer 104. The output of gate driver circuit 101 is coupled to transistor 112 via series resistor Rs. During operation, an input signal is buffered by buffers 102 and 104, which drive the gates of transistors 108 and 110, respectively. When the signal at node INPUT goes high, the output of buffer 102 also goes high, driving the gate of transistor 108. When transistor 108 turns on, the gate of transistor 112 goes high and turns on transistor 112 via gate resistor Rs.When the signal at node INPUT goes low, the output of buffer 102 goes low, turning off transistor 108, while the output of inverting buffer 104 goes high, turning on transistor 110. When transistor 110 turns on, the gate of transistor 112 discharges through resistor Rs, turning off transistor 112. During turn-on and turn-off of transistor 112, steep transients caused by the periodic, rapid charging and discharging of the device capacitances of transistor 112 can cause EMI.

[0015] In the past, EMI has been addressed by modulating the switching frequency and / or the duty cycle of the switching signal itself. This spreads the spurious power of the fundamental frequency and its sidebands over a wider frequency band, thereby attenuating the peak height of the spurious signals.

[0016] In one embodiment of the present invention, spurious emissions are attenuated by randomly and / or quasi-randomly adjusting the drive strength of a switching transistor driver system. Fig. Figure 2a illustrates an embodiment of a switching transistor driver system 200 that adjusts its drive strength by adjusting the driver's output impedance, for example, on a per-cycle basis. As shown, the switching transistor driver system 200 includes the random signal generator 202, which randomly activates one or more of n high-side transistors 208_1 through 208_n via respective buffers 204_1 through 204_n and n low-side transistors 210_1 through 210_n via respective buffers 206_1 through 206_n. In one embodiment, the n high-side transistors 208_1 through 208_n and the n low-side transistors are implemented using NMOS transistors. Alternatively, other transistor types may be used, for example, PMOS transistors, NPN bipolar transistors, and PNP bipolar transistors, or any combination thereof. It is understood that control logic according to the present invention may be modified to drive the transistors of such alternative embodiments.For example, PMOS transistors can be used to implement high-side transistors, or a combination of PMOS and NMOS transistors working together can be used to implement high-side switches. In such an embodiment, the signal used to activate a high-side PMOS transistor is inverted with respect to the signal used to activate a high-side NMOS device.

[0017] In one embodiment, the output impedance of switching transistor driver system 220 at output pins OUTPUT1 and OUTPUT2 is inversely proportional to the number of selected high-side and low-side transistors. By modifying the selection of output transistors on a per-cycle basis, the variation at the output of switching transistor driver system 200 serves to attenuate spikes in the frequency response. In one embodiment, switching transistor driver system 200 may include any number of randomly selected transistor output stages. In some embodiments, deselected transistor stages are completely disabled by turning the corresponding transistors OFF. For example, if transistors 208_1 and 210_1 are not selected, both transistors are turned OFF.

[0018] As shown, all high-side transistors 208_1 to 208_n, as well as the low-side transistors 210_1 to 210_n, are separately and independently addressable via the high-side control signals A1H to AnH and the low-side control signals A1L to AnL, respectively. In some embodiments, the various high-side and low-side transistors are randomly selected independently of each other. In other embodiments, transistor pairs are selected by the random signal generator 202.

[0019] The switching transistor driver system 200 includes the integrated circuit 222, on which the various driver elements are arranged and which is coupled to the IGBT switching transistor 212 via the resistor Rs. Alternatively, other types of semiconductor-based switches can be used to implement the transistor 212, such as power MOSFETs and bipolar transistors. As shown, the OUTPUT1 and OUTPUT2 pins are connected together externally of the integrated circuit 222. In alternative embodiments, other external connection configurations can be implemented, such as those with one resistor at OUTPUT1 and another resistor at OUTPUT2.

[0020] Fig. Figure 2b illustrates the switching transistor driver system 230, which includes the integrated circuit 232 coupled to the IGBT switching transistor 244 via resistors Rs1, Rs2, and Rs3. The integrated circuit 232 includes the random signal generator 202, which is configured to drive the high-side transistors 238_1 through 238_n via buffers 234_1 through 234_n and the low-side transistors 240_1 through 240_n via inverting buffers 236_1 through 236_n. As shown, the transistors 238_1 through 238_n and 240_1 through 240_n are arranged in pairs. For example, the high-side transistor 238_1 is coupled to the low-side transistor 240_1 to drive the transistor 244 via the resistor Rs1, the high-side transistor 238_2 is coupled to the low-side transistor 240_2 to drive the transistor 244 via the resistor Rs2, and the high-side transistor 238_n is coupled to the low-side transistor 240_n to drive the transistor 244 via the resistor Rsn.It should be understood that n could be any number two or greater, and that integrated circuit 232 may be configured to support any number of switching transistors. As shown, each transistor of each transistor pair may be independently controlled using separate high-side control signals A1H through AnH and low-side control signals A1L through AnL, as described with respect to FIG. Fig. 2b is described.

[0021] In some embodiments, deselected transistor stages are completely deactivated by turning the corresponding transistors OFF. For example, if transistors 238_1 and 240_1 are not selected, both transistors are turned OFF via control signals A1H and A1L, placing the corresponding transistor pair output in a high-impedance state. In some embodiments, once a full switching cycle has been executed for the high-side and low-side transistors, the outputs of the random signal generators are set to a known state to maintain the selected transistors in a safe, fully on or off state. This known state can then be asserted at a fixed time after the gate signal completes its transition, and / or it can be asserted based on voltage feedback, current feedback, charge feedback, or a combination thereof.

[0022] Fig. Figure 3a illustrates a random signal generator 300 according to the invention that can be used to generate the Fig. 2a and Fig. 2b and described above. As shown, the embodiment random signal generator 300 includes random signal generator 302, which produces an m-bit random number. This m-bit random number is mapped to a set of high-side enable outputs P1H through PnH and low-side enable outputs P1L through PnL, which are used to determine which transistor output stages are enabled when the input gate signal is enabled. In some embodiments, random number generator 302 produces a new random value at each transition of the gate signal. In an alternative embodiment, a new random value is produced by random number generator 302 based on the state of the optional clock signal CLK.

[0023] As shown, the AND gates 306_1H to 306_nH produce the selection signals A1H to AnH, and the inverters 307_1 to 307_n together with the AND gates 306_1L to 306_nL produce the selection signals A1L to AnL, which are used to select the various Fig. 2a and Fig. 2b shown transistor output stages. It is understood that the embodiment in Fig. 3a is merely one example of many possible circuits that can be used to produce the selection signals A1H to AnH and A1L to AnL. In alternative embodiments, other circuits that produce a similar function can be used. For example, the lookup table 304 can be implemented using other forms of mapping logic. Likewise, the various Fig. 3a may be implemented using other circuits and / or logic functions. For example, in some embodiments, a single inverter may be used instead of inverters 307_1 through 307_n.

[0024] Fig. Figure 3b illustrates an exemplary linear feedback shift register 360 that can be used to Fig. 3a. As shown, the linear feedback shift register 360 takes the form of a linear Fibonacci feedback shift register containing a 16-bit shift register implemented using D flip-flops 320 to 335 with outputs D0 to D15. The outputs of registers 330, 332, 333, and 335, corresponding to outputs D10, D12, D13, and D15, are each fed back to the first register 320 via exclusive-OR gates 340, 342, and 344. Accordingly, the linear feedback shift register 360 implements the following polynomial: x16+x14+x13+x11+1.

[0025] It is understood that the Fig. 3b is merely one of many linear feedback shift register structures that may be used to implement the embodiment-specific random number generator 320. Other linear feedback structures may be used, including, but not limited to, linear Galois feedback shift registers. Furthermore, embodiment-specific linear feedback shift registers may be implemented using bit lengths other than 16 and / or may be implemented using polynomials other than those described above. In some embodiments, the clock signal CLK coupled to the various registers may be based on the state of the Fig. 3a shown gate signal.

[0026] In another embodiment, other random number generator circuits besides linear feedback shift register-based random number generators may be used, including, but not limited to, hardware generators based on physical entropy sources (thermal noise, shot noise, avalanche noise, radioactive decay, etc.) and random number algorithms implemented in software and / or hardware.

[0027] According to a further embodiment, the strength of the drive signal can be varied by randomly adjusting the drive voltage applied to a drive transistor. As in Fig. As illustrated in Figure 4, the supply voltage provided to high-side transistor 412 and low-side transistor 416 is varied according to the output of random signal generator 402 in driver system 400. As shown, the output of high-side transistor 412 is coupled to IGBT switching transistor 450 via resistor Rs2, and the output of low-side transistor 416 is coupled to IGBT switching transistor 450 via resistor Rs1. In one embodiment, the output of random signal generator 402 is applied to the inputs of digital-to-analog converters (DACs) 404 and 408, whose output voltages are buffered by unity-gain operational amplifier-based buffers 406 and 410, respectively. The DACs 404 and 408 can be implemented using standard DAC circuits known in the art.Alternatively, other DAC circuits and / or bit resolutions may be used according to the particular embodiment and its specifications. Buffers 406 and 410 may be implemented using various operational amplifier circuits known in the art. Alternatively, non-unit-gain architectures and / or buffer circuits that do not utilize operational amplifiers may be used. In some embodiments, once a full switching cycle has been executed for the high-side and low-side transistors, the outputs of the random signal generators are set to a known state to maintain the controlled transistors in a safe, fully on or off state.This known state can then be activated at a fixed time after the gate signal has completed the transition, and / or it can be activated based on voltage feedback, current feedback, charge feedback, or a combination thereof.

[0028] In a further embodiment, the strength of the drive signal can be varied by randomly adjusting the current drive fed into the gate of the switching transistors. As in Fig. 5, the current provided to high-side transistor 438 and low-side transistor 446 is varied according to the output of random signal generator 432. As shown, the output of high-side transistor 438 is coupled to IGBT switching transistor 452 via resistor Rs2, and the output of low-side transistor 446 is coupled to IGBT switching transistor 452 via resistor Rs1. In one embodiment, the output of random signal generator 432 is applied to the input of digital-to-analog converter (DAC) 434, and its output voltage is converted to a corresponding drive current using a feedback circuit including output transistor 438, resistor 440, and operational amplifier 436. In one embodiment, the output voltage of DAC 434 is applied to resistor 440 via operational amplifier 436 and high-side transistor 438.The gain of operational amplifier 436 effectively forces the voltage at the negative input terminal of operational amplifier 436 to substantially match the voltage at the positive input terminal of operational amplifier 436. Thus, when the output voltage of DAC 434 is adjusted, the voltage across resistor 440 is adjusted, thereby changing the current flowing through transistor 438. Similarly, another output of random signal generator 432 is coupled to the input of DAC 442, which applies its output voltage to a feedback circuit including operational amplifier 444, low-side transistor 446, and resistor 448.

[0029] During operation, the high-side gate signal Gate_HS causes the random signal generator 432 to output a random value, which is applied to the DAC 434. The output of the DAC 434 is then converted into a drive current using the operational amplifier 436, the output transistor 438, and the resistor 440. Similarly, the low-side gate signal Gate_LS causes the random signal generator 432 to output a random value, which is applied to the DAC 442. The output of the DAC 442 is then converted into a drive current using the operational amplifier 444, the output transistor 446, and the resistor 448. In alternative embodiments of the present invention, other circuits may be used. For example, in one embodiment, the drive current at the outputs OUTPUT1 and OUTPUT2 are produced directly using a current DAC (IDAC).In some embodiments, once a full switching cycle has been executed for the high-side and low-side transistors, the outputs of the random signal generators are set to a known state to maintain the controlled transistors in a safe, fully on or off state. This known state can then be activated at a fixed time after the gate signal has completed the transition, and / or it can be activated based on voltage feedback, current feedback, charge feedback, or a combination thereof.

[0030] Fig.6 illustrates a block diagram 500 of an embodiment of a method for driving a switching transistor. In step 502, an activation signal for a switching transistor is received, and in step 504, a sequence of random values ​​is generated. In some embodiments, each random value may be generated from the sequence of random values ​​upon receipt of the activation signal, or it may be generated using an independent clock. Finally, in step 506, a control node of the switching transistor is driven using a drive strength based on a random value from the sequence of random values. As discussed with respect to embodiments herein, the drive strength may be varied, for example, by modifying the output impedance, drive voltage, or drive current of the switching transistor driver.

[0031] Systems and methods according to the present invention may be combined with other known systems and methods for attenuating noise emissions. For example, the phase, frequency, and / or duty cycle of the gate signal used to trigger circuits and systems according to the present invention may be modulated using conventional systems and methods for reducing noise emissions. In one example, the frequency of the switching signal is modulated. By further modifying the drive strength of the drive signal in a random manner, as described above, noise emissions may be further reduced.

[0032] According to various embodiments, circuits or systems may be configured to perform specific operations or actions by virtue of having hardware, software, firmware, or a combination thereof installed in the system that, in operation, causes the system to perform the actions. A general aspect includes a method for driving a switching transistor, including receiving an activation signal for the switching transistor and generating random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value from the sequence of random values. Other embodiments of this aspect include corresponding circuits and systems configured to perform the various actions of these methods.

[0033] The implementations may include one or more of the following features. The method, wherein driving the control node of the switching transistor includes driving the control node of the switching transistor with a driver circuit, and wherein the method further includes adjusting the driver circuit according to the random value from the sequence of random values. The method, wherein adjusting the driver circuit includes adjusting an output impedance of the driver circuit. Driving the control node of the switching transistor with the drive strength based on the random value from the sequence of random values ​​may be configured to attenuate peaks in an electromagnetic interference (EMI) spectrum.

[0034] In some embodiments, adjusting the output impedance of the driver circuit includes selectively enabling a subset of a plurality of parallel output drivers such that a number of output drivers in the subset is based on the random value from the sequence of random values. In another embodiment, selectively enabling a subset of a plurality of parallel output drivers includes applying the random value to an input of a lookup table and determining the subset of the plurality of parallel output drivers based on an output of the lookup table. Adjusting the driver circuit may include adjusting an output voltage of the driver circuit according to the random value from the sequence of random values.

[0035] In one embodiment, driving the control node of the switching transistor includes applying the adjusted output voltage to the control node of the switching transistor via at least one resistor. Adjusting the output voltage may include applying the random value to an input of a digital-to-analog converter and coupling an output of the digital-to-analog converter to the control node of the switching transistor. In various embodiments, adjusting the driver circuit includes adjusting an output current of the driver circuit. In one embodiment, generating the sequence of random values ​​includes using a linear feedback shift register. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0036] Another general aspect includes a circuit comprising a random sequence circuit configured to produce a sequence of random values, and an adjustable drive circuit having an output configured to be coupled to a control node of a switching transistor. The adjustable drive circuit is configured to produce a drive signal upon receiving an activation signal, the drive signal having a drive strength based on a random value from the sequence of random values. Other embodiments of this aspect include corresponding circuits and systems configured to perform the various actions of these methods.

[0037] The implementations may include one or more of the following features. The circuit further includes the switching transistor coupled to the output of the adjustable drive circuit. The circuit further includes a resistor coupled between the output of the adjustable drive circuit and the control node of the switching transistor. The circuit, wherein the random sequence circuit and the adjustable drive circuit are arranged on a semiconductor substrate. The circuit, wherein the adjustable drive circuit has an output impedance based on the random value.

[0038] In some embodiments, the adjustable drive circuit has an output voltage based on the random value, while in other embodiments, the adjustable drive circuit has an output current based on the random value. In some embodiments, the random sequence circuit includes a plurality of enable outputs, and the random sequence circuit is configured to determine a subset of the plurality of enable outputs based on the random value and enable the subset of the plurality of enable outputs. The random sequence circuit may include a linear feedback shift register.

[0039] The adjustable drive circuit may include a plurality of output drivers with corresponding inputs coupled to the plurality of enable outputs. In some embodiments, the plurality of output drivers are coupled in parallel. Each of the plurality of output drivers may include a high-side driver and a low-side driver, with an output of the high-side driver coupled to an output of the low-side driver. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0040] Another general aspect includes an integrated circuit including a quasi-random sequence generator, a plurality of output drivers configured to be coupled to an external switching transistor, and logic circuitry having inputs coupled to an output of the quasi-random sequence generator and outputs coupled to the plurality of output drivers. The logic circuitry is configured to activate a subset of the plurality of output drivers based on an output of the quasi-random sequence generator upon receipt of an activation signal. Other embodiments of this aspect include corresponding circuits and systems configured to perform the various actions of the methods.

[0041] Implementations may include one or more of the following features: The integrated circuit, wherein the plurality of output drivers are coupled in parallel. The integrated circuit, wherein each of the plurality of output drivers includes a high-side and a low-side driver such that an output of the high-side driver is coupled to an output of the low-side driver. In some embodiments, the quasi-random sequence generator includes a linear feedback shift register followed by a lookup table. Implementations of the described techniques may include hardware, a method or process, or computer software on a computer-accessible medium.

[0042] Advantages of some embodiments include the ability to modulate the steepness of the switching edge from cycle to cycle to attenuate sharp peaks in the frequency spectrum of electromagnetic emissions without having to modulate the frequency and / or duty cycle of the switching signal. Furthermore, circuitry used to modulate the frequency and / or duty cycle to reduce spurious emissions can be omitted in some embodiments where the drive strength is modulated. In various embodiments, higher power efficiencies can be maintained due to fast switching edges while simultaneously limiting electromagnetic emissions.

[0043] Another advantage is the ability to modulate the strength of the driver circuit independently of the gating signal provided by a control unit, enabling EME improvement through a plug-and-play replacement of gate drivers without replacing other system components. Another advantage of some embodiments is the ability to attenuate sharp peaks in the frequency spectrum without significantly affecting the switching frequency and duty cycle.

[0044] In one or more examples, the functionality described herein may be implemented at least in part in hardware, such as special-purpose hardware components or a processor. In general, the techniques may be implemented in hardware, processors, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored on or transmitted over a computer-readable medium as one or more instructions or code and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media that corresponds to a tangible medium, such as data storage media or transmission media, including any medium that enables transmission of a computer program from one location to another, e.g., according to a communications protocol.Computer-readable media in this manner may generally correspond to (1) tangible, computer-readable storage media that is non-transitory, or (2) a communications medium, such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or by one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0045] By way of example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium used to store desired program code in the form of instructions or data structures and accessible by a computer. Additionally, each connection is properly called a computer-readable medium, i.e., a computer-readable transmission medium.For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL (Digital Subscriber Line), or wireless technologies such as infrared, radio, and microwave, then the definition of medium includes the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave. It is understood, however, that computer-readable storage media and data storage media do not contain connections, carrier waves, signals, or other transient media, but instead refer to non-transient, tangible storage media. Disk and disc, as used herein, include CD (Compact Disc), laser disc, optical disc, DVD (Digital Versatile Disc), floppy disk, and Blu-ray Disc, with disks typically reproducing data magnetically, while discs reproducing data optically using lasers.Combinations of the above should also be included in the area of ​​computer-readable media.

[0046] Instructions may be executed by one or more processors, such as one or more central processing units (CPUs), digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FGPAs), or other equivalent integrated or discrete logic circuits. Accordingly, the term "processor" as used herein may refer to any of the aforementioned structures or to any other structure capable of implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided in dedicated hardware and / or software modules configured for encoding and decoding or integrated into a combined codec.In addition, the techniques could be fully implemented in one or more circuits or logic elements.

[0047] The techniques of this disclosure may be implemented in a wide variety of devices or apparatus, including a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to carry out the disclosed techniques, but do not necessarily require implementation by different hardware units. Rather, as described above, various units may be combined into a single hardware unit or provided as a collection of intraoperative hardware units, including one or more processors in conjunction with suitable software and / or firmware, as described above.

Claims

[1] A method for driving a switching transistor (212; 244; 450; 452), the method comprising: Obtaining an activation signal for the switching transistor (212; 244; 450; 452); Generating a sequence of random values; and upon receipt of the activation signal, driving a control node of the switching transistor (212; 244; 450; 452) with a driving strength based on a random value from the sequence of random values. [2] Method according to claim 1, wherein driving the control node of the switching transistor (212; 244; 450; 452) comprises driving the control node of the switching transistor (212; 244; 450; 452) with a driver circuit (200; 230; 400; 430); and wherein the method further comprises adjusting the driver circuit (200; 230; 400; 430) according to the random value from the sequence of random values. [3] The method of claim 2, wherein adjusting the driver circuit (200; 230; 400; 430) comprises adjusting an output impedance of the driver circuit (200; 230; 400; 430). [4] The method of claim 3, wherein adjusting the output impedance of the driver circuit (200; 230; 400; 430) comprises selectively activating a subset of a plurality of parallel output drivers, wherein a number of output drivers in the subset is based on the random value from the sequence of random values. [5] The method of claim 4, wherein selectively activating the subset of multiple parallel output drivers comprises applying the random value to an input of a lookup table (304) and determining the multiple parallel output drivers based on an output of the lookup table (304). [6] The method of any one of claims 2 to 5, wherein adjusting the driver circuit (200; 230; 400; 430) comprises adjusting an output voltage of the driver circuit (200; 230; 400; 430) according to the random value from the sequence of random values. [7] The method of claim 6, wherein driving the control node of the switching transistor (212; 244; 450; 452) comprises applying the adjusted output voltage to the control node of the switching transistor (212; 244; 450; 452) via at least one resistor (Rs; Rs1, Rs2; Rs1, Rs2, Rsn). [8] The method of claim 6, wherein adjusting the output voltage comprises applying the random value to an input of a digital-to-analog converter and coupling an output of the digital-to-analog converter to the control node of the switching transistor (212; 244; 450; 452). [9] The method of any one of claims 2 to 5, wherein adjusting the driver circuit (200; 230; 400; 430) comprises adjusting an output current of the driver circuit (200; 230; 400; 430). [10] A method according to any one of the preceding claims, wherein generating the sequence of random values ​​comprises using a linear feedback shift register (360). [11] The method of any preceding claim, wherein driving the control node of the switching transistor (212; 244; 450; 452) with the drive strength based on the random value of the sequence of random values ​​is configured to attenuate peaks in an electromagnetic interference (EMI) spectrum. [12] Circuit that has: a random sequence circuit (202; 300; 402; 432) configured to produce a sequence of random values; and an adjustable drive circuit having an output configured to be coupled to a control node of a switching transistor (212; 244; 450; 452), wherein the adjustable drive circuit is configured to produce a drive signal upon receipt of an activation signal, wherein the drive signal has a drive strength based on a random value from the sequence of random values. [13] The circuit of claim 12, further comprising the switching transistor (212; 244; 450; 452) coupled to the output of the adjustable drive circuit. [14] The circuit of claim 13, further comprising a resistor (Rs; Rs1, Rs2; Rs1, Rs2, Rsn) coupled between the output of the adjustable drive circuit and the control node of the switching transistor (212; 244; 450; 452). [15] Circuit according to one of claims 12 to 14, wherein the random sequence circuit (202; 300; 402; 432) and the adjustable drive circuit are arranged on a semiconductor substrate. [16] A circuit according to any one of claims 12 to 15, wherein the adjustable drive circuit has an output impedance based on the random value. [17] A circuit according to any one of claims 12 to 15, wherein the adjustable drive circuit has an output voltage based on the random value. [18] A circuit according to any one of claims 12 to 15, wherein the adjustable drive circuit has an output current based on the random value. [19] Circuit according to one of claims 12 to 18, in which the random sequence circuit (202; 300; 402; 432) has a plurality of activation outputs; and the random sequence circuit is configured to determine a subset of the plurality of activation outputs based on the random value and to activate the subset of the plurality of activation outputs. [20] The circuit of claim 19, wherein the adjustable drive circuit comprises a plurality of output drivers having respective inputs coupled to the plurality of enable outputs. [21] The circuit of claim 20, wherein the plurality of output drivers are coupled in parallel. [22] The circuit of claim 20, wherein each of the plurality of output drivers comprises a high-side driver and a low-side driver, an output of the high-side driver coupled to an output of the low-side driver. [23] A circuit according to any one of claims 12 to 22, wherein the random sequence circuit comprises a linear feedback shift register (360). [24] Integrated circuit comprising: a quasi-random sequence generator (202; 300; 402; 432); a plurality of output drivers configured to be coupled to an external switching transistor (212; 244; 450; 452); and a logic circuit having inputs coupled to an output of the quasi-random sequence generator (202; 300; 402; 432) and having outputs coupled to the plurality of output drivers, wherein the logic circuit is configured to activate a subset of the plurality of output drivers based on an output of the quasi-random sequence generator (202; 300; 402; 432) upon receipt of an activation signal. [25] The integrated circuit of claim 24, wherein the plurality of output drivers are coupled in parallel. [26] The integrated circuit of claim 24 or 25, wherein each of the plurality of output drivers comprises a high-side driver and a low-side driver, an output of the high-side driver being coupled to an output of the low-side driver. [27] Integrated circuit according to one of claims 24 to 26, wherein the quasi-random sequence generator (202; 300; 402; 432) comprises a linear feedback shift register (360) followed by a lookup table (304).

Images