LEVEL CONVERTER AND METHOD FOR OPERATING THIS

Abstract

Level converter (100), comprising the following: a connection for low supply voltage (LS), a connection for high supply voltage (HS), at least one input port (I1, I2), at least one output port (O, O'), and a latch (150) comprising several transistors (T1, T2, T3, T4) and designed to do the following: • Storing a predetermined logical state by setting a memory node (K3, K5 / K4, K6) to a voltage level in response to receiving a predetermined voltage level at the at least one input terminal (I1, I2), where the voltage level at the low supply voltage (LS) terminal is a first value and the voltage level at the high supply voltage (HS) terminal is a second value. • Changing the voltage level at the storage node (K3, K5 / K4, K6) in response to receiving one or more changed voltage levels at the low supply voltage (LS) and high supply voltage (HS) terminals, and • Outputting the predetermined logical state with the changed voltage level from the memory node (K3, K5 / K4, K6) to at least one output (O, O'), • where changing the voltage level at the storage node exhibits: • Increasing the voltage level at the high supply voltage terminal from the second value to a third value; • then increase the voltage level at the low supply voltage terminal from the first value to a fourth value; • then increase the voltage level at the high supply voltage (HS) terminal from the third value to a fifth value, • where the fifth value is chosen such that a voltage difference between the fifth value and the fourth value is just maintained by the transistors (T1, T2, T3, T4).

Description

background

[0001] The present invention relates generally to a level converter and a method for operating it.

[0002] Logic device supply voltages are typically around 1 V, a low voltage level. However, higher voltages are required to operate non-volatile flash memory, e.g., 10 to 17 V. Special high-voltage devices (HV devices) are used in the logic process to handle these high voltages.

[0003] Generally, low voltage has a voltage level above 0 V. Furthermore, medium voltage has a voltage level above low voltage, and high voltage has a voltage level above medium voltage. Specific transition values ​​between low, medium, and high voltage depend on the specific application of the logic device and are known in the art.

[0004] To switch high output voltage signals 306, 308 to low input voltage signals 310, 312, a so-called level converter is used. A known design of a level converter uses a cascode structure, which includes a cascode connection 314, 316. Fig. Figure 3 is shown – used when the output high voltage is higher than the maximum permissible operating voltage of a device. The cascode structure is used to operate with voltages higher than the permissible operating voltage of a device such as a transistor, supplied by supply voltage terminals 302 and 304. In the cascode 318, a second transistor (source) is connected to the drain of a first transistor to reduce the overall voltage, similar to a series resistor. Thus, the cascode circuit can operate with higher voltages than the individual transistors would allow.

[0005] As with all other types of cascoded circuits, the circuit area increases significantly. This means that a higher silicon area is required when the number of transistors needed increases and the transistor width needs to be enlarged. In particular, the transistor footprint of high-voltage (HV) transistors is significantly larger than that of low-voltage (LV) transistors. Furthermore, the manufacturing effort increases with the higher high-voltage capabilities of the HV devices. For this reason, it would be preferable to implement the cheapest possible HV devices to reduce process costs.

[0006] DE 10 2014 102 151 A1 discloses a voltage-level converter circuit comprising a voltage switch circuit and a level-shifting circuit. The voltage switch circuit is configured to sequentially output an intermediate voltage and a converter voltage in response to a switching signal. The level-shifting circuit is configured to temporarily store a voltage level corresponding to an input signal using the intermediate voltage and to convert the temporarily stored voltage level using the converter voltage to generate an output signal.

[0007] US 6,333,662 B1 discloses a latch-type level shifter circuit comprising a circuit for generating an internal power supply potential, for generating a first and a second internal power supply potential; a latch circuit with a first and a second node driven by the first and the second internal power supply potential; a level shifter with a first and a second output terminal driven by the first internal power supply potential and a fixed potential; a first MOS transistor at whose gate the fixed potential is applied; and a second MOS transistor at whose gate the fixed potential is applied.

[0008] DE 695 17 287 T2 discloses a voltage level converter comprising: an input bias terminal; connections to a first low-voltage source VCC, a second high-voltage source VPP, and a reference voltage source VSS; first and second output terminals transmitting complementary high-voltage output signals; an input control terminal; and an automatic bias stage with a third output terminal, wherein the input bias terminal is connected to the third output terminal of the automatic bias stage, the bias stage comprising a first unidirectional current conductor to provide a low voltage drop, which is connected between the first low-voltage source and the third output terminal, and a second unidirectional current conductor to provide a selected voltage drop, which is connected between the second high-voltage source and the third output terminal.and a third conductive element connected between the reference voltage source and the third output terminal, the biasing stage having connections to the voltage sources to provide essentially the first low voltage to the third output terminal in the absence of the second high voltage, and to provide a third voltage greater than the first low voltage when the second high voltage is present, the third voltage being derived from the second high voltage.

[0009] US 2009 / 0058493A1 discloses an electronic device with a supply voltage level converter that converts a signal from a first low supply voltage level to a second high supply voltage level and comprises: a first pair of cross-coupled MOS transistors compatible with the second supply voltage level, each having a source connected to the second supply voltage level and providing complementary output signals at respective drains; driven by a second pair of common-gate MOS transistors compatible with the second supply voltage; driven by a third pair of common-gate MOS transistors compatible with the first voltage level;and controlled by first and second inverters coupled in a chain and supplied with the first supply voltage level, each having an output connected to the source of a transistor in a third pair.

[0010] US 7,560,970 B2 discloses a level shifter comprising first and second latches and first through fourth transistors. The first latch has a first and second power supply terminal and a first and second node. The second latch has a third and fourth power supply terminal and a third and fourth node. The first transistor has a first current electrode coupled to the first node, a control electrode coupled to receive a first bias, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to the third node, and a control electrode coupled to receive a second bias.The third transistor has a first current electrode coupled to the second node, a control electrode coupled to receive the first bias voltage, and a second current electrode. The fourth transistor has a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to receive the second bias voltage, and a second current electrode coupled to the fourth node.

[0011] US 7,348,800 B2 discloses a level-shifting circuit comprising a driver circuit and an output circuit. The driver circuit includes a clamping circuit for receiving a first and a second bias potential, which outputs a first and a second driver signal that are not lower than a reference potential, lower than the first bias potential, and complementary to each other, and which also outputs a third and a fourth driver signal that are higher than the second bias potential, not higher than a current source potential, and complementary to each other. Summary of the invention

[0012] A level converter according to claim 1 and a method for operating a level converter according to claim 15 are provided. Further embodiments are provided in the dependent claims.

[0013] The invention provides a level shifter for shifting a voltage and a method for operating such a level shifter, i.e., for converting a lower voltage signal into a higher voltage signal. This eliminates the need for a cascode structure. Alternatively or additionally, the output voltage can be higher than the permissible operating voltage of the level shifter's components. Furthermore, the level shifter can have a smaller footprint than that required for a cascode level shifter. Brief description of the drawings

[0014] In the drawings, the same reference numerals generally refer to the same parts across different views. The drawings are not necessarily to scale; instead, the focus is generally on illustrating the principles of the invention. The following description details various embodiments of the invention with reference to the following drawings, wherein: Fig. 1 shows a circuit diagram of a level converter according to different embodiments; Fig. 2 Time diagrams of voltage levels in a level converter according to different embodiments are shown; and Fig. 3 shows a level converter according to a state of the art. Description

[0015] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be implemented. These embodiments are described in sufficient detail to enable those skilled in the art to apply the invention. Other embodiments may be used, and structural, logical, and electrical modifications may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments.

[0016] Fig. Figure 1 shows a circuit diagram of a level shifter 100 according to various embodiments. In these embodiments, the level shifter includes a latch 150, wherein the low supply voltage (provided at a low supply voltage terminal LS) and the high supply voltage (provided at a high supply voltage terminal HS) of the latch 150 can be changed. The latch 150 comprises several transistors T1, T2, T3, T4 and is designed to store a value set by an input I1, I2, such as a set input I1 and a reset input I2. The value can be a voltage or a voltage level that correlates with a logic state such as "1" or "0". The value can be stored in a node K4, K6 or K3, K5, each connected to an output O and O' of the level shifter 100.

[0017] The content of Latch 150, e.g., a logic "1" or a logic "0", can be set to a low supply voltage level via the low supply voltage terminal LS from a low-voltage input signal at input terminal I1. A low supply voltage level can be approximately 0 V, for example. The operating principle of the level shifter is described in Fig. 2 shown in more detail.

[0018] Afterwards, the low and / or high supply voltage of the Latch 150 can be changed to higher voltages via the respective terminals LS, HS for high and low supply voltage.

[0019] As a result, the voltage level at the output terminal O of the level shifter 100 can be converted to approximately the voltage level of the high supply voltage if the stored content is a logic "1". That is, the voltage level can be approximately the same as the voltage level provided at the low supply terminal if the stored content is a logic "0". However, the latch 150 retains the content, which is the logic state at the output terminal O, if one or more input terminals I1, I2 are isolated after the latch 150 is set. The isolation of the input terminal can be achieved by biasing the transistors T1, T2, T3, T4 of the latch 150 with a voltage, such as a mid-voltage across a bias terminal C1, C2, which is connected to and / or controls the voltage level at the gate or base terminals of the respective terminals T1, T2, T3, T4.

[0020] The voltage at one or more input terminals I1, I2 can be a low voltage, i.e., in a range of approximately 0 V to 5 V. The voltage at one or more bias terminals C1, C2 can be a medium voltage, which is higher than the low voltage. The voltage at transistors T1, T2, T3, T4 of latch 150 can be a high voltage, which is higher than the medium voltage.

[0021] The maximum bias voltage across transistors T1, T2, T3, and T4 of latch 150 cannot be increased during operation of the level shifter 100, for example, if the low and high supply voltages are simultaneously converted to higher voltages. This means that transistors T1, T2, T3, and T4 of latch 150 will only see the voltage difference between the high and low supply voltages and will not see the entire high output voltage of the high supply voltage relative to 0 V.

[0022] Specifically, the level converter 100 can, in various embodiments, include a connection for low supply voltage LS and a connection for high supply voltage HS. The low supply voltage connection LS can be connected to a second node K2, and the high supply voltage connection HS can be connected to an eighth node K8.

[0023] The level converter 100 can further include the latch circuit 150, one or more input terminals I1, I2, C1, C2 and one or more output terminals O, O', which are described in more detail below.

[0024] The Latch 150 can be implemented using high-voltage devices (HV devices) and HV transistors T1, T2, T3, and T4 in various configurations. Transistors T7 and T8, which are directly connected to input terminals I1 and I2, can be low-voltage devices (LV devices).

[0025] The Latch 150 of the Level Converter 100 can comprise a first path and a second path. The second path can have a competing voltage level with respect to the voltage level of the first path.

[0026] The first path can be connected to or include a first input terminal I1 and a first cascode bias terminal C1. The first input terminal I1 can be connected to a transistor T8, and the first cascode bias terminal C1 can be connected to a transistor T5.

[0027] Transistor T8, connected to the first input terminal I1, can be a low-voltage transistor. Transistor T8 can have a first terminal, which is either an emitter or a source terminal, connected to a second node K2. Transistor T8 can have a second terminal, which is either a gate or a base terminal, connected to input terminal I1. Transistor T8 can have a third terminal, which is either a collector or a drain terminal, connected to a terminal of transistor T5, which is connected to the cascode bias terminal C1.

[0028] Transistor T5, connected to the first cascode bias terminal C1, can be a high-voltage transistor. Transistor T5 can have a first terminal, which is an emitter or source terminal, connected to a terminal of transistor T8, which in turn is connected to the input terminal I1, for example, connected to the collector or drain terminal of transistor T8. Transistor T5 can have a second terminal, which is a gate or base terminal, connected to the cascode bias terminal C1. Transistor T5 can have a third terminal, which is a collector or drain terminal, connected to a third node K3 and / or a fifth node K5.

[0029] The second path can be connected to or include a second input terminal I2 and a second cascode bias terminal C2. The second input terminal I2 can be connected to transistor T7, and the second cascode bias terminal C2 can be connected to transistor T6.

[0030] Transistor T7, connected to the second input terminal I2, can be a low-voltage transistor. Transistor T7 can have a first terminal, which is either an emitter or a source terminal, connected to the first capacitor K1. Transistor T7 can have a second terminal, which is either a gate or a base terminal, connected to input terminal I2. Transistor T7 can have a third terminal, which is either a collector or a drain terminal, connected to a terminal of transistor T6, which is connected to the cascode bias terminal C2.

[0031] Transistor T6, connected to the second cascode bias terminal C2, can be a high-voltage transistor. Transistor T6 can have a first terminal, which is an emitter or source terminal, connected to a terminal of transistor T7, which is connected to input terminal I2, for example, connected to the collector or drain terminal of transistor T7. Transistor T6 can have a second terminal, which is a gate or base terminal, connected to cascode bias terminal C2. Transistor T6 can have a third terminal, which is a collector or drain terminal, connected to a sixth node K6 and / or a fourth node K4.

[0032] The second input terminal I2 can be inverted relative to the first input terminal I1, i.e., the voltage level correlated with a logic state is inverted.

[0033] The first node K1 can be connected to the second node K2. The sixth node K6 can be connected to the fourth node K4. A seventh node K7 can be connected to the eighth node K8. A fifth node K5 can be connected to the third node K3. Fig. In Figure 1, nodes K1, K2, K3, K4, K5, K6, K7, and K8 are shown as separate nodes to clearly illustrate the underlying principles of the logic device. At least some of the nodes may actually have the same electrical potential. Therefore, nodes with the same electrical potential can be considered as a single node. In particular, node K1 may be the same as node K2, node K3 may be the same as node K5, node K4 may be the same as node K6, and node K7 may be the same as node K8.

[0034] A first output terminal O can be connected to the fourth node K4, and a second output terminal O' can be connected to the fifth node K5. The second output terminal O' can have a voltage level corresponding to a logic state that competes with an inverted logic state corresponding to a voltage level at the first output terminal O.

[0035] Additionally, the first path can include a first transistor T1 and a second transistor T2. Both transistors, T1 and T2, can be high-voltage transistors. In various embodiments, the first transistor T1 can be an n-type transistor (npn) and the second transistor T2 a P-type transistor (pnp).

[0036] Transistor T1 can have a first terminal, which is an emitter terminal or a source terminal, connected to node K2. Transistor T1 can have a second terminal, which is a gate terminal or a base terminal, connected to node K4. Transistor T1 can have a third terminal, which is a collector terminal or a drain terminal, connected to node K3.

[0037] Transistor T2 can have a first terminal, which is an emitter or source terminal, connected to node K8. Transistor T2 can have a second terminal, which is a gate or base terminal, connected to node K4. Transistor T2 can have a third terminal, which is a collector or drain terminal, connected to node K3.

[0038] The second approach can include a third transistor T3 and a fourth transistor T4. The third and fourth transistors, T3 and T4, can be high-voltage transistors. In various embodiments, the third transistor T3 can be an n-type transistor (npn) and the fourth transistor T4 a P-type transistor (pnp).

[0039] Transistor T3 can have a first terminal, which is either an emitter or a source terminal, connected to node K1. Transistor T1 can have a second terminal, which is either a gate or a base terminal, connected to node K5. Transistor T1 can have a third terminal, which is either a collector or a drain terminal, connected to node K6.

[0040] Transistor T4 can have a first terminal, which is an emitter or source terminal, connected to node K7. Transistor T4 can have a second terminal, which is a gate or base terminal, connected to node K5. Transistor T4 can have a third terminal, which is a collector or drain terminal, connected to node K6.

[0041] This means that the collector or drain terminals of the first and second transistors T1, T2 of the first path can be connected to the gate or base terminals of the third and fourth transistors T3, T4 of the second path via nodes K3, K5. Furthermore, the collector or drain terminals of the third and fourth transistors T3, T4 of the second path can be connected to the gate or base terminals of the first and second transistors T1, T2 of the first path via nodes K4, K6.

[0042] The emitter or source terminals of the first transistor T1 of the first path and the third transistor T3 of the second path can be connected to the low supply voltage terminal LS via nodes K1 and / or K2.

[0043] The emitter or source terminals of the second transistor T2 of the first path and the fourth transistor T4 of the second path can be connected to the high supply voltage terminal HS via nodes K7 and / or K8.

[0044] The collector or drain terminal of transistor T5, which is connected to the first cascode bias terminal C1, can be connected to the collector or drain terminals of the first and second transistors T1, T2 via node K3.

[0045] The collector or drain terminal of transistor T6, which is connected to the second cascode bias terminal C2, can be connected to the collector or drain terminals of the third and fourth transistors T3, T4 via node K6.

[0046] The emitter or source terminals of transistors T7, T8, which are connected to the first and second input terminals I1, I2 as described above, can be connected to the emitter or source terminals of the first transistor T1 of the first path and the third transistor T3 of the second path.

[0047] The first output terminal O can be connected to the gate or base terminals of the first and second transistors T1, T2 of the first path and / or the drain or collector terminals of the third or fourth transistors T3, T4 of the second path via nodes K4 and / or K6.

[0048] The second output terminal O' can be connected to the gate or base terminals of the third and fourth transistors T3, T4 of the second path and / or the drain or collector terminals of the first or second transistors T1, T2 of the first path via nodes K3 and / or K5.

[0049] The voltage at the cascode bias terminals C1, C2 prevents high voltages, e.g., from the low and high supply voltage terminals LS, HS, from propagating to the low-voltage input terminals I1, I2. This means that the one or more LV transistors T7, T8, which are directly connected to the one or more input terminals I1, I2, are each protected by HV transistors T5, T6, which are each connected, for example, to the one or more cascode bias terminals C1, C2. The gates or bases of the HV transistors T1, T2, T3, T4 of latch 150 can be constantly biased by the high supply voltage of the one or more cascode bias terminals C1, C2, for example, by about 5 V in the example shown in timing diagram 210. Fig. 2 is shown.

[0050] Thus, the level converter 100, according to various embodiments, can comprise fewer HV devices, such as transistors, than a level converter known in the art, e.g., 6 HV transistors instead of 8 HV transistors as used by a cascoded level converter, as described in Fig. Figure 3 shows that cascoding the low supply voltage in the latch by using four high-voltage devices T1, T2, T3, T4 is optional, e.g., not required.

[0051] The level shifter 100 can therefore be used in an embedded flash module, thus reducing the silicon area required for the embedded flash module. The flash module can be a non-volatile flash memory.

[0052] Fig. Figure 2 shows timing diagrams of voltage levels in a level converter according to various embodiments. The timing diagrams shown in Fig. Figure 2 illustrates the underlying operating principle of a level converter in various embodiments without limiting it to the underlying embodiment. The level converter can be configured according to an embodiment of a level converter described above or below, such as, for example, in Fig. 1 is described.

[0053] In a first time diagram 200, the voltage level at the low supply voltage terminal V(LS) and the voltage level at the high supply voltage terminal V(HS) are illustrated.

[0054] In a second time diagram 210, the voltage level at the cascode gate bias terminals V(C) is illustrated.

[0055] In a third time diagram 220, the voltage level at the first input terminal V(I1) and the voltage level at the second input terminal V(I2) are illustrated.

[0056] In a fourth time diagram 230, the voltage level at the first output terminal is illustrated.

[0057] The voltage level V(C) at the cascode gate bias remains approximately constant and above 0 V during this time, e.g., at about 5 V. The voltage level at the second input terminal V(I2) is approximately the inverse of the voltage level at the first input terminal V(11). The maximum voltage level at the input terminals V(11) and V(I2) can be about 5 V, i.e., a low voltage value.

[0058] The latch is set to a voltage level V(O_t1) at t1 by increasing the voltage level at the first input terminal V(I1) and decreasing the voltage level at the second input terminal V(I2). This means that the logic state correlated with the voltage level is stored in latch 150. Therefore, the voltage level at the output terminal V(O) rises to approximately the voltage level proportional to the voltage at the input terminal V(I1) and / or the high supply voltage V(HS).

[0059] The voltage level at the low supply voltage terminal V(LS) can be a first value before, during, and after the level shifter is set at t1. The first value can be, for example, 0 V. The voltage level at the high supply voltage terminal V(HS) can be a second value before, during, and after the level shifter is set at t1. The second value can be a value large enough to distinguish the first value from the second value, for example, at least 3 V, or approximately 5 V. That is, the difference between the first and second values ​​can be approximately 5 V. In general, the difference between the low and high supply voltage levels can be less than or equal to an average voltage level, such as the voltage level at the cascode bias terminal.

[0060] At a second time point t2, the voltage level at the high supply voltage terminal V(HS) can be increased from the second value to a third value. The third value can be large enough for the transistors of latch 204 to maintain the voltage difference between the high supply voltage terminal and the low supply voltage terminal. That is, the third value can produce a maximum voltage difference, e.g., approximately 8 V. Increasing the voltage level to the third value at t2 can cause an increase in the voltage level at the first output terminal V(O_t2), e.g., to a value proportional to the voltage level of the third value, e.g., approximately 8 V. That is, the voltage at the first output O is shifted to a higher level, corresponding to a higher voltage of the stored logic state.

[0061] At a third time point t3, the voltage level at the low supply voltage terminal V(LS) can be increased from the first value to a fourth value. This means that the voltage level at the low supply voltage terminal follows the voltage level at the high supply voltage terminal. The fourth value can be large enough to distinguish the third value from the fourth value, for example, about 3 V. That is, the difference between the third and fourth values ​​can be approximately 3 V. Increasing the voltage level to the fourth value at t3 may not cause an increase in the voltage level at the first output terminal V(O_t3). This means that the voltage level of the stored logical state, in this example a logical "1", remains unchanged.However, if the stored logic state were a logic "0", the voltage level at output terminal O at t3 would rise to approximately the voltage level of the low-supply terminal. This rise to the third value causes the latch to lock itself. This means that a decrease in the voltage level at the first input terminal might not result in a change in the voltage level at any of the output terminals.

[0062] At a fourth time point t4, the voltage level at the high supply voltage terminal V(HS) can be increased from the third value to a fifth value. The fifth value can be large enough for the level shifter transistors 208 to maintain a voltage difference between the high supply voltage terminal and the low supply voltage terminal. This means that the fifth value can produce a maximum voltage difference, e.g., about 8 V. Thus, the fifth value can be, for example, 13 V, since the voltage level at the low supply can be the third value, e.g., 5 V. The increase of the voltage level to the fifth value at t4 can cause an increase in the voltage level at the first output terminal V(O_t4), e.g., to a value corresponding to the voltage level of the fifth value, e.g., about 13 V. This means that the voltage at the first output O is shifted to an even higher level.However, the content, and more specifically the logical state, stored in the latch remains as originally stored.

[0063] The voltage level at the output terminal can perhaps be further increased in a similar process as described to set a predetermined voltage level at the output terminal. The predetermined voltage level may depend on the specific application using the described level conversion, e.g., for non-volatile flash memory. Therefore, higher or lower voltage levels can be used, e.g., up to approximately 20 V or more, e.g., up to 50 to 100 V.

[0064] In various embodiments, the voltage levels of the low and high supply voltages at t2, t3, and / or t4 can be increased simultaneously or at different times. In the example, the voltage level at the low supply voltage terminal at t3 is increased before the voltage level at the high supply voltage terminal at t4 is increased. Alternatively, the voltage level at the low supply voltage terminal at t3 can be increased after the voltage level at the high supply voltage terminal at t4 has been increased, provided the difference between the voltage levels V(HS) - V(LS) is less than a predetermined value. The predetermined value can be the maximum voltage difference that can be maintained by the latch transistors.

[0065] From t1 to t3, the voltage levels at the cascode bias terminal and the input terminals V(C), V(I1), and V(I2) remain approximately constant or unchanged. The constant voltage level at the cascode bias terminal V(C) biases the transistors of the latch. Therefore, due to this bias, the latch, and consequently the logic state stored in the latch, becomes self-locked when the voltage level at the low-supply terminal is increased at t3. Starting at t3, the input terminals are isolated from the output terminals. Therefore, the voltage levels at the input terminals V(I1) and V(I2) can be changed without affecting the voltage level at the output terminal V(I0).

[0066] In the example that is in Fig. As shown in Figure 2, in the fourth time interval, which begins at t4 with the rise of the high supply voltage, the low-voltage range (i.e., logic "0") extends from approximately 0 V to approximately 5 V, and the high-voltage range (i.e., logic "1") extends from approximately 5 V to approximately 13 V. The maximum voltage across the HV transistors of Latch 150 is limited to approximately 8 V in this example due to the parallel rise of the low and high supply voltages. The maximum voltage across the HV transistors can be higher or lower than 8 V, depending on the design of the HV transistors used for Latch 150. The parallel rise can be understood as the low supply voltage following the high supply voltage. The parallel rise essentially refers to the voltage levels. The rise of the voltage levels of the low and high supply voltages can be parallel or staggered in time.

[0067] Thus, the voltage level at the output terminal can be shifted to a higher level than that seen by any transistor within the circuit by increasing the low and high supply voltages in parallel.

[0068] Furthermore, the functionality of Latch 150 allows the input of input terminals I1 and I2 to be isolated after setting the state of Latch 150 (low / high) at t1, without losing the stored logical state in Latch 150. That is, Latch 150 is self-blocking while the voltage level at the low supply voltage terminal LS is shifted upwards, and self-unblocking while the voltage level at the low supply voltage terminal LS is shifted downwards.

[0069] This means that the latch can be self-unlocked by reducing the voltage level at the low supply voltage terminal and the high supply voltage terminal to the first and second values, respectively, in a voltage level reduction procedure that is the reverse of the increase described above.

[0070] Example 1, which relates to Fig. 1 and Fig. The component described in section 2 is a level shifter 100. The level shifter 100 comprises a low supply voltage terminal LS, a high supply voltage terminal HS, at least one input terminal I1, I2, at least one output terminal O, O', and a latch 150. The latch 150 is designed to: store a predetermined logical state by setting a memory node to a (first) voltage level in response to receiving a predetermined voltage level at the at least one input terminal, changing the voltage level at the memory node in response to receiving one or more changed voltages at the low supply voltage terminal and / or at the high supply voltage terminal, and outputting the predetermined logical state with the changed (second) voltage level from the memory node to the at least one output.

[0071] The predetermined logical state can be "0" or "1". The memory node for the first input I1 can be a node connected to output O, e.g., node K4, K6. The memory node for the second input I2 can be a node connected to output O', e.g., node K3, K5. The predetermined voltage level at the at least one input terminal can be, for example, approximately 0 V (logical "0") or approximately 5 V (logical "1"), or similar. Thus, the (first) voltage level at the memory node can be approximately 0 V or 5 V.

[0072] Changing the voltage level at the memory node can be either an increase or a decrease. However, the stored logical state remains in the memory node. This means that Latch 150 is locked during the change. Changing one or more voltages at the low supply voltage (LS) terminal and / or the high supply voltage (HS) terminal can each be either an increase or a decrease. The voltage is changed in such a way that the voltage difference between the voltage level at the low supply voltage (LS) terminal and the high supply voltage (HS) terminal is lower than a first predetermined value, such as 8 V, meaning it correlates with a maximum voltage that can be maintained by the transistors of Latch 150.Additionally, the voltage difference can be greater than a second predetermined value that is correlated to reliably distinguish a logical state "0" from a logical state "1" by comparing the respective voltage levels, e.g. 3 V.

[0073] The output of the predetermined logical state with the changed (second) voltage level from the memory node to the at least one output can be provided by an electrical connection between the memory node and the output terminal.

[0074] Thus, a level shifter for converting a voltage level, according to various embodiments, requires fewer high-voltage devices than a conventional level shifter. Furthermore, cascoding the low supply voltage in the latch is optional, for example, not required.

[0075] In Example 2, the subject of Example 1 can further include the latch 150 comprising several transistors T1, T2, T3, T4, and the level shifter 100 comprising at least one bias terminal C1, C2. The bias terminal C1, C2 is designed to bias transistors T1, T2, T3, T4 in response to receiving a voltage at the at least one bias terminal C1, C2. In this way, the voltage level of the output terminal O of the level shifter 100 can be shifted to approximately the voltage level of the high supply voltage, and the latch 150 retains the content, which is the logic state at the output terminal O.

[0076] In Example 3, the subject of Example 1 or 2 may further comprise the level converter 100 comprising a first output terminal O' coupled to the memory node K3, K5 / K4, K6, and a second output terminal O' coupled to another memory node K3, K5 / K4, K6, wherein the latch 150 is configured such that the voltage level at the first output terminal O corresponds to a first logical state and the voltage level at the second output terminal O' corresponds to a second logical state, wherein the second logical state is an inverted logical state with respect to the first logical state.

[0077] In Example 4, the subject matter of Examples 1 to 3 can further include the level shifter 100 comprising a bias terminal C1, C2, which is connected to the latch 150 such that at least a portion of the latch 150 can be biased by a voltage applied to the bias terminals C1, C2. The portions of the latch 150 that are biased by a voltage at the bias terminals C1, C2 can include the gate / base and / or drain / collector terminals of the latch's transistors, e.g., from competing paths, such as via one or more nodes. This enables self-locking and self-unlocking of the latch.

[0078] In Example 5, the subject of Example 3 may further include the level converter 100 comprising a first bias terminal C1 directly coupled to the second output terminal O' and a second bias terminal C2 directly coupled to the first output terminal O.

[0079] In Example 6, the subject of Example 5 may further include the level converter 100 comprising a first input terminal I1 and a second input terminal I2, wherein the first input terminal I1 is coupled to the first bias terminal C1 and the second input terminal I2 is coupled to the second bias terminal C2.

[0080] In Example 7, the subject matter of Example 5 can further include the level shifter 100 comprising a first input terminal I1 and a second input terminal I2, wherein the first input terminal I1 is coupled to the first bias terminal C1 via a low-voltage device T8, and the second input terminal I2 is coupled to the second bias terminal C2 via another low-voltage device T7. A low-voltage device can be a transistor having a maximum output voltage of about 5 V.

[0081] In Example 8, the subject of Examples 1 to 7 may further include the level converter 100 comprising a low-voltage transistor T7, T8, which is directly connected to the at least one input terminal I1, I2.

[0082] In Example 9, the subject matter of Examples 4 to 8 may further include that at least one bias connection C1, C2 is a cascode bias connection C1, C2.

[0083] In Example 10, the subject matter of Examples 4 to 9 may further include the fact that the at least one bias terminal C1, C2 is directly connected to the gate or base terminals of transistors T1, T2, T3, T4 of latch 150.

[0084] In Example 11, the subject matter of Examples 4 to 10 may further include the fact that the Latch 150 comprises several high-voltage transistors. A high-voltage device may be a transistor that has a maximum output voltage of more than approximately 5 V.

[0085] In Example 12, the subject of Examples 1 to 11 may further include the fact that Latch 150 comprises a first path and a second path that competes with the first path with respect to the stored logical state.

[0086] In Example 13, the subject matter of Example 12 may further include the level converter 100 comprising at least one bias terminal C1, C2, wherein the gate or base terminals of the transistors T1, T2, T3, T4 of the first and second paths are connected to the at least one bias terminal C1, C2.

[0087] In Example 14, the subject of Examples 12 or 13 may further include the first and second paths comprising a p-type transistor and an n-type transistor, respectively.

[0088] Example 15, which relates to Fig. 1 and Fig.The method described in Section 2 is for operating a level shifter 100. The level shifter 100 can be configured according to an example or embodiment described above. The method comprises: setting the latch 150 by inputting a logic state into the latch 150, increasing the voltage level at the low supply voltage terminal LS from a first voltage level to a second voltage level different from the first level, increasing the voltage level at the high supply voltage terminal HS from a third voltage level to a fourth voltage level different from the third level, and outputting the content in the latch 150 that has the fourth voltage level.Receiving a voltage with a predetermined voltage level at the at least one input terminal I1, I2; setting a voltage level at the storage node K3, K5 / K4, K6 in response to the received predetermined voltage level; receiving one or more voltages at the low supply voltage terminal LS and / or at the high supply voltage terminal HS with one or more modified voltage levels; changing the voltage level at the storage node K3, K5 / K4, K6 in response to the one or more received modified voltage levels; and outputting the voltage with the modified voltage level from the storage node K3, K5 / K4, K6 to the at least one output. The change in voltage refers to an increase or decrease of the respective voltage level.

[0089] In Example 16, the subject of Example 15 may further include changing the voltage level of the voltage at the high supply voltage terminal HS before changing the voltage level of the voltage at the low supply voltage terminal LS.

[0090] In Example 17, the subject of Examples 15 or 16 may further comprise several changes to the one or more voltage levels at the low supply voltage terminal and / or the high supply voltage terminal until the voltage is output with the changed voltage level.

[0091] In Example 18, the subject matter of Examples 15 to 17 can further comprise that the latch 150 includes several transistors and that the level shifter 100 includes at least one bias terminal C1, C2, wherein the at least one bias terminal C1, C2 is directly connected to the gates of transistors T1, T2, T3, T4 of the latch 150. The method further comprises setting the voltage level at the bias terminal C1, C2 to bias the transistors T1, T2, T3, T4 of the latch 150.

[0092] In Example 19, the subject matter of Examples 15 to 18 may further include the latch 150 being designed such that the voltage level at the bias terminal C1, C2 remains constantly above approximately 0 V, at least after the voltage level has been set until the output. The method further comprises providing a voltage at the bias terminal C1, C2 that has a voltage level above approximately 0 V.

[0093] In Example 20, the subject matter of Examples 15 to 19 may further include the latch 150 being designed such that the gate or base terminals of transistors T1, T2, T3, T4 of the latch 150 are biased at least after the voltage level has been set until output. The method further includes biasing the gate or base terminals of the transistors at least after the voltage level has been set until output.

[0094] Although the invention has been shown and described, particularly with reference to specific embodiments, it should be understood by those skilled in the field that various modifications in form and detail can be made without departing from the concept and scope of the invention as defined by the accompanying claims. The scope of the invention is therefore specified by the accompanying claims, and thus all modifications falling within the meaning and equivalence of the claims are intended to be included.

[0095] In particular, the devices such as transistors of the level converter according to various embodiments are not limited to a specific design, but can be selected depending on the intended application of the level converter and the voltage levels available.

Claims

[1] Level converter (100) comprising the following: a connection for low supply voltage (LS), a connection for high supply voltage (HS), at least one input port (I1, I2), at least one output port (O, O'), and a latch (150) comprising several transistors (T1, T2, T3, T4) and designed to do the following: • Storing a predetermined logical state by setting a memory node (K3, K5 / K4, K6) to a voltage level in response to receiving a predetermined voltage level at the at least one input terminal (I1, I2), where the voltage level at the low supply voltage (LS) terminal is a first value and the voltage level at the high supply voltage (HS) terminal is a second value. • Changing the voltage level at the storage node (K3, K5 / K4, K6) in response to receiving one or more changed voltage levels at the low supply voltage (LS) and high supply voltage (HS) terminals, and • Outputting the predetermined logical state with the changed voltage level from the memory node (K3, K5 / K4, K6) to at least one output (O, O'), • where changing the voltage level at the storage node exhibits: • Increasing the voltage level at the high supply voltage terminal from the second value to a third value; • then increase the voltage level at the low supply voltage terminal from the first value to a fourth value; • then increase the voltage level at the high supply voltage (HS) terminal from the third value to a fifth value, • where the fifth value is chosen such that a voltage difference between the fifth value and the fourth value is just maintained by the transistors (T1, T2, T3, T4). [2] Level converter (100) according to claim 1, wherein the level converter (100) comprises at least one bias terminal (C1, C2), wherein the bias terminal (C1, C2) is designed to bias the transistors (T1, T2, T3, T4) in response to receiving a voltage at the at least one bias terminal (C1, C2). [3] Level converter (100) according to claim 1 or 2, wherein the level converter (100) comprises a first output terminal (O) coupled to the memory node (K4, K6) and a second output terminal (O') coupled to a further memory node (K3, K5), wherein the latch (150) is configured such that the voltage level at the first output terminal (O) corresponds to a first logical state and the voltage level at the second output terminal (O') corresponds to a second logical state, wherein the second logical state is an inverted logical state with respect to the first logical state. [4] Level converter (100) according to any one of claims 1 to 3, wherein the level converter (100) comprises a bias terminal (C1, C2) which is connected to the latch (150) such that at least a part of the latch (150) can be biased by a voltage applied to the bias terminal (C1, C2). [5] Level converter (100) according to claim 3, wherein the level converter (100) comprises a first bias terminal (C1) coupled to the second output terminal (O') and a second bias terminal (C2) coupled to the first output terminal (O). [6] Level converter (100) according to claim 5, wherein the level converter (100) comprises a first input terminal (11) and a second input terminal (I2), wherein the first input terminal (11) is coupled to the first bias terminal (C1) and the second input terminal (I2) is coupled to the second bias terminal (C2). [7] Level converter (100) according to claim 5, wherein the level converter (100) comprises a first input terminal (11) and a second input terminal (I2), wherein the first input terminal (11) is coupled to the first bias terminal (C1) via a low-voltage device and the second input terminal (I2) is coupled to the second bias terminal (C2) via a further low-voltage device. [8] Level converter (100) according to any one of claims 1 to 7, wherein the level converter (100) comprises a low-voltage transistor which is directly connected to the at least one input terminal (I1, I2). [9] Level converter (100) according to any one of claims 4 to 8, wherein at least one bias connection (C1, C2) is a cascode bias connection. [10] Level shifter (100) according to any one of claims 4 to 9, wherein the at least one bias terminal (C1, C2) is connected to the gate or base terminals of the transistors (T1, T2, T3, T4) of the latch (150). [11] Level shifter (100) according to any one of claims 4 to 10, wherein the latch (150) comprises several high-voltage transistors. [12] Level converter (100) according to any one of claims 1 to 11, wherein the latch (150) comprises a first path and a second path which competes with the first path with respect to the stored logical state. [13] Level shifter (100) according to claim 12, wherein the level shifter (100) comprises at least one bias terminal (C1, C2), wherein the gate or base terminals of the transistors of the first and second path are connected to the at least one bias terminal (C1, C2). [14] Level shifter (100) according to claim 12 or 13, wherein the first and second paths each comprise a p-type transistor and an n-type transistor. [15] Method for operating a level converter (100) wherein the level converter (100) comprises the following: a connection for low supply voltage (LS), a connection for high supply voltage (HS), at least one input port (I1, I2), at least one output port (O, O'), and a latch (150) comprising several transistors (T1, T2, T3, T4) and designed to do the following: • Storing a predetermined logical state by setting a memory node (K3, K5 / K4, K6) to a voltage level in response to receiving a voltage with a predetermined voltage level at the at least one input terminal (I1, I2), where the voltage level at the low supply voltage (LS) terminal is a first value and the voltage level at the high supply voltage (HS) terminal is a second value, • Changing the voltage level at the storage node (K3, K5 / K4, K6) in response to receiving one or more changed voltage levels at the low supply voltage (LS) and high supply voltage (HS) terminals, and • Outputting the predetermined logical state with the changed voltage level from the memory node (K3, K5 / K4, K6) to the at least one output (O, O'), wherein the method comprises the following: • Receiving a voltage with a predetermined voltage level at at least one input terminal (I1, I2), • Setting a voltage level at the storage node (K3, K5 / K4, K6) in response to the received predetermined voltage level, • Receiving one or more voltages at the low supply voltage (LS) terminal and at the high supply voltage (HS) terminal with one or more modified voltage levels, • Changing the voltage level at the storage node (K3, K5 / K4, K6) in response to one or more received changed voltage levels, and • Outputting the voltage with the modified voltage level from the memory node (K3, K5 / K4, K6) to at least one output, • where changing the voltage level at the storage node exhibits: • Increasing the voltage level at the high supply voltage (HS) terminal from the second value to a third value; • then increase the voltage level at the low supply voltage (LS) terminal from the first value to a fourth value; • then increase the voltage level at the high supply voltage (HS) terminal from the third value to a fifth value, • where the fifth value is chosen such that a voltage difference between the fifth value and the fourth value is just maintained by the transistors (T1, T2, T3, T4). [16] Method according to claim 15, wherein the method further comprises: changing the voltage level of the voltage at the high supply voltage (HS) terminal before changing the voltage level of the voltage at the low supply voltage (LS) terminal. [17] Method according to claim 15 or 16, wherein the method further comprises several changes of the one or more voltage levels at the low supply voltage (LS) terminal and the high supply voltage (HS) terminal until the voltage is output with the changed voltage level. [18] Method according to any one of claims 15 to 17, wherein the level shifter (100) comprises at least one bias terminal (C1, C2), wherein the at least one bias terminal (C1, C2) is connected to the gates of the transistors of the latch (150), wherein the method further comprises: Setting the voltage level at the bias terminal (C1, C2) to bias the transistors (T1, T2, T3, T4) of the latch (150). [19] Method according to any one of claims 15 to 18, wherein the latch (150) is designed such that the voltage level at the bias terminal (C1, C2) remains constant above approximately 0 V at least after the voltage level has been set until the output, wherein the method further comprises: Providing a voltage at the bias terminal (C1, C2) that has a voltage level above approximately 0 V. [20] Method according to any one of claims 15 to 19, wherein the latch (150) is designed such that the gate or base terminals of the transistors (T1, T2, T3, T4) of the latch (150) are biased at least after the voltage level has been set until output, wherein the method further comprises: Preloading the gate or base terminals of the transistors (T1, T2, T3, T4) at least after setting the voltage level until output.

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