METHOD FOR THE TRAINING OF FIN FIELD DEFECT TRANSISTORS

The method of forming semiconductor strips with sacrificial oxide layers and doping processes addresses the complexity of FinFET manufacturing, resulting in improved performance and efficiency of FinFETs by optimizing source/drain regions.

DE102016121443B4Active Publication Date: 2026-01-22TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102016121443
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2016-11-01
Filing Date
2016-11-09
Publication Date
2026-01-22
Estimated Expiration
2036-11-09

AI Technical Summary

Technical Problem

The complexity of manufacturing Fin field-effect transistors (FinFETs) is high due to the challenges in forming semiconductor fins, implanting dopants, and creating source/drain regions, which affect the performance and efficiency of these devices.

Method used

A method involving the formation of semiconductor strips with sacrificial oxide layers, followed by doping and annealing processes to create diffused regions, and subsequent epitaxy to form source/drain regions, optimizing the semiconductor structure for improved performance.

Benefits of technology

This method enhances the performance of FinFETs by reducing resistance and improving the profile of source/drain regions, leading to better device efficiency and manufacturing consistency.

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Abstract

Method for the formation of Fin field-effect transistors, which includes: Etching a semiconductor substrate (20) to form a first trench (26) and a second trench (26), wherein a residual section of the semiconductor substrate between the first trench and the second trench is left as a semiconductor region, and wherein the semiconductor region is a semiconductor base (130) and comprising semiconductor strips (132) arranged above and connected to the semiconductor base; Forming a doped dielectric layer(36) on side walls of the semiconductor region and over a top surface of the semiconductor region, wherein the doped dielectric layer contains a dopant; Filling a dielectric material (50) into the first and second trenches and above the doped dielectric layer (36) to form insulating regions (54), wherein after filling the dielectric material (50) into the first and second trenches, the dielectric material is arranged in the first trench (26) and the second trench (26) above the doped dielectric layer (36); and Performing a tempering process to diffuse the dopant in the doped dielectric layer (36) into the totality of the semiconductor strips (132) and a surface layer of the semiconductor base (130), thereby forming a diffused semiconductor region (52).
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Citation Information

Patent Citations

  • Method of forming lightly doped halo regions and extension regions in a semiconductor device

    DE10058031B4

  • Semiconductor device, multi-gate field effect transistor and method of manufacturing a semiconductor device

    DE102007004789A1

  • Method for manufacturing a Fin-FET unit

    DE102012207913B4

  • Method for forming semiconductor units with fin structures

    DE112013000813T5

  • Methods of forming bulk finfet devices so as to reduce punch through leakage currents

    US20130280883A1